未验证 提交 8015b61f 编写于 作者: 杨熙 提交者: GitHub

[bsp][lpc55sxx] update spi driver (#6986)

* [bsp][lpc55sxx] update spi driver

1. update spi driver, fix pin driver
2. move DMA_Init to board.c

* [bsp][lpc55sxx] formmat code

* [bsp][lpc55sxx] format lpc55s69_nxp_evk board file
上级 7542f780
...@@ -160,7 +160,6 @@ int rt_hw_i2c_init(void) ...@@ -160,7 +160,6 @@ int rt_hw_i2c_init(void)
lpc_obj[i].parent.ops = &i2c_ops; lpc_obj[i].parent.ops = &i2c_ops;
lpc_obj[i].sem = rt_sem_create("sem_i2c", 0, RT_IPC_FLAG_FIFO); lpc_obj[i].sem = rt_sem_create("sem_i2c", 0, RT_IPC_FLAG_FIFO);
DMA_Init(lpc_obj[i].DMA);
DMA_CreateHandle(&lpc_obj[i].dmaHandle, lpc_obj[i].DMA, lpc_obj[i].dma_chl); DMA_CreateHandle(&lpc_obj[i].dmaHandle, lpc_obj[i].DMA, lpc_obj[i].dma_chl);
I2C_MasterTransferCreateHandleDMA(lpc_obj[i].I2C, &lpc_obj[i].i2c_mst_dma_handle, i2c_mst_dma_callback, &lpc_obj[i], &lpc_obj[i].dmaHandle); I2C_MasterTransferCreateHandleDMA(lpc_obj[i].I2C, &lpc_obj[i].i2c_mst_dma_handle, i2c_mst_dma_callback, &lpc_obj[i], &lpc_obj[i].dmaHandle);
......
...@@ -132,7 +132,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] = ...@@ -132,7 +132,7 @@ struct rt_pin_irq_hdr pin_irq_hdr_tab[] =
{-1, 0, RT_NULL, RT_NULL}, {-1, 0, RT_NULL, RT_NULL},
}; };
static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_uint8_t mode)
{ {
int dir; int dir;
uint32_t pin_cfg; uint32_t pin_cfg;
...@@ -191,7 +191,7 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) ...@@ -191,7 +191,7 @@ static void lpc_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
} }
static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_uint8_t value)
{ {
if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
{ {
...@@ -201,7 +201,7 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) ...@@ -201,7 +201,7 @@ static void lpc_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value); GPIO_PinWrite(lpc_pin_map[pin].gpio, lpc_pin_map[pin].gpio_port, lpc_pin_map[pin].gpio_pin, value);
} }
static int lpc_pin_read(rt_device_t dev, rt_base_t pin) static rt_int8_t lpc_pin_read(rt_device_t dev, rt_base_t pin)
{ {
int value; int value;
if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0)) if ((pin > __ARRAY_LEN(lpc_pin_map)) || (pin == 0))
...@@ -259,8 +259,8 @@ void PIN_INT0_IRQHandler(void) ...@@ -259,8 +259,8 @@ void PIN_INT0_IRQHandler(void)
} }
static rt_err_t lpc_pin_attach_irq(struct rt_device *device, static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
rt_int32_t pin, rt_base_t pin,
rt_uint32_t mode, rt_uint8_t mode,
void (*hdr)(void *args), void (*hdr)(void *args),
void *args) void *args)
{ {
...@@ -336,7 +336,7 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device, ...@@ -336,7 +336,7 @@ static rt_err_t lpc_pin_attach_irq(struct rt_device *device,
return RT_EOK; return RT_EOK;
} }
static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_base_t pin)
{ {
int i; int i;
...@@ -359,7 +359,7 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin) ...@@ -359,7 +359,7 @@ static rt_err_t lpc_pin_detach_irq(struct rt_device *device, rt_int32_t pin)
return RT_EOK; return RT_EOK;
} }
static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) static rt_err_t lpc_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint8_t enabled)
{ {
int irqn_type, i; int irqn_type, i;
......
...@@ -7,103 +7,95 @@ ...@@ -7,103 +7,95 @@
* Date Author Notes * Date Author Notes
* 2019-07-15 Magicoe The first version for LPC55S6x * 2019-07-15 Magicoe The first version for LPC55S6x
*/ */
#include "drv_spi.h" #include "rtdevice.h"
#include "fsl_common.h" #include "fsl_common.h"
#include "fsl_iocon.h" #include "fsl_iocon.h"
#include "fsl_spi.h" #include "fsl_spi.h"
#include "fsl_spi_dma.h"
#if defined(BSP_USING_SPIBUS0) || \ enum
defined(BSP_USING_SPIBUS1) || \ {
defined(BSP_USING_SPIBUS2) || \ #ifdef BSP_USING_SPI3
defined(BSP_USING_SPIBUS3) || \ SPI3_INDEX,
defined(BSP_USING_SPIBUS4) || \ #endif
defined(BSP_USING_SPIBUS5) || \ #ifdef BSP_USING_SPI8
defined(BSP_USING_SPIBUS6) || \ SPI8_INDEX,
defined(BSP_USING_SPIBUS7) || \
defined(BSP_USING_SPIBUS8)
#if defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL
#error "Please don't define 'FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL'!"
#endif #endif
};
struct lpc_spi struct lpc_spi
{ {
SPI_Type *base; struct rt_spi_bus parent;
struct rt_spi_configuration *cfg; SPI_Type *SPIx;
SYSCON_RSTn_t spi_rst; clock_attach_id_t clock_attach_id;
clock_ip_name_t clock_name;
DMA_Type *DMAx;
uint8_t tx_dma_chl;
uint8_t rx_dma_chl;
dma_handle_t dma_tx_handle;
dma_handle_t dma_rx_handle;
spi_dma_handle_t spi_dma_handle;
rt_sem_t sem;
char *device_name;
}; };
static uint32_t lpc_get_spi_freq(SPI_Type *base) static struct lpc_spi lpc_obj[] =
{ {
uint32_t freq = 0; #ifdef BSP_USING_SPI3
{
.SPIx = SPI3,
.clock_attach_id = kMAIN_CLK_to_FLEXCOMM3,
.clock_name = kCLOCK_FlexComm3,
.device_name = "spi3",
#if defined(BSP_USING_SPIBUS0) .DMAx = DMA0,
if(base == SPI0) .tx_dma_chl = 9,
{ .rx_dma_chl = 8,
freq = CLOCK_GetFlexCommClkFreq(0);
}
#endif
#if defined(BSP_USING_SPIBUS1) },
if(base == SPI1)
{
freq = CLOCK_GetFlexCommClkFreq(1);
}
#endif #endif
#ifdef BSP_USING_SPI8
{
.SPIx = SPI8,
.clock_attach_id = kMAIN_CLK_to_HSLSPI,
.clock_name = kCLOCK_Hs_Lspi,
.device_name = "spi8",
#if defined(BSP_USING_SPIBUS2) .DMAx = DMA0,
if(base == SPI2) .tx_dma_chl = 3,
{ .rx_dma_chl = 2,
freq = CLOCK_GetFlexCommClkFreq(2);
}
#endif
#if defined(BSP_USING_SPIBUS3) },
if(base == SPI3)
{
freq = CLOCK_GetFlexCommClkFreq(3);
}
#endif #endif
};
#if defined(BSP_USING_SPIBUS4)
if(base == SPI4)
{
freq = CLOCK_GetFlexCommClkFreq(4);
}
#endif
#if defined(BSP_USING_SPIBUS5) struct lpc_sw_spi_cs
if(base == SPI5) {
{ rt_uint32_t pin;
freq = CLOCK_GetFlexCommClkFreq(5); };
}
#endif
#if defined(BSP_USING_SPIBUS6)
if(base == SPI6)
{
freq = CLOCK_GetFlexCommClkFreq(6);
}
#endif
#if defined(BSP_USING_SPIBUS7) static uint32_t lpc_get_spi_freq(SPI_Type *base)
if(base == SPI7) {
uint32_t freq = 0;
if(base == SPI3)
{ {
freq = CLOCK_GetFlexCommClkFreq(7); freq = CLOCK_GetFlexCommClkFreq(kCLOCK_FlexComm3);
} }
#endif
/* High Speed SPI - 50MHz */
#if defined(BSP_USING_SPIBUS8)
if(base == SPI8) if(base == SPI8)
{ {
freq = CLOCK_GetHsLspiClkFreq(); freq = CLOCK_GetFlexCommClkFreq(kCLOCK_Hs_Lspi);
} }
#endif
return freq; return freq;
} }
...@@ -111,30 +103,12 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) ...@@ -111,30 +103,12 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
{ {
spi_master_config_t masterConfig = {0}; spi_master_config_t masterConfig = {0};
RT_ASSERT(cfg != RT_NULL);
if(cfg->data_width != 8 && cfg->data_width != 16)
{
return (-RT_EINVAL);
}
SPI_MasterGetDefaultConfig(&masterConfig); SPI_MasterGetDefaultConfig(&masterConfig);
#if defined(BSP_USING_SPIBUS8) if(cfg->data_width != 8 && cfg->data_width != 16)
if(base == SPI8)
{
if(cfg->max_hz > 50*1000*1000)
{
cfg->max_hz = 50*1000*1000;
}
}
#else
if(cfg->max_hz > 12*1000*1000)
{ {
cfg->max_hz = 12*1000*1000; cfg->data_width = 8;
} }
#endif
masterConfig.baudRate_Bps = cfg->max_hz; masterConfig.baudRate_Bps = cfg->max_hz;
...@@ -179,183 +153,106 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg) ...@@ -179,183 +153,106 @@ static rt_err_t lpc_spi_init(SPI_Type *base, struct rt_spi_configuration *cfg)
return RT_EOK; return RT_EOK;
} }
rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin) rt_err_t rt_hw_spi_device_attach(const char *bus_name, const char *device_name, rt_uint32_t pin)
{ {
rt_err_t ret = RT_EOK; rt_err_t ret = RT_EOK;
struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); struct rt_spi_device *spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device));
RT_ASSERT(spi_device != RT_NULL); struct lpc_sw_spi_cs *cs_pin = (struct lpc_sw_spi_cs *)rt_malloc(sizeof(struct lpc_sw_spi_cs));
cs_pin->pin = pin;
rt_pin_mode(pin, PIN_MODE_OUTPUT); rt_pin_mode(pin, PIN_MODE_OUTPUT);
rt_pin_write(pin, PIN_HIGH); rt_pin_write(pin, PIN_HIGH);
ret = rt_spi_bus_attach_device_cspin(spi_device, device_name, bus_name, pin, NULL); ret = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin);
return ret; return ret;
} }
static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg) static rt_err_t spi_configure(struct rt_spi_device *device, struct rt_spi_configuration *cfg)
{ {
rt_err_t ret = RT_EOK; rt_err_t ret = RT_EOK;
struct lpc_spi *spi = RT_NULL; struct lpc_spi *spi = RT_NULL;
RT_ASSERT(cfg != RT_NULL);
RT_ASSERT(device != RT_NULL);
spi = (struct lpc_spi *)(device->bus->parent.user_data); spi = (struct lpc_spi *)(device->bus->parent.user_data);
spi->cfg = cfg; ret = lpc_spi_init(spi->SPIx, cfg);
ret = lpc_spi_init(spi->base, cfg);
return ret; return ret;
} }
#define SPISTEP(datalen) (((datalen) == 8) ? 1 : 2)
static rt_uint32_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message) static void SPI_MasterUserCallback(SPI_Type *base, spi_dma_handle_t *handle, status_t status, void *userData)
{
struct lpc_spi *spi = (struct lpc_spi*)userData;
rt_sem_release(spi->sem);
}
static rt_ssize_t spixfer(struct rt_spi_device *device, struct rt_spi_message *message)
{ {
uint32_t length; int i;
spi_transfer_t transfer = {0};
RT_ASSERT(device != RT_NULL); RT_ASSERT(device != RT_NULL);
RT_ASSERT(device->bus != RT_NULL); RT_ASSERT(device->bus != RT_NULL);
RT_ASSERT(device->bus->parent.user_data != RT_NULL); RT_ASSERT(device->bus->parent.user_data != RT_NULL);
struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data); struct lpc_spi *spi = (struct lpc_spi *)(device->bus->parent.user_data);
int cs_pin = device->cs_pin; struct lpc_sw_spi_cs *cs = device->parent.user_data;
if(message->cs_take) if(message->cs_take)
{ {
rt_pin_write(cs_pin, PIN_LOW); rt_pin_write(cs->pin, PIN_LOW);
} }
length = message->length; transfer.dataSize = message->length;
const rt_uint8_t *txData = (uint8_t *)(message->send_buf); transfer.rxData = (uint8_t *)(message->recv_buf);
rt_uint8_t *rxData = (uint8_t *)(message->recv_buf); transfer.txData = (uint8_t *)(message->send_buf);
transfer.configFlags = kSPI_FrameAssert;
rt_kprintf("*** spi send %d\r\n", length);
while (length) // if(message->length < MAX_DMA_TRANSFER_SIZE)
if(0)
{ {
/* clear tx/rx errors and empty FIFOs */ SPI_MasterTransferBlocking(spi->SPIx, &transfer);
spi->base->FIFOCFG |= SPI_FIFOCFG_EMPTYTX_MASK | SPI_FIFOCFG_EMPTYRX_MASK;
spi->base->FIFOSTAT |= SPI_FIFOSTAT_TXERR_MASK | SPI_FIFOSTAT_RXERR_MASK;
spi->base->FIFOWR = *txData | 0x07300000;
/* wait if TX FIFO of previous transfer is not empty */
while ((spi->base->FIFOSTAT & SPI_FIFOSTAT_RXNOTEMPTY_MASK) == 0) {
}
if(rxData != NULL)
{
*rxData = spi->base->FIFORD;
rxData += SPISTEP(spi->cfg->data_width);
}
txData += SPISTEP(spi->cfg->data_width);;
length--;
} }
else
if(message->cs_release)
{ {
rt_pin_write(cs_pin, PIN_HIGH); uint32_t block, remain;
} block = message->length / DMA_MAX_TRANSFER_COUNT;
remain = message->length % DMA_MAX_TRANSFER_COUNT;
return (message->length - length); for(i=0; i<block; i++)
} {
transfer.dataSize = DMA_MAX_TRANSFER_COUNT;
#if defined(BSP_USING_SPIBUS0) if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
static struct lpc_spi spi0 = if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
{
.base = SPI0
};
static struct rt_spi_bus spi0_bus =
{
.parent.user_data = &spi0
};
#endif
#if defined(BSP_USING_SPIBUS1) SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
static struct lpc_spi spi1 = rt_sem_take(spi->sem, RT_WAITING_FOREVER);
{ }
.base = SPI1
};
static struct rt_spi_bus spi1_bus =
{
.parent.user_data = &spi1
};
#endif
#if defined(BSP_USING_SPIBUS2) if(remain)
static struct lpc_spi spi2 = {
{ transfer.dataSize = remain;
.base = SPI2 if(message->recv_buf) transfer.rxData = (uint8_t *)(message->recv_buf + i*DMA_MAX_TRANSFER_COUNT);
}; if(message->send_buf) transfer.txData = (uint8_t *)(message->send_buf + i*DMA_MAX_TRANSFER_COUNT);
static struct rt_spi_bus spi2_bus =
{
.parent.user_data = &spi2
};
#endif
#if defined(BSP_USING_SPIBUS3) SPI_MasterTransferDMA(spi->SPIx, &spi->spi_dma_handle, &transfer);
static struct lpc_spi spi3 = rt_sem_take(spi->sem, RT_WAITING_FOREVER);
{ }
.base = SPI3 }
};
static struct rt_spi_bus spi3_bus =
{
.parent.user_data = &spi3
};
#endif
#if defined(BSP_USING_SPIBUS4)
static struct lpc_spi spi4 =
{
.base = SPI4
};
static struct rt_spi_bus spi4_bus =
{
.parent.user_data = &spi4
};
#endif
#if defined(BSP_USING_SPIBUS5)
static struct lpc_spi spi5 =
{
.base = SPI5
};
static struct rt_spi_bus spi5_bus =
{
.parent.user_data = &spi5
};
#endif
#if defined(BSP_USING_SPIBUS6) if(message->cs_release)
static struct lpc_spi spi6 = {
{ rt_pin_write(cs->pin, PIN_HIGH);
.base = SPI6 }
};
static struct rt_spi_bus spi6_bus =
{
.parent.user_data = &spi6
};
#endif
#if defined(BSP_USING_SPIBUS7) return message->length;
static struct lpc_spi spi7 = }
{
.base = SPI7
};
static struct rt_spi_bus spi7_bus =
{
.parent.user_data = &spi7
};
#endif
#if defined(BSP_USING_SPIBUS8)
static struct lpc_spi spi8 =
{
.base = SPI8
};
static struct rt_spi_bus spi8_bus =
{
.parent.user_data = &spi8
};
#endif
static struct rt_spi_ops lpc_spi_ops = static struct rt_spi_ops lpc_spi_ops =
...@@ -364,76 +261,29 @@ static struct rt_spi_ops lpc_spi_ops = ...@@ -364,76 +261,29 @@ static struct rt_spi_ops lpc_spi_ops =
.xfer = spixfer .xfer = spixfer
}; };
int rt_hw_spi_init(void)
{
#if defined(BSP_USING_SPIBUS0)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM0);
RESET_PeripheralReset(kFC0_RST_SHIFT_RSTn);
spi0.cfg = RT_NULL;
rt_spi_bus_register(&spi0_bus, "spi0", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS1)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM1);
RESET_PeripheralReset(kFC1_RST_SHIFT_RSTn);
spi1.cfg = RT_NULL;
rt_spi_bus_register(&spi1_bus, "spi1", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS2) int rt_hw_spi_init(void)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM2); {
RESET_PeripheralReset(kFC2_RST_SHIFT_RSTn); int i;
spi2.cfg = RT_NULL;
rt_spi_bus_register(&spi2_bus, "spi2", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS3)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM3);
RESET_PeripheralReset(kFC3_RST_SHIFT_RSTn);
spi3.cfg = RT_NULL;
rt_spi_bus_register(&spi3_bus, "spi3", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS4)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM4);
RESET_PeripheralReset(kFC4_RST_SHIFT_RSTn);
spi4.cfg = RT_NULL;
rt_spi_bus_register(&spi4_bus, "spi4", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS5)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM5);
RESET_PeripheralReset(kFC5_RST_SHIFT_RSTn);
spi5.cfg = RT_NULL;
rt_spi_bus_register(&spi5_bus, "spi5", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS6)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM6);
RESET_PeripheralReset(kFC6_RST_SHIFT_RSTn);
spi6.cfg = RT_NULL;
rt_spi_bus_register(&spi6_bus, "spi6", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS7)
CLOCK_AttachClk(kFRO12M_to_FLEXCOMM7);
RESET_PeripheralReset(kFC7_RST_SHIFT_RSTn);
spi7.cfg = RT_NULL;
rt_spi_bus_register(&spi7_bus, "spi7", &lpc_spi_ops);
#endif
#if defined(BSP_USING_SPIBUS8)
CLOCK_AttachClk(kMAIN_CLK_to_HSLSPI);
RESET_PeripheralReset(kHSLSPI_RST_SHIFT_RSTn);
spi8.cfg = RT_NULL;
spi8.spi_rst = kHSLSPI_RST_SHIFT_RSTn;
rt_spi_bus_register(&spi8_bus, "spi8", &lpc_spi_ops);
#endif
for(i=0; i<ARRAY_SIZE(lpc_obj); i++)
{
CLOCK_AttachClk(lpc_obj[i].clock_attach_id);
lpc_obj[i].parent.parent.user_data = &lpc_obj[i];
lpc_obj[i].sem = rt_sem_create("sem_spi", 0, RT_IPC_FLAG_FIFO);
DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
DMA_EnableChannel(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl, kDMA_ChannelPriority3);
DMA_SetChannelPriority(lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl, kDMA_ChannelPriority2);
DMA_CreateHandle(&lpc_obj[i].dma_tx_handle, lpc_obj[i].DMAx, lpc_obj[i].tx_dma_chl);
DMA_CreateHandle(&lpc_obj[i].dma_rx_handle, lpc_obj[i].DMAx, lpc_obj[i].rx_dma_chl);
SPI_MasterTransferCreateHandleDMA(lpc_obj[i].SPIx, &lpc_obj[i].spi_dma_handle, SPI_MasterUserCallback, &lpc_obj[i], &lpc_obj[i].dma_tx_handle, &lpc_obj[i].dma_rx_handle);
rt_spi_bus_register(&lpc_obj[i].parent, lpc_obj[i].device_name, &lpc_spi_ops);
}
return RT_EOK; return RT_EOK;
} }
INIT_BOARD_EXPORT(rt_hw_spi_init); INIT_DEVICE_EXPORT(rt_hw_spi_init);
#endif
/*
* Copyright (c) 2006-2023, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef __DRV_SPI_H__
#define __DRV_SPI_H__
#include <rtthread.h>
#include <rtdevice.h>
int rt_hw_spi_init(void);
rt_err_t lpc_spi_bus_attach_device(const char *bus_name, const char *device_name, rt_uint32_t pin);
#endif
...@@ -192,7 +192,13 @@ CONFIG_RT_MMCSD_STACK_SIZE=1024 ...@@ -192,7 +192,13 @@ CONFIG_RT_MMCSD_STACK_SIZE=1024
CONFIG_RT_MMCSD_THREAD_PREORITY=22 CONFIG_RT_MMCSD_THREAD_PREORITY=22
CONFIG_RT_MMCSD_MAX_PARTITION=16 CONFIG_RT_MMCSD_MAX_PARTITION=16
# CONFIG_RT_SDIO_DEBUG is not set # CONFIG_RT_SDIO_DEBUG is not set
# CONFIG_RT_USING_SPI is not set CONFIG_RT_USING_SPI=y
# CONFIG_RT_USING_SPI_BITOPS is not set
# CONFIG_RT_USING_QSPI is not set
# CONFIG_RT_USING_SPI_MSD is not set
# CONFIG_RT_USING_SFUD is not set
# CONFIG_RT_USING_ENC28J60 is not set
# CONFIG_RT_USING_SPI_WIFI is not set
# CONFIG_RT_USING_WDT is not set # CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set # CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set # CONFIG_RT_USING_SENSOR is not set
...@@ -254,6 +260,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -254,6 +260,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_RT_USING_ULOG is not set # CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set # CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_VAR_EXPORT is not set # CONFIG_RT_USING_VAR_EXPORT is not set
# CONFIG_RT_USING_ADT is not set
# CONFIG_RT_USING_RT_LINK is not set # CONFIG_RT_USING_RT_LINK is not set
# CONFIG_RT_USING_VBUS is not set # CONFIG_RT_USING_VBUS is not set
...@@ -446,6 +453,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -446,6 +453,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_EASYLOGGER is not set # CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set # CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_SEGGER_RTT is not set # CONFIG_PKG_USING_SEGGER_RTT is not set
# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
# CONFIG_PKG_USING_RDB is not set # CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set # CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_LOGMGR is not set # CONFIG_PKG_USING_LOGMGR is not set
...@@ -625,6 +633,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -625,6 +633,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_CW2015 is not set # CONFIG_PKG_USING_CW2015 is not set
# CONFIG_PKG_USING_ICM20608 is not set # CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_PAJ7620 is not set # CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_STHS34PF80 is not set
# #
# touch drivers # touch drivers
...@@ -763,6 +772,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -763,6 +772,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_TETRIS is not set # CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_DONUT is not set # CONFIG_PKG_USING_DONUT is not set
# CONFIG_PKG_USING_COWSAY is not set # CONFIG_PKG_USING_COWSAY is not set
# CONFIG_PKG_USING_MORSE is not set
# CONFIG_PKG_USING_LIBCSV is not set # CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set # CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set # CONFIG_PKG_USING_FASTLZ is not set
...@@ -952,6 +962,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -952,6 +962,7 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# Display # Display
# #
# CONFIG_PKG_USING_ARDUINO_U8G2 is not set # CONFIG_PKG_USING_ARDUINO_U8G2 is not set
# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
# CONFIG_PKG_USING_SEEED_TM1637 is not set # CONFIG_PKG_USING_SEEED_TM1637 is not set
# #
...@@ -981,10 +992,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8 ...@@ -981,10 +992,17 @@ CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set # CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set # CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
# #
# Other # Other
# #
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
# #
# Signal IO # Signal IO
...@@ -1016,13 +1034,16 @@ CONFIG_BSP_USING_UART=y ...@@ -1016,13 +1034,16 @@ CONFIG_BSP_USING_UART=y
CONFIG_BSP_USING_UART0=y CONFIG_BSP_USING_UART0=y
# CONFIG_HW_UART0_BAUDRATE_9600 is not set # CONFIG_HW_UART0_BAUDRATE_9600 is not set
CONFIG_HW_UART0_BAUDRATE_115200=y CONFIG_HW_UART0_BAUDRATE_115200=y
# CONFIG_BSP_USING_UART1 is not set
# CONFIG_BSP_USING_UART2 is not set # CONFIG_BSP_USING_UART2 is not set
CONFIG_BSP_USING_I2C=y CONFIG_BSP_USING_I2C=y
# CONFIG_BSP_USING_I2C1 is not set # CONFIG_BSP_USING_I2C1 is not set
CONFIG_BSP_USING_I2C4=y CONFIG_BSP_USING_I2C4=y
CONFIG_HW_I2C4_BAUDRATE_100kHZ=y CONFIG_HW_I2C4_BAUDRATE_100kHZ=y
# CONFIG_HW_I2C4_BAUDRATE_400kHZ is not set # CONFIG_HW_I2C4_BAUDRATE_400kHZ is not set
# CONFIG_BSP_USING_SPI is not set CONFIG_BSP_USING_SPI=y
CONFIG_BSP_USING_SPI3=y
CONFIG_BSP_USING_SPI8=y
# CONFIG_BSP_USING_ADC is not set # CONFIG_BSP_USING_ADC is not set
CONFIG_BSP_USING_SDIO=y CONFIG_BSP_USING_SDIO=y
CONFIG_BSP_USING_RTC=y CONFIG_BSP_USING_RTC=y
...@@ -1037,6 +1058,7 @@ CONFIG_BSP_USING_LED=y ...@@ -1037,6 +1058,7 @@ CONFIG_BSP_USING_LED=y
CONFIG_BSP_USING_KEY=y CONFIG_BSP_USING_KEY=y
CONFIG_BSP_USING_MMA8562=y CONFIG_BSP_USING_MMA8562=y
CONFIG_BSP_USING_MMA8562I2C="i2c4" CONFIG_BSP_USING_MMA8562I2C="i2c4"
# CONFIG_BSP_USING_ARDUINO is not set
# #
# Board extended module Drivers # Board extended module Drivers
......
...@@ -124,11 +124,11 @@ menu "On-chip Peripheral Drivers" ...@@ -124,11 +124,11 @@ menu "On-chip Peripheral Drivers"
default y default y
if BSP_USING_SPI if BSP_USING_SPI
config BSP_USING_SPIBUS3 config BSP_USING_SPI3
bool "Enable Flexcomm3 as SPI" bool "Enable Flexcomm3 as SPI"
default n default n
config BSP_USING_SPIBUS8 config BSP_USING_SPI8
bool "Enable Flexcomm8 as High Speed SPI" bool "Enable Flexcomm8 as High Speed SPI"
default y default y
endif endif
......
...@@ -203,7 +203,7 @@ void BOARD_BootClockPLL100M(void) ...@@ -203,7 +203,7 @@ void BOARD_BootClockPLL100M(void)
/*!< Set up PLL */ /*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = { const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U), .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
.pllndec = SYSCON_PLL0NDEC_NDIV(4U), .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
...@@ -276,7 +276,7 @@ void BOARD_BootClockPLL150M(void) ...@@ -276,7 +276,7 @@ void BOARD_BootClockPLL150M(void)
/*!< Set up PLL */ /*!< Set up PLL */
CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */ CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */ POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG); POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
const pll_setup_t pll0Setup = { const pll_setup_t pll0Setup = {
.pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U), .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(53U) | SYSCON_PLL0CTRL_SELP(31U),
.pllndec = SYSCON_PLL0NDEC_NDIV(8U), .pllndec = SYSCON_PLL0NDEC_NDIV(8U),
......
...@@ -318,12 +318,23 @@ void BOARD_InitPins(void) ...@@ -318,12 +318,23 @@ void BOARD_InitPins(void)
/* Select Digital mode. /* Select Digital mode.
* : Digital mode, digital input is enabled. */ * : Digital mode, digital input is enabled. */
| IOCON_PIO_DIGIMODE(PIO1_7_DIGIMODE_DIGITAL)); | IOCON_PIO_DIGIMODE(PIO1_7_DIGIMODE_DIGITAL));
/* I2C4 */ /* I2C4 */
IOCON_PinMuxSet(IOCON, 1U, 20, 5 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); IOCON_PinMuxSet(IOCON, 1U, 20, 5 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI);
IOCON_PinMuxSet(IOCON, 1U, 21, 5 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); IOCON_PinMuxSet(IOCON, 1U, 21, 5 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI);
/* FC3 SPI */
IOCON_PinMuxSet(IOCON, 0, 2, 1 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* MISO */
IOCON_PinMuxSet(IOCON, 0, 3, 1 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* MOSI */
// IOCON_PinMuxSet(IOCON, 0, 4, 8 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* CS */
IOCON_PinMuxSet(IOCON, 0, 6, 1 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* SCK */
/* FC8 SPI */
IOCON_PinMuxSet(IOCON, 1, 3, 6 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* MISO */
IOCON_PinMuxSet(IOCON, 0, 26, 9 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* MOSI */
IOCON_PinMuxSet(IOCON, 1, 2, 6 | IOCON_PIO_MODE_INACT | IOCON_PIO_SLEW_STANDARD | IOCON_PIO_INV_DI | IOCON_PIO_DIGITAL_EN | IOCON_PIO_OPENDRAIN_DI); /* SCK */
} }
/*********************************************************************************************************************** /***********************************************************************************************************************
* EOF * EOF
......
/* /*
* Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2006-2023, RT-Thread Development Team
* Copyright (c) 2019-2020, Arm Limited. All rights reserved. * Copyright (c) 2019-2020, Arm Limited. All rights reserved.
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
...@@ -52,6 +52,9 @@ void rt_hw_board_init() ...@@ -52,6 +52,9 @@ void rt_hw_board_init()
GPIO_PortInit(GPIO, 0); GPIO_PortInit(GPIO, 0);
GPIO_PortInit(GPIO, 1); GPIO_PortInit(GPIO, 1);
DMA_Init(DMA0);
DMA_Init(DMA1);
/* NVIC Configuration */ /* NVIC Configuration */
#define NVIC_VTOR_MASK 0x3FFFFF80 #define NVIC_VTOR_MASK 0x3FFFFF80
#ifdef VECT_TAB_RAM #ifdef VECT_TAB_RAM
......
/* /*
* Copyright (c) 2006-2021, RT-Thread Development Team * Copyright (c) 2006-2023, RT-Thread Development Team
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
* *
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#include "fsl_gpio.h" #include "fsl_gpio.h"
#include "fsl_iocon.h" #include "fsl_iocon.h"
#include "pin_mux.h" #include "pin_mux.h"
#include "fsl_dma.h"
// <RDTConfigurator URL="http://www.rt-thread.com/eclipse"> // <RDTConfigurator URL="http://www.rt-thread.com/eclipse">
...@@ -48,25 +49,6 @@ extern int __HeapLimit; ...@@ -48,25 +49,6 @@ extern int __HeapLimit;
void rt_hw_board_init(void); void rt_hw_board_init(void);
#define BOARD_SDIF_BASEADDR SDIF
#define BOARD_SDIF_CLKSRC kCLOCK_SDio
#define BOARD_SDIF_CLK_FREQ CLOCK_GetFreq(kCLOCK_SDio)
#define BOARD_SDIF_CLK_ATTACH kMAIN_CLK_to_SDIO_CLK
#define BOARD_SDIF_IRQ SDIO_IRQn
#define BOARD_MMC_VCC_SUPPLY kMMC_VoltageWindows270to360
#define BOARD_SD_CARD_DETECT_PIN 17
#define BOARD_SD_CARD_DETECT_PORT 0
#define BOARD_SD_CARD_DETECT_GPIO GPIO
#define BOARD_SD_DETECT_TYPE kSDMMCHOST_DetectCardByHostCD
#define BOARD_SDIF_CD_GPIO_INIT() \
{ \
CLOCK_EnableClock(kCLOCK_Gpio2); \
GPIO_PinInit(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN, \
&(gpio_pin_config_t){kGPIO_DigitalInput, 0U}); \
}
#define BOARD_SDIF_CD_STATUS() \
GPIO_PinRead(BOARD_SD_CARD_DETECT_GPIO, BOARD_SD_CARD_DETECT_PORT, BOARD_SD_CARD_DETECT_PIN)
#endif #endif
......
...@@ -340,7 +340,7 @@ ...@@ -340,7 +340,7 @@
<MiscControls>--target=arm-arm-none-eabi</MiscControls> <MiscControls>--target=arm-arm-none-eabi</MiscControls>
<Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, DEBUG</Define> <Define>__STDC_LIMIT_MACROS, RT_USING_ARMLIBC, RT_USING_LIBC, __CLK_TCK=RT_TICK_PER_SECOND, __RTTHREAD__, DEBUG</Define>
<Undefine></Undefine> <Undefine></Undefine>
<IncludePath>..\..\..\components\libc\posix\ipc;board;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board\MCUX_Config\board;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\..\..\components\drivers\include;..\Libraries\drivers;..\..\..\components\dfs\include;..\..\..\components\libc\posix\io\poll;..\Libraries\drivers\config;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\finsh;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\..\..\components\libc\posix\io\stdio;..\..\..\components\utilities\libadt;applications;..\Libraries\CMSIS\Core\Include;..\Libraries\LPC55S6X\components\codec;.;..\..\..\components\libc\compilers\common\extension;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\..\..\components\drivers\include;..\..\..\include</IncludePath> <IncludePath>..\..\..\components\libc\posix\ipc;board;..\Libraries\LPC55S6X\middleware\sdmmc\port;..\..\..\components\drivers\include;..\..\..\components\drivers\include;board\MCUX_Config\board;..\..\..\components\libc\compilers\common\extension\fcntl\octal;..\..\..\include;..\..\..\components\drivers\include;..\Libraries\drivers;..\..\..\components\dfs\include;..\..\..\components\libc\posix\io\poll;.;..\..\..\components\dfs\filesystems\devfs;..\..\..\components\libc\compilers\common\extension;..\..\..\components\finsh;..\..\..\components\dfs\filesystems\elmfat;..\..\..\components\libc\compilers\common\include;..\..\..\libcpu\arm\common;..\..\..\libcpu\arm\cortex-m33;..\..\..\components\drivers\include;..\..\..\components\drivers\include;..\Libraries\LPC55S6X\middleware\sdmmc\inc;..\..\..\components\libc\posix\io\stdio;applications;..\Libraries\CMSIS\Core\Include;..\Libraries\LPC55S6X\components\codec;..\Libraries\drivers\config;..\..\..\components\drivers\spi;..\Libraries\LPC55S6X\LPC55S6X;..\Libraries\LPC55S6X\LPC55S6X\drivers;..\..\..\components\drivers\include;..\..\..\components\drivers\include</IncludePath>
</VariousControls> </VariousControls>
</Cads> </Cads>
<Aads> <Aads>
...@@ -381,16 +381,6 @@ ...@@ -381,16 +381,6 @@
</TargetArmAds> </TargetArmAds>
</TargetOption> </TargetOption>
<Groups> <Groups>
<Group>
<GroupName>ADT</GroupName>
<Files>
<File>
<FileName>avl.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\utilities\libadt\avl.c</FilePath>
</File>
</Files>
</Group>
<Group> <Group>
<GroupName>Applications</GroupName> <GroupName>Applications</GroupName>
<Files> <Files>
...@@ -574,6 +564,16 @@ ...@@ -574,6 +564,16 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\..\..\components\drivers\serial\serial.c</FilePath> <FilePath>..\..\..\components\drivers\serial\serial.c</FilePath>
</File> </File>
<File>
<FileName>spi_core.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_core.c</FilePath>
</File>
<File>
<FileName>spi_dev.c</FileName>
<FileType>1</FileType>
<FilePath>..\..\..\components\drivers\spi\spi_dev.c</FilePath>
</File>
</Files> </Files>
</Group> </Group>
<Group> <Group>
...@@ -629,6 +629,11 @@ ...@@ -629,6 +629,11 @@
<FileType>1</FileType> <FileType>1</FileType>
<FilePath>..\Libraries\drivers\drv_sdif.c</FilePath> <FilePath>..\Libraries\drivers\drv_sdif.c</FilePath>
</File> </File>
<File>
<FileName>drv_spi.c</FileName>
<FileType>1</FileType>
<FilePath>..\Libraries\drivers\drv_spi.c</FilePath>
</File>
<File> <File>
<FileName>drv_uart.c</FileName> <FileName>drv_uart.c</FileName>
<FileType>1</FileType> <FileType>1</FileType>
......
...@@ -113,6 +113,7 @@ ...@@ -113,6 +113,7 @@
#define RT_MMCSD_STACK_SIZE 1024 #define RT_MMCSD_STACK_SIZE 1024
#define RT_MMCSD_THREAD_PREORITY 22 #define RT_MMCSD_THREAD_PREORITY 22
#define RT_MMCSD_MAX_PARTITION 16 #define RT_MMCSD_MAX_PARTITION 16
#define RT_USING_SPI
/* Using USB */ /* Using USB */
...@@ -249,6 +250,7 @@ ...@@ -249,6 +250,7 @@
/* Other */ /* Other */
/* Signal IO */ /* Signal IO */
...@@ -267,6 +269,9 @@ ...@@ -267,6 +269,9 @@
#define BSP_USING_I2C #define BSP_USING_I2C
#define BSP_USING_I2C4 #define BSP_USING_I2C4
#define HW_I2C4_BAUDRATE_100kHZ #define HW_I2C4_BAUDRATE_100kHZ
#define BSP_USING_SPI
#define BSP_USING_SPI3
#define BSP_USING_SPI8
#define BSP_USING_SDIO #define BSP_USING_SDIO
#define BSP_USING_RTC #define BSP_USING_RTC
......
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册