- 21 10月, 2011 9 次提交
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由 Jesse Barnes 提交于
The cursor regs have moved around, add the offsets and new macros for getting at them. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
We can have more than just A and B these days. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Add two new fields to the intel_crtc struct for 3 pipe support: no_pll and use_pll_a. The no_pll field is only set on the 3rd pipe to indicate that it doesn't have a PLL of its own and so shouldn't try to write the main PLL regs. The use_pll_a field controls which PLL pipe 3 will share, A or B. The core code will try to share PLLs with whichever pipe has the same timings, rejecting the mode set if none is found. This means that pipe 3 must always be set after one of the other pipes has been configured with real PLL settings. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Add a couple of checks now that we're using the 3rd transcoder: 1) make sure the transcoder PLL enable bit is set for the transcoder in question 2) when checking actual PLL enable, use the selected PLL number rather than the transcoder number (they could be different now) Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Just a cleanup to make the mode_set function more manageable. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Well almost anyway. IVB has 3 planes, pipes, transcoders, and FDI interfaces, but only 2 pipe PLLs. So two of the pipes must use the same pipe timings (e.g. 2 DP plus one other, or two HDMI with the same mode and one other, etc.). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
Add a macro for accessing the two pipe PLLs and add a check to make sure we don't access a non-existent one in the enable/disable functions. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Reviewed-By: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
It's needed for 3 pipe support as well as just regular functionality (e.g. DisplayPort). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NAdam Jackson <ajax@redhat.com> Tested-by: NEugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Daniel Vetter 提交于
The rps disabling code wasn't properly cancelling outstanding work items. Also add a comment that explains why we're not racing with the work item that could unmask interrupts - that piece of code confused me quite a bit. v2: Ben Widawsky pointed out that the first patch would deadlock (and a few lesser problems). All corrected. Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch> Reviewed-by: NBen Widawsky <ben@bwidawsk.net> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 29 9月, 2011 3 次提交
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由 Keith Packard 提交于
The reference clock configuration must be done before any mode setting can occur as all outputs must be disabled to change anything. Initialize the clocks after turning everything off during the initialization process. Also, re-initialize the refclk at resume time. Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
I can't find any reference clocks which run at 96MHz as seems to be indicated from the comments in this code. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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由 Keith Packard 提交于
When trying to use SSC on Ibex Peak without CK505, any non-SSC outputs (like VGA or TV) get broken. So, do not use SSC on Ibex Peak unless there is a CK505 available (as specified by the VBT). On Cougar Point, all clocking is internal, so SSC can always be used, and there will never be a CK505 available. This eliminates VGA shimmer on some Ironlake machines which have a CK505 clock source. References: https://bugzilla.kernel.org/show_bug.cgi?id=21742 References: https://bugs.freedesktop.org/show_bug.cgi?id=38750Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 28 9月, 2011 2 次提交
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由 Keith Packard 提交于
The PCH refclk settings are global, so we need to look at all of the encoders, not just the current encoder when deciding how to configure it. Also, handle systems with more than one panel (any combination of PCH/non-PCH eDP and LVDS). Disable SSC clocks when no panels are connected. Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
Allow SSC to be enabled even when the BIOS disables it for testing SSC paths. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 22 9月, 2011 3 次提交
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由 Keith Packard 提交于
Make the default FBC behaviour chipset specific, allowing us to turn it on by default for Ironlake and older where it has been seen to cause trouble with screen updates. Signed-off-by: NKeith Packard <keithp@keithp.com> Tested-by: NFrancis Moreau <francis.moro@gmail.com>
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由 Wu Fengguang 提交于
Add ELD support for Intel Eaglelake, IbexPeak/Ironlake, SandyBridge/CougarPoint and IvyBridge/PantherPoint chips. ELD (EDID-Like Data) describes to the HDMI/DP audio driver the audio capabilities of the plugged monitor. It's built and passed to audio driver in 2 steps: (1) at get_modes time, parse EDID and save ELD to drm_connector.eld[] (2) at mode_set time, write drm_connector.eld[] to the Transcoder's hw ELD buffer and set the ELD_valid bit to inform HDMI/DP audio driver This patch is tested OK on G45/HDMI, IbexPeak/HDMI and IvyBridge/HDMI+DP. Test scheme: plug in the HDMI/DP monitor, and run cat /proc/asound/card0/eld* to check if the monitor name, HDMI/DP type, etc. show up correctly. Minor imperfection: the GEN5_AUD_CNTL_ST/DIP_Port_Select field always reads 0 (reserved). Without knowing the port number, I worked it around by setting the ELD_valid bit for ALL the three ports. It's tested to not be a problem, because the audio driver will find invalid ELD data and hence rightfully abort, even when it sees the ELD_valid indicator. Thanks to Zhenyu and Pierre-Louis for a lot of valuable help and testing. CC: Zhao Yakui <yakui.zhao@intel.com> CC: Wang Zhenyu <zhenyu.z.wang@intel.com> CC: Jeremy Bush <contractfrombelow@gmail.com> CC: Christopher White <c.white@pulseforce.com> CC: Pierre-Louis Bossart <pierre-louis.bossart@intel.com> CC: Paul Menzel <paulepanter@users.sourceforge.net> Signed-off-by: NWu Fengguang <fengguang.wu@intel.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
We want to enable dithering on any pipe where the frame buffer has more color resolution than the output device. The previous code was incorrectly clamping the frame buffer bpc to the display bpc, effectively disabling dithering all of the time as the computed frame buffer bpc would never be larger than the display bpc. Signed-off-by: NKeith Packard <keithp@keithp.com> Reported-by: NOliver Hartkopp <socketcan@hartkopp.net> Tested-by: NOliver Hartkopp <socketcan@hartkopp.net>
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- 20 9月, 2011 2 次提交
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由 Keith Packard 提交于
We want to enable dithering on any pipe where the frame buffer has more color resolution than the output device. The previous code was incorrectly clamping the frame buffer bpc to the display bpc, effectively disabling dithering all of the time as the computed frame buffer bpc would never be larger than the display bpc. Signed-off-by: NKeith Packard <keithp@keithp.com> Reported-by: NOliver Hartkopp <socketcan@hartkopp.net> Tested-by: NOliver Hartkopp <socketcan@hartkopp.net>
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由 Akshay Joshi 提交于
Various issues involved with the space character were generating warnings in the checkpatch.pl file. This patch removes most of those warnings. Signed-off-by: NAkshay Joshi <me@akshayjoshi.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 26 8月, 2011 1 次提交
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由 Thomas Jarosch 提交于
Otherwise it just contains random memory. Issue detected by cppcheck. Signed-off-by: NThomas Jarosch <thomas.jarosch@intra2net.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 23 8月, 2011 1 次提交
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由 Kamal Mostafa 提交于
The commit "Not all systems expose a firmware or platform mechanism for changing the backlight intensity on i915, so add native driver support" adds calls to intel_panel_setup_backlight() from intel_{lvds,dp}_init so do not call it again from intel_setup_outputs(). BugLink: http://bugs.launchpad.net/bugs/831542Signed-off-by: NKamal Mostafa <kamal@canonical.com> ACKed-by: NMatthew Garrett <mjg@redhat.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 10 8月, 2011 1 次提交
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由 Jesse Barnes 提交于
We ought to be calling this from our DPMS routines as well as global state may change and we need to enable/disable clocks. So split out the code in preparation for further changes. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 09 8月, 2011 2 次提交
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由 Keith Packard 提交于
Just an extra parameter which isn't actually needed. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Keith Packard 提交于
CPT pipe select is different from previous generations (using two bits instead of one). All of the paths from intel_disable_pch_ports were not making this distinction. Mode setting with pipe A turned off would then also force all outputs on pipe B to get turned off as the disable code would mistakenly decide that all of these outputs were on pipe A and turn them off. This is an extension of the CPT DP disable fix (why didn't I fix this then?) Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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- 02 8月, 2011 1 次提交
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由 Jesse Barnes 提交于
The EDID parser will zero out the bpc value, and the driver needs to handle that case. In our picker, we'll just ignore 0 values as far as bpp picking goes. Fixes https://bugs.freedesktop.org/show_bug.cgi?id=39323. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 30 7月, 2011 3 次提交
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由 Jesse Barnes 提交于
These bits moved around on SNB and above. v2: again with the git send-email fail v3: add macros for getting per-pipe override & enable bits v4: enable phase sync pointer on SNB and IVB configs as well Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Michel Alexandre Salim 提交于
Using the new quirk added to support disabling SSC on Lenovo U160 (#36656, commit 435793df), also register the Vaio as a special case and disable SSC for it. This patch fixes #34437 on fdo bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=34437Signed-off-by: NMichel Alexandre Salim <salimma@fedoraproject.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
If a mode set fails we may get a message from drm_crtc_helper if we're lucky, but it won't tell us anything about *why* we failed to set a mode. So add a few DRM_ERRORs for the cases that shouldn't happen so we can debug things more easily. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 29 7月, 2011 6 次提交
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由 Jesse Barnes 提交于
CB tuning is needed to handle potential process variations that might cause clock jitter for certain PLL settings. However, we were setting it incorrectly since we were using the wrong M value as a check (M1 when we needed to use the whole M value). Fix it up, making my HDMI attached display a little prettier (used to have occasional dots crawl across the display). Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
Writes to the plane control register are buffered in the chip until a write to the DSPADDR (pre-965) or DSPSURF (post-965) register occurs. This patch adds flushes in: intel_enable_plane gen6_init_clock_gating ivybridge_init_clock_gating Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
After writing to the plane control reg we need to write to the surface reg to trigger the double buffered register latch. On previous chipsets, writing to DSPADDR was enough, but on ILK+ DSPSURF is the reg that triggers the double buffer latch. v2: write DSPADDR too to cover pre-965 chipsets v3: use flush_display_plane instead, that's what it's for v4: send the right patch Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Tested-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Jesse Barnes 提交于
On CougarPoint and PantherPoint PCH chips, the timing generator may fail to start after DP training completes. This is due to a bug in the FDI autotraining detect logic (which will stall the timing generator and re-enable it once training completes), so disable it to avoid silent DP mode setting failures. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Keith Packard 提交于
This corrects the DPMS mode tracking so that the DPMS code will actually turn the CRTC off the next time the screen saves. Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org>
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由 Keith Packard 提交于
Display port pipe selection on CPT is not done with a bit in the output register, rather it is controlled by a couple of bits in the separate transcoder register which indicate which display port output is connected to the transcoder. This patch replaces the simplistic macro DP_PIPE_ENABLED with the rather more complicated function dp_pipe_enabled which checks the output register to see if that is enabled, and then goes on to either check the output register pipe selection bit (on non-CPT) or the transcoder DP selection bits (on CPT). Before this patch, any time the mode of pipe A was changed, any display port outputs on pipe B would get disabled as intel_disable_pch_ports would ensure that the mode setting operation could occur on pipe A without interference from other outputs connected to that pch port Signed-off-by: NKeith Packard <keithp@keithp.com> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Reviewed-by: NAdam Jackson <ajax@redhat.com>
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- 23 7月, 2011 1 次提交
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由 Jesse Barnes 提交于
Per the specs and to address https://bugs.freedesktop.org/show_bug.cgi?id=36888. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Cc: stable@kernel.org Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 22 7月, 2011 1 次提交
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由 Jesse Barnes 提交于
If a mode set fails we may get a message from drm_crtc_helper if we're lucky, but it won't tell us anything about *why* we failed to set a mode. So add a few DRM_ERRORs for the cases that shouldn't happen so we can debug things more easily. Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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- 14 7月, 2011 1 次提交
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由 Keith Packard 提交于
We've tried several times to make this machine 'just work', but every patch that does causes many other machines to fail. This adds a quirk which special cases this hardware and forces ssc to be disabled. There's no way to override this from the command line; that would be a significantly more invasive change. This patch fixes #36656 on fdo bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=36656Signed-off-by: NKeith Packard <keithp@keithp.com> References: https://bugs.freedesktop.org/show_bug.cgi?id=36656Reviewed-by: NChris Wilson <chris@chris-wilson.co.uk>
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- 09 7月, 2011 3 次提交
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由 Chris Wilson 提交于
Upon review, all path share the same dependencies for updating the registers and so we can benefit from sharing the code and checking early. This removes the unsightly intel_wait_for_vblank() from the lowlevel functions and upon further analysis the only path that will require a wait is if we are performing an instantaneous transition between two valid FBC configurations. The page-flip path itself will have disabled FBC registers and will have waited for at least one vblank before finishing the flip and attempting to re-enable FBC. This wait can be accomplished simply by delaying the enable until after we are sure that a vblank will have passed, which we are already doing to make sure that the display is settled before enabling FBC. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NKeith Packard <keithp@keithp.com> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Chris Wilson 提交于
In order to accommodate the requirements of re-enabling FBC after page-flipping, but to avoid doing so and incurring the cost of a wait for vblank in the middle of a page-flip sequence, we defer the actual enablement by 50ms. If any request to disable FBC arrive within that interval, the enablement is cancelled and we are saved from blocking on the wait. Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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由 Chris Wilson 提交于
Page-flipping updates the scanout address, nukes the FBC compressed image and so forces an FBC update so that the displayed image remains consistent. However, page-flipping does not update the FBC registers themselves, which remain pointing to both the old address and the old CPU fence. Future updates to the new front-buffer (scanout) are then undetected! This first approach to demonstrate the issue and highlight the fix, simply disables FBC upon page-flip (a recompression will be forced on every flip so FBC becomes immaterial) and then re-enables FBC in the page-flip finish work function, so that the FBC registers are now pointing to the new framebuffer and front-buffer rendering works once more. Ideally, we want to only re-enable FBC after page-flipping is complete, as otherwise we are just wasting cycles and power (with needless recompression) whilst the page-flipping application is still running. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33487Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk> Reviewed-by: NJesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: NKeith Packard <keithp@keithp.com>
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