Merge tag 'omap-for-v3.16/pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Merge "ARM: omap pm changes for v3.16 merge window, resend" from Tony Lindgren:

PM related fixes for omap3 that were discovered during omap3
conversion to device tree. This series sets up the PMIC signaling
in a way where we can test for PM regressions easily by
looking at state of the the sys_clkreq and sys_off_mode pins.

Note that this series alone does not make omap3 PM to cut
off core voltage during off-idle, changes to twl4030-power.c
configurations are still needed. Those will be posted
separately.

* tag 'omap-for-v3.16/pm-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: OMAP2+: Enable CPUidle in omap2plus_defconfig
  ARM: dts: Enable N900 keyboard sleep leds by default
  ARM: OMAP2+: Fix voltage scaling init for device tree
  ARM: dts: Configure omap3 twl4030 I2C4 pins by default
  ARM: OMAP3: Fix voltage control for deeper idle states
  ARM: OMAP3: Disable broken omap3_set_off_timings function
  ARM: OMAP3: Fix idle mode signaling for sys_clkreq and sys_off_mode
  ARM: dts: Fix omap serial wake-up when booted with device tree
  mfd: twl-core: Fix idle mode signaling for omaps when booted with device tree
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'omap-for-v3.16/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/soc

Pull "ARM: omap soc changes for v3.16 merge window" from Tony Lindgren:

SoC related changes for omaps.

* tag 'omap-for-v3.16/soc-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: DRA752: add detection of SoC information
  ARM: OMAP2+: Remove suspend_set_ops from common pm late init
  ARM: OMAP2+: hwmod: OMAP5 DSS hwmod data
  ARM: omap4: hwmod_data: Clean up audio related structures (remove/merge them)
Signed-off-by: NOlof Johansson <olof@lixom.net>

The sunxi reset controller code is only used with sun6i (a31).
After the platform has been split up into per-soc options, it's
now possible to build it without the reset controller code, so
the base platform init must not call into the reset driver
if that is turned off at compile time.
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

People have appended new entries instead of inserting them at
the right location, so sort them.
Signed-off-by: NOlof Johansson <olof@lixom.net>

With the newly introduced CPU_METHOD_OF_DECLARE is not necessary anymore
to reference the relevant smp_ops in the board file, but instead it can
simply be set by the enable-method property of the cpu nodes.
Signed-off-by: NHeiko Stuebner <heiko@sntech.de>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge "mach-bcm 3.16 soc updates" From Matt Porter:

* only show ARCH_BCM in multi v6/v7 configs
* enable ARM erratum 775420
* bcm_defconfig updates for pwm

* tag 'for-3.16/bcm-soc' of git://github.com/broadcom/mach-bcm:
  ARM: bcm_defconfig: Enable PWM and Backlight
  ARM: mach-bcm: add ARM_ERRATA_775420
  ARM: bcm: Restrict ARCH_BCM selection to ARCH_MULTI_V6_V7
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Conflicts:
	arch/arm/mach-bcm/Kconfig

Merge "Allwinner Core additions for 3.16, take 2" from Maxime Ripard:

  - Convert the A31 SMP operations to the CPU_METHOD_OF_DECLARE mechanism
  - Remove the reset code from the machine definition, that removes pretty much
    all the code left in mach-sunxi

* tag 'sunxi-core-for-3.16-2' of https://github.com/mripard/linux:
  ARM: sunxi: Remove init_machine callback
  ARM: sunxi: Remove reset code from the platform
  ARM: sun6i: Retire the smp field in A31 machine
  Documentation: dt: bindings: Document Allwinner A31 enable method
  ARM: sun6i: Use CPU_METHOD_OF_DECLARE
  Documentation: dt: bindings: Document ARM PSCI enable method
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Merge tag 'qcom-soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into next/soc

Merge "Qualcomm ARM Based SoC Updates for v3.16" from Kumar Gala:

* Enabling building pinctrl and AMBA bus support
* Clean up debug UART selection

* tag 'qcom-soc-for-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom:
  ARM: qcom: Select PINCTRL by default for ARCH_QCOM
  ARM: debug: qcom: make UART address selection configuration option
  ARM: qcom: Enable ARM_AMBA option for Qualcomm SOCs.

Conflicts:
	arch/arm/Kconfig.debug
	arch/arm/mach-qcom/Kconfig
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Merge "mvebu SoC changes for v3.16 (incremental #2)" from Jason Cooper <jason@lakedaemon.net>:

 - mvebu
    - fix coherency on big-endian in -next
    - hardware IO coherency
    - L2/PCIe deadlock workaround
    - small coherency cleanups

* tag 'mvebu-soc-3.16-2' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: returns ll_get_cpuid() to ll_get_coherency_cpumask()
  ARM: mvebu: improve comments in coherency_ll.S
  ARM: mvebu: fix indentation of assembly instructions in coherency_ll.S
  ARM: mvebu: fix big endian booting after coherency code rework
  ARM: mvebu: coherency: fix registration of PCI bus notifier when !PCI
  ARM: mvebu: implement L2/PCIe deadlock workaround
  ARM: mvebu: use hardware I/O coherency also for PCI devices
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Patches from Anders Berg applied individually:

Here is version 4 of platform support for AXM5516 SoC.

The clk driver is now applied to clk-next. The rest should be ready for
arm-soc. Haven't got any response from the power/reset maintainers... I hope
this driver can be taken via arm-soc as well.

The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.

This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.

* axxia/soc:
  ARM: dts: axxia: Add reset controller
  power: reset: Add Axxia system reset driver
  ARM: axxia: Adding defconfig for AXM55xx
  ARM: dts: Device tree for AXM55xx.
  ARM: Add platform support for LSI AXM55xx SoC
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add the reset controller to the AXM5xx device tree.
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add Axxia (AXM55xx) SoC system reset driver. This driver handles only system
reboot (and not power-off).
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Cc: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add a defconfig file for the LSI Axxia family of devices (CONFIG_ARCH_AXXIA).
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Add device tree for the Amarillo validation board with an AXM5516 SoC.
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The AXM55xx family consists of devices that may contain up to 16 ARM Cortex-A15
cores (in a 4x4 cluster configuration). The cores within each cluster share an
L2 cache, and the clusters are connected to each other via a CCN-504 cache
coherent interconnect.

This machine requires CONFIG_ARM_LPAE enabled as all peripherals are located
above 4GB in the memory map.
Signed-off-by: NAnders Berg <anders.berg@lsi.com>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

The init_machine hook is now at its default value. We can remove it.

Even though the sun4i and sun7i machines are nothing more than generic machines
now, leave them in so that we won't have to add them back if needed, and so
that the machine is still displayed in /proc/cpuinfo.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Now that reset is handled either by the watchdog driver for the sun4i, sun5i
and sun7i, and by a driver of its own for sun6i, we can remove it from the
platform code.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: NArnd Bergmann <arnd@arndb.de>

Add missing PINCTRL selection.  This enables selection of pinctrollers for
Qualcomm processors.
Signed-off-by: NAndy Gross <agross@codeaurora.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

Separate Qualcomm low-level debugging UART to two options.

DEBUG_MSM_UART is used in earlier non-multi platform arches,
like MSM7X00A, QSD8X50 and MSM7X30.

DEBUG_QCOM_UARTDM is used in multi-plafrom arches and have
embedded data mover.

Make DEBUG_UART_PHYS and DEBUG_UART_BASE user adjustable by
Kconfig menu.
Signed-off-by: NIvan T. Ivanov <iivanov@mm-sol.com>
Reviewed-by: NStephen Boyd <sboyd@codeaurora.org>
Tested-by: NStephen Boyd <sboyd@codeaurora.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

As some of the IPs on Qualcomm SOCs are based on ARM PrimeCell IPs.
For example SDCC controller is PrimeCell MCI pl180. Adding this option will
give flexibility to reuse the existing drivers as it is without major
modifications.
Signed-off-by: NSrinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: NKumar Gala <galak@codeaurora.org>

In the refactoring of the coherency fabric assembly code, a function
called ll_get_cpuid() was created to factorize common logic between
functions adding CPU to the SMP coherency group, enabling and
disabling the coherency.

However, the name of the function is highly misleading: ll_get_cpuid()
makes one think tat it returns the ID of the CPU, i.e 0 for CPU0, 1
for CPU1, etc. In fact, this is not at all what this function returns:
it returns a CPU mask for the current CPU, usable for the coherency
fabric configuration and control registers.

Therefore this commit renames this function to
ll_get_coherency_cpumask(), and adds additional comments on top of the
function to explain in more details what it does, and also how the
endianess issue is handled.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-5-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This commit makes no functional change, it only improves a bit the
various code comments in mach-mvebu/coherency_ll.S, by fixing a few
typos and adding a few more details.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-4-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

This commit does not make any functional change, it only fixes the
indentation of a few assembly instructions in
arch/arm/mach-mvebu/coherency_ll.S.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-3-git-send-email-thomas.petazzoni@free-electrons.comAcked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

As part of the introduction of the cpuidle support for Armada XP, the
coherency code was significantly reworked, especially in the
coherency_ll.S file. However, when the ll_get_cpuid function was
created, the big-endian specific code that switches the endianess of
the register was not updated properly.

This patch fixes this code, and therefore makes big endian systems
bootable again.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400762882-10116-2-git-send-email-thomas.petazzoni@free-electrons.com
Fixes: 2e8a5942 ("ARM: mvebu: Split low level functions to manipulate HW coherency")
Reported-by: NKevin Hilman <khilman@linaro.org>
Cc: Kevin Hilman <khilman@linaro.org>
Acked-by: NGregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: NJason Cooper <jason@lakedaemon.net>

Commit b0063aad ("ARM: mvebu: use hardware I/O coherency also for
PCI devices") added a reference to the pci_bus_type variable, but this
variable is only available when CONFIG_PCI is enabled. Therefore,
there is now a build failure in !CONFIG_PCI situations.

This commit fixes that by enclosing the entire initcall into a
IS_ENABLED(CONFIG_PCI) condition.
Reported-by: NArnd Bergmann <arnd@arndb.de>
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400598783-706-1-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

The Marvell Armada 375 and Armada 38x SOCs, which use the Cortex-A9
CPU core, the PL310 cache and the Marvell PCIe hardware block are
affected a L2/PCIe deadlock caused by a system erratum when hardware
I/O coherency is used.

This deadlock can be avoided by mapping the PCIe memory areas as
strongly-ordered (note: MT_UNCACHED is strongly-ordered), and by
removing the outer cache sync done in software. This is implemented in
this patch by:

 * Registering a custom arch_ioremap_caller function that allows to
   make sure PCI memory regions are mapped MT_UNCACHED.

 * Adding at runtime the 'arm,io-coherent' property to the PL310 cache
   controller. This cannot be done permanently in the DT, because the
   hardware I/O coherency can only be enabled when CONFIG_SMP is
   enabled, in the current kernel situation.
Signed-off-by: NThomas Petazzoni <thomas.petazzoni@free-electrons.com>
Link: https://lkml.kernel.org/r/1400165974-9059-4-git-send-email-thomas.petazzoni@free-electrons.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>

Merge tag 'tegra-for-3.16-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc

Merge "ARM: tegra: core code changes for 3.16" from Stephen Warren:

This branch contains just a single patch this time around. Thierry
enhanced Tegra's restart code to allow programming PMC scratch registers
to request specific behaviour after reboot. One of the most useful
options for mainline software is the ability to reboot directly into USB
recovery mode, which e.g. allows the bootloader to be reflashed.

* tag 'tegra-for-3.16-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
  ARM: tegra: Support reboot modes
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/soc

Merge "ARM: imx: soc changes for 3.16" from Shawn Guo:

i.MX SoC changes for 3.16:
 - A few cleanups on mx21ads board file, which should make the later
   conversion to DT a little bit easier.
 - Add some missing clocks and drop unused clk lookups for i.MX1 and
   i.MX27 clock drivers
 - Add initial i.MX SoloX (imx6sx) SoC support
 - Remove mx51_babbage and mach-cpuimx51sd board files, as the
   equivalent DT support is ready for the boards
 - Clean up device tree timer initialization a little bit
 - Add missing i2c4 clock for i.MX6 DualLite/Solo
 - Add missing CKO clock i.MX25
 - Add shared gate clock support for i.MX specific clk_gate2
 - Add low-level debug support for SoC VF610
 - Some random code cleanups and defconfig updates

* tag 'imx-soc-3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux: (33 commits)
  ARM: mx25: Add CLKO support
  ARM: i.MX1 clk: Remove clk_register_clkdev() for unused clocks
  ARM: i.MX1 clk: Add missing clocks
  ARM: imx: add basic imx6sx SoC support
  ARM: imx: add clock driver for imx6sx
  ARM: imx: add low-level debug support for imx6sx
  ARM: mx51: Remove mach-cpuimx51sd board file
  ARM: i.MX: Setup IRQ handler from IRQ driver
  ARM: i.MX27 pca100: remove deprecated IRQF_DISABLED
  ARM: imx/mxs defconfigs: add MTD_SPI_NOR (new dependency for M25P80)
  ARM: i.MX: Fix eMMa PrP resource size
  ARM: imx_v4_v5_defconfig: drop CONFIG_COMMON_CLK_DEBUG option
  ARM: i.MX27 clk: Remove clk_register_clkdev() for unused clocks
  ARM: i.MX27 clk: Add missing clocks for MSHC and RTIC
  ARM: imx6q: add the missing esai_ahb clock
  ARM: imx: add shared gate clock support
  ARM: imx: lock is always valid for clk_gate2
  ARM: imx: define struct clk_gate2 on our own
  ARM: i.MX: Remove #ifdef CONFIG_OF
  ARM: imx_v6_v7_defconfig: enable option CONFIG_LOCALVERSION_AUTO
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge "Allwinner SoCs core additions for 3.16" from Maxime Ripard:

Refactor the Kconfig options to have one Kconfig option per machine.

* tag 'sunxi-core-for-3.16' of https://github.com/mripard/linux:
  ARM: sunxi: select MFD_SUN6I_PRCM when sun6i arch support is enabled
  ARM: sunxi: Split the various SoCs support in Kconfig
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge "ARM: STi: SoC changes for v3.16" from Maxime Coquelin:

SoC changes for STi platforms
 - Add support for STiH407

* tag 'sti-soc-for-v3.16' of git://git.stlinux.com/devel/kernel/linux-sti:
  ARM: STi: Add STiH407 SoC support
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'renesas-soc-cleanup-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Renesas ARM Based SoC soc-cleanup Updates for v3.16" from Simon Horman:

r8a7791 (R-Car H2) SoC and its Koelsch board and,
r8a7740 (R-Mobile A1) SoC and its Armadillo800eva board
* Set CPU clock frequency from OF nodes

* tag 'renesas-soc-cleanup-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: Set clock frequency in HZ from OF nodes
  ARM: shmobile: Use shmobile_init_late() on r8a7740
  ARM: shmobile: Remove unused r8a7791_init_early()
  ARM: shmobile: Use r8a7791 DT CPU Frequency for Koelsch
  ARM: shmobile: Use r8a7791 DT CPU Frequency in common case
  ARM: shmobile: Remove unused r8a7740_init_delay()
  ARM: shmobile: Use r8a7740 DT CPU Frequency for Armadillo DT Ref
  ARM: shmobile: Use r8a7740 DT CPU Frequency in common case
  ARM: shmobile: Add r8a7740 Maximum CPU Frequency to DTS
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge tag 'renesas-clock2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc

Merge "Second Round of Renesas ARM Based SoC Clock Updates for v3.16" from
Simon Horman:

r8a7791 (R-Car M2) SoC
* Correct SYS-DMAC clock defines

r8a7740 (R-Mobile A1) SoC
* Correct name of DT Ethernet clock

* tag 'renesas-clock2-for-v3.16' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  ARM: shmobile: r8a7791: Correct SYS-DMAC clock defines
  ARM: shmobile: r8a7740: Correct name of DT Ethernet clock
Signed-off-by: NOlof Johansson <olof@lixom.net>

Bring in the cleanup branch due to conflicts in new additions. Should really
have been the base before the other branch, but this way works too.

* cleanup/kconfig:
  ARM: qcom: clean-up unneeded kconfig selects
  ARM: bcm: clean-up unneeded kconfig selects
  ARM: mvebu: clean-up unneeded kconfig selects
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge "ARM: mvebu: SoC changes for v3.16" from Jason Cooper:

mvebu SoC changes for v3.16

 - Armada 375/38x coherency support
 - Armada 375/38x SMP support
 - mvebu PMSU and CPU reset support
 - Armada 370/XP cpuidle support
 - kirkwood remove platform init of audio device
 - small fixes and cleanup for new SoC (375/38x)

Note:
 - due to complex deps, cpuidle changes Acked by appropriate maintainer for
   going though arm-soc tree.

* tag 'mvebu-soc-3.16' of git://git.infradead.org/linux-mvebu: (46 commits)
  ARM: mvebu: Fix pmsu compilation when ARMv6 is selected
  ARM: mvebu: conditionalize Armada 375 coherency workaround
  ARM: mvebu: conditionalize Armada 375 SMP workaround
  ARM: mvebu: add Armada 375 A0 revision definition
  ARM: mvebu: initialize mvebu-soc-id earlier
  ARM: mvebu: fix thermal quirk SoC revision check
  ARM: Kirkwood: t5325: Remove platform device to instantiate audio
  ARM: Kirkwood: Remove platform driver for codec
  ARM: mvebu: Add thermal quirk for the Armada 375 DB board
  ARM: mvebu: Select HAVE_ARM_TWD only if SMP is enabled
  ARM: mvebu: fix the name of the parameter used in mvebu_get_soc_id
  ARM: mvebu: remove unnecessary ifdef around l2x0_of_init
  ARM: mvebu: register the cpuidle driver for the Armada XP SoCs
  cpuidle: mvebu: Add initial CPU idle support for Armada 370/XP SoC
  ARM: mvebu: Register notifier callback for the cpuidle transition
  ARM: mvebu: refine which files are build in mach-mvebu
  ARM: mvebu: Add the PMSU related part of the cpu idle functions
  ARM: mvebu: Allow to power down L2 cache controller in idle mode
  ARM: mvebu: Low level function to disable HW coherency support
  ARM: mvebu: Split low level functions to manipulate HW coherency
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

Merge "ARM: mvebu: SoC orion5x DT conversion for v3.16" from Jason Cooper:

mvebu SoC orion5x DT conversion for v3.16

 - orion5x
    - convert to DT

* tag 'mvebu-soc-orion5x-3.16' of git://git.infradead.org/linux-mvebu: (29 commits)
  ARM: orion: remove no longer needed gpio DT code
  ARM: orion: remove no longer needed DT IRQ code
  ARM: orion5x: convert Maxtor Shared Storage II to the Device Tree
  ARM: orion5x: convert d2net to Device Tree
  ARM: orion5x: convert RD-88F5182 to Device Tree
  ARM: orion5x: remove unneeded code for edmini_v2
  ARM: orion5x: keep TODO list in edmini_v2 DT
  ARM: orion5x: use DT to describe NOR on edmini_v2
  ARM: orion5x: use DT to describe EHCI on edmini_v2
  ARM: orion5x: use DT to describe I2C devices on edmini_v2
  ARM: orion5x: convert edmini_v2 to DT pinctrl
  ARM: orion5x: add standard pinctrl configs for sata0 and sata1
  ARM: orion5x: add Device Bus description at SoC level
  ARM: orion5x: update I2C description at SoC level
  ARM: orion5x: enable pinctrl driver at SoC level
  ARM: orion5x: switch to DT interrupts and timer
  ARM: orion: switch to a per-platform handle_irq() function
  ARM: orion5x: convert to use 'clocks' property for UART controllers
  ARM: orion5x: switch to use the clock driver for DT platforms
  ARM: orion5x: add interrupt for Ethernet in Device Tree
  ...
Signed-off-by: NOlof Johansson <olof@lixom.net>

Currently the files in /sys/devices/soc0/ show no information about
DRA7. Few userspace programs do depend on this information to make SoC
specific support. So update logic to detect the relevant information and
provide to userspace.
Signed-off-by: NNishanth Menon <nm@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

In omap2_common_pm_late_init suspend_set_ops was called to set common
suspend handling functions for all omap platforms. This created two
problems. First, these suspend ops were being set for all platforms,
regardless of whether or not suspend support has been integrated so in
the case of AM33XX, suspend to mem was presented as available but
failed every time. Second, some platforms will need to define a
completely separate set of suspend ops, such as AM33XX, due to
differences from previous omap platforms so there is no need to
always set the common omap ops.

This patch moves the suspend_set_ops call from omap2_common_pm_late_init
into a separate function that then gets called in the omap*_pm_init
functions for each platform.
Signed-off-by: NDave Gerlach <d-gerlach@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Now that we can rely on the enable-method, remove the smp field declaration
from A31 machine.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>

Document the necently introduced A31 enable-method as a valid option.
Signed-off-by: NMaxime Ripard <maxime.ripard@free-electrons.com>