clock2420_data.c 58.0 KB
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/*
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 * OMAP2420 clock data
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 *
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 * Copyright (C) 2005-2009 Texas Instruments, Inc.
 * Copyright (C) 2004-2011 Nokia Corporation
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 *
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 * Contacts:
 * Richard Woodruff <r-woodruff2@ti.com>
 * Paul Walmsley
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 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License version 2 as
 * published by the Free Software Foundation.
 */

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#include <linux/kernel.h>
#include <linux/clk.h>
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#include <linux/list.h>
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#include <plat/clkdev_omap.h>
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#include "clock.h"
#include "clock2xxx.h"
#include "opp2xxx.h"
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#include "cm2xxx_3xxx.h"
#include "prm2xxx_3xxx.h"
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#include "prm-regbits-24xx.h"
#include "cm-regbits-24xx.h"
#include "sdrc.h"
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#include "control.h"
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#define OMAP_CM_REGADDR                 OMAP2420_CM_REGADDR

/*
 * 2420 clock tree.
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 *
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 * NOTE:In many cases here we are assigning a 'default' parent. In
 *	many cases the parent is selectable. The set parent calls will
 *	also switch sources.
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 *
 *	Several sources are given initial rates which may be wrong, this will
 *	be fixed up in the init func.
 *
 *	Things are broadly separated below by clock domains. It is
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 *	noteworthy that most peripherals have dependencies on multiple clock
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 *	domains. Many get their interface clocks from the L4 domain, but get
 *	functional clocks from fixed sources or other core domain derived
 *	clocks.
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 */
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/* Base external input clocks */
static struct clk func_32k_ck = {
	.name		= "func_32k_ck",
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	.ops		= &clkops_null,
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	.rate		= 32768,
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	.clkdm_name	= "wkup_clkdm",
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};
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static struct clk secure_32k_ck = {
	.name		= "secure_32k_ck",
	.ops		= &clkops_null,
	.rate		= 32768,
	.clkdm_name	= "wkup_clkdm",
};

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/* Typical 12/13MHz in standalone mode, will be 26Mhz in chassis mode */
static struct clk osc_ck = {		/* (*12, *13, 19.2, *26, 38.4)MHz */
	.name		= "osc_ck",
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	.ops		= &clkops_oscck,
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &omap2_osc_clk_recalc,
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};

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/* Without modem likely 12MHz, with modem likely 13MHz */
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static struct clk sys_ck = {		/* (*12, *13, 19.2, 26, 38.4)MHz */
	.name		= "sys_ck",		/* ~ ref_clk also */
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	.ops		= &clkops_null,
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	.parent		= &osc_ck,
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &omap2xxx_sys_clk_recalc,
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};
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static struct clk alt_ck = {		/* Typical 54M or 48M, may not exist */
	.name		= "alt_ck",
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	.ops		= &clkops_null,
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	.rate		= 54000000,
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	.clkdm_name	= "wkup_clkdm",
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};
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/* Optional external clock input for McBSP CLKS */
static struct clk mcbsp_clks = {
	.name		= "mcbsp_clks",
	.ops		= &clkops_null,
};

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/*
 * Analog domain root source clocks
 */

/* dpll_ck, is broken out in to special cases through clksel */
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/* REVISIT: Rate changes on dpll_ck trigger a full set change.	...
 * deal with this
 */

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static struct dpll_data dpll_dd = {
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	.mult_div1_reg		= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
	.mult_mask		= OMAP24XX_DPLL_MULT_MASK,
	.div1_mask		= OMAP24XX_DPLL_DIV_MASK,
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	.clk_bypass		= &sys_ck,
	.clk_ref		= &sys_ck,
	.control_reg		= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
	.enable_mask		= OMAP24XX_EN_DPLL_MASK,
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	.max_multiplier		= 1023,
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	.min_divider		= 1,
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	.max_divider		= 16,
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};

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/*
 * XXX Cannot add round_rate here yet, as this is still a composite clock,
 * not just a DPLL
 */
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static struct clk dpll_ck = {
	.name		= "dpll_ck",
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	.ops		= &clkops_omap2xxx_dpll_ops,
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	.parent		= &sys_ck,		/* Can be func_32k also */
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	.dpll_data	= &dpll_dd,
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &omap2_dpllcore_recalc,
	.set_rate	= &omap2_reprogram_dpllcore,
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};

static struct clk apll96_ck = {
	.name		= "apll96_ck",
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	.ops		= &clkops_apll96,
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	.parent		= &sys_ck,
	.rate		= 96000000,
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	.flags		= ENABLE_ON_INIT,
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	.clkdm_name	= "wkup_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
	.enable_bit	= OMAP24XX_EN_96M_PLL_SHIFT,
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};

static struct clk apll54_ck = {
	.name		= "apll54_ck",
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	.ops		= &clkops_apll54,
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	.parent		= &sys_ck,
	.rate		= 54000000,
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	.flags		= ENABLE_ON_INIT,
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	.clkdm_name	= "wkup_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKEN),
	.enable_bit	= OMAP24XX_EN_54M_PLL_SHIFT,
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};

/*
 * PRCM digital base sources
 */
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/* func_54m_ck */

static const struct clksel_rate func_54m_apll54_rates[] = {
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	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
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	{ .div = 0 },
};

static const struct clksel_rate func_54m_alt_rates[] = {
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	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 0 },
};

static const struct clksel func_54m_clksel[] = {
	{ .parent = &apll54_ck, .rates = func_54m_apll54_rates, },
	{ .parent = &alt_ck,	.rates = func_54m_alt_rates, },
	{ .parent = NULL },
};

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static struct clk func_54m_ck = {
	.name		= "func_54m_ck",
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	.ops		= &clkops_null,
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	.parent		= &apll54_ck,	/* can also be alt_clk */
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	.clkdm_name	= "wkup_clkdm",
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	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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	.clksel_mask	= OMAP24XX_54M_SOURCE_MASK,
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	.clksel		= func_54m_clksel,
	.recalc		= &omap2_clksel_recalc,
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};
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static struct clk core_ck = {
	.name		= "core_ck",
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	.ops		= &clkops_null,
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	.parent		= &dpll_ck,		/* can also be 32k */
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &followparent_recalc,
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};
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static struct clk func_96m_ck = {
	.name		= "func_96m_ck",
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	.ops		= &clkops_null,
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	.parent		= &apll96_ck,
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &followparent_recalc,
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};

/* func_48m_ck */

static const struct clksel_rate func_48m_apll96_rates[] = {
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	{ .div = 2, .val = 0, .flags = RATE_IN_24XX },
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	{ .div = 0 },
};

static const struct clksel_rate func_48m_alt_rates[] = {
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	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 0 },
};

static const struct clksel func_48m_clksel[] = {
	{ .parent = &apll96_ck,	.rates = func_48m_apll96_rates },
	{ .parent = &alt_ck, .rates = func_48m_alt_rates },
	{ .parent = NULL }
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};

static struct clk func_48m_ck = {
	.name		= "func_48m_ck",
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	.ops		= &clkops_null,
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	.parent		= &apll96_ck,	 /* 96M or Alt */
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	.clkdm_name	= "wkup_clkdm",
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	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(PLL_MOD, CM_CLKSEL1),
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	.clksel_mask	= OMAP24XX_48M_SOURCE_MASK,
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	.clksel		= func_48m_clksel,
	.recalc		= &omap2_clksel_recalc,
	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
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};

static struct clk func_12m_ck = {
	.name		= "func_12m_ck",
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	.ops		= &clkops_null,
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	.parent		= &func_48m_ck,
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	.fixed_div	= 4,
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	.clkdm_name	= "wkup_clkdm",
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	.recalc		= &omap_fixed_divisor_recalc,
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};

/* Secure timer, only available in secure mode */
static struct clk wdt1_osc_ck = {
	.name		= "ck_wdt1_osc",
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	.ops		= &clkops_null, /* RMK: missing? */
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	.parent		= &osc_ck,
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	.recalc		= &followparent_recalc,
};

/*
 * The common_clkout* clksel_rate structs are common to
 * sys_clkout, sys_clkout_src, sys_clkout2, and sys_clkout2_src.
 * sys_clkout2_* are 2420-only, so the
 * clksel_rate flags fields are inaccurate for those clocks. This is
 * harmless since access to those clocks are gated by the struct clk
 * flags fields, which mark them as 2420-only.
 */
static const struct clksel_rate common_clkout_src_core_rates[] = {
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	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_sys_rates[] = {
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	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_96m_rates[] = {
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	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel_rate common_clkout_src_54m_rates[] = {
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	{ .div = 1, .val = 3, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel common_clkout_src_clksel[] = {
	{ .parent = &core_ck,	  .rates = common_clkout_src_core_rates },
	{ .parent = &sys_ck,	  .rates = common_clkout_src_sys_rates },
	{ .parent = &func_96m_ck, .rates = common_clkout_src_96m_rates },
	{ .parent = &func_54m_ck, .rates = common_clkout_src_54m_rates },
	{ .parent = NULL }
};

static struct clk sys_clkout_src = {
	.name		= "sys_clkout_src",
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	.ops		= &clkops_omap2_dflt,
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	.parent		= &func_54m_ck,
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	.clkdm_name	= "wkup_clkdm",
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	.enable_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.enable_bit	= OMAP24XX_CLKOUT_EN_SHIFT,
	.init		= &omap2_init_clksel_parent,
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	.clksel_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.clksel_mask	= OMAP24XX_CLKOUT_SOURCE_MASK,
	.clksel		= common_clkout_src_clksel,
	.recalc		= &omap2_clksel_recalc,
	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
};

static const struct clksel_rate common_clkout_rates[] = {
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	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
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	{ .div = 2, .val = 1, .flags = RATE_IN_24XX },
	{ .div = 4, .val = 2, .flags = RATE_IN_24XX },
	{ .div = 8, .val = 3, .flags = RATE_IN_24XX },
	{ .div = 16, .val = 4, .flags = RATE_IN_24XX },
	{ .div = 0 },
};

static const struct clksel sys_clkout_clksel[] = {
	{ .parent = &sys_clkout_src, .rates = common_clkout_rates },
	{ .parent = NULL }
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};

static struct clk sys_clkout = {
	.name		= "sys_clkout",
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	.ops		= &clkops_null,
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	.parent		= &sys_clkout_src,
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	.clkdm_name	= "wkup_clkdm",
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	.clksel_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.clksel_mask	= OMAP24XX_CLKOUT_DIV_MASK,
	.clksel		= sys_clkout_clksel,
	.recalc		= &omap2_clksel_recalc,
	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
};

/* In 2430, new in 2420 ES2 */
static struct clk sys_clkout2_src = {
	.name		= "sys_clkout2_src",
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	.ops		= &clkops_omap2_dflt,
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	.parent		= &func_54m_ck,
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	.clkdm_name	= "wkup_clkdm",
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	.enable_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.enable_bit	= OMAP2420_CLKOUT2_EN_SHIFT,
	.init		= &omap2_init_clksel_parent,
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	.clksel_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.clksel_mask	= OMAP2420_CLKOUT2_SOURCE_MASK,
	.clksel		= common_clkout_src_clksel,
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	.recalc		= &omap2_clksel_recalc,
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	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
};

static const struct clksel sys_clkout2_clksel[] = {
	{ .parent = &sys_clkout2_src, .rates = common_clkout_rates },
	{ .parent = NULL }
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};

/* In 2430, new in 2420 ES2 */
static struct clk sys_clkout2 = {
	.name		= "sys_clkout2",
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	.ops		= &clkops_null,
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	.parent		= &sys_clkout2_src,
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	.clkdm_name	= "wkup_clkdm",
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	.clksel_reg	= OMAP2420_PRCM_CLKOUT_CTRL,
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	.clksel_mask	= OMAP2420_CLKOUT2_DIV_MASK,
	.clksel		= sys_clkout2_clksel,
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	.recalc		= &omap2_clksel_recalc,
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	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
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};

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static struct clk emul_ck = {
	.name		= "emul_ck",
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	.ops		= &clkops_omap2_dflt,
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	.parent		= &func_54m_ck,
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	.clkdm_name	= "wkup_clkdm",
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	.enable_reg	= OMAP2420_PRCM_CLKEMUL_CTRL,
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	.enable_bit	= OMAP24XX_EMULATION_EN_SHIFT,
	.recalc		= &followparent_recalc,
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};
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/*
 * MPU clock domain
 *	Clocks:
 *		MPU_FCLK, MPU_ICLK
 *		INT_M_FCLK, INT_M_I_CLK
 *
 * - Individual clocks are hardware managed.
 * - Base divider comes from: CM_CLKSEL_MPU
 *
 */
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static const struct clksel_rate mpu_core_rates[] = {
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	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
	{ .div = 4, .val = 4, .flags = RATE_IN_242X },
	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
	{ .div = 0 },
};

static const struct clksel mpu_clksel[] = {
	{ .parent = &core_ck, .rates = mpu_core_rates },
	{ .parent = NULL }
};

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static struct clk mpu_ck = {	/* Control cpu */
	.name		= "mpu_ck",
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	.ops		= &clkops_null,
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	.parent		= &core_ck,
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	.clkdm_name	= "mpu_clkdm",
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	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(MPU_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP24XX_CLKSEL_MPU_MASK,
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	.clksel		= mpu_clksel,
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	.recalc		= &omap2_clksel_recalc,
};
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/*
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 * DSP (2420-UMA+IVA1) clock domain
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 * Clocks:
 *	2420: UMA_FCLK, UMA_ICLK, IVA_MPU, IVA_COP
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 *
 * Won't be too specific here. The core clock comes into this block
 * it is divided then tee'ed. One branch goes directly to xyz enable
 * controls. The other branch gets further divided by 2 then possibly
 * routed into a synchronizer and out of clocks abc.
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 */
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static const struct clksel_rate dsp_fck_core_rates[] = {
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	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
	{ .div = 0 },
};

static const struct clksel dsp_fck_clksel[] = {
	{ .parent = &core_ck, .rates = dsp_fck_core_rates },
	{ .parent = NULL }
};

static struct clk dsp_fck = {
	.name		= "dsp_fck",
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	.ops		= &clkops_omap2_dflt_wait,
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	.parent		= &core_ck,
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	.clkdm_name	= "dsp_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_CM_FCLKEN_DSP_EN_DSP_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP24XX_CLKSEL_DSP_MASK,
	.clksel		= dsp_fck_clksel,
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	.recalc		= &omap2_clksel_recalc,
};

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static const struct clksel dsp_ick_clksel[] = {
	{ .parent = &dsp_fck, .rates = dsp_ick_rates },
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	{ .parent = NULL }
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};

static struct clk dsp_ick = {
	.name		= "dsp_ick",	 /* apparently ipi and isp */
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	.ops		= &clkops_omap2_iclk_dflt_wait,
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	.parent		= &dsp_fck,
	.clkdm_name	= "dsp_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP2420_EN_DSP_IPI_SHIFT,	      /* for ipi */
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	.clksel_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP24XX_CLKSEL_DSP_IF_MASK,
	.clksel		= dsp_ick_clksel,
	.recalc		= &omap2_clksel_recalc,
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};

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/*
 * The IVA1 is an ARM7 core on the 2420 that has nothing to do with
 * the C54x, but which is contained in the DSP powerdomain.  Does not
 * exist on later OMAPs.
 */
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static struct clk iva1_ifck = {
	.name		= "iva1_ifck",
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	.ops		= &clkops_omap2_dflt_wait,
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	.parent		= &core_ck,
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	.clkdm_name	= "iva1_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP2420_EN_IVA_COP_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP2420_CLKSEL_IVA_MASK,
	.clksel		= dsp_fck_clksel,
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	.recalc		= &omap2_clksel_recalc,
};

/* IVA1 mpu/int/i/f clocks are /2 of parent */
static struct clk iva1_mpu_int_ifck = {
	.name		= "iva1_mpu_int_ifck",
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	.ops		= &clkops_omap2_dflt_wait,
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	.parent		= &iva1_ifck,
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	.clkdm_name	= "iva1_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(OMAP24XX_DSP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP2420_EN_IVA_MPU_SHIFT,
	.fixed_div	= 2,
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	.recalc		= &omap_fixed_divisor_recalc,
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};

/*
 * L3 clock domain
 * L3 clocks are used for both interface and functional clocks to
 * multiple entities. Some of these clocks are completely managed
 * by hardware, and some others allow software control. Hardware
 * managed ones general are based on directly CLK_REQ signals and
 * various auto idle settings. The functional spec sets many of these
 * as 'tie-high' for their enables.
 *
 * I-CLOCKS:
 *	L3-Interconnect, SMS, GPMC, SDRC, OCM_RAM, OCM_ROM, SDMA
 *	CAM, HS-USB.
 * F-CLOCK
 *	SSI.
 *
 * GPMC memories and SDRC have timing and clock sensitive registers which
 * may very well need notification when the clock changes. Currently for low
 * operating points, these are taken care of in sleep.S.
 */
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static const struct clksel_rate core_l3_core_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
	{ .div = 2, .val = 2, .flags = RATE_IN_242X },
524
	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
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	{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
	{ .div = 16, .val = 16, .flags = RATE_IN_242X },
	{ .div = 0 }
};

static const struct clksel core_l3_clksel[] = {
	{ .parent = &core_ck, .rates = core_l3_core_rates },
	{ .parent = NULL }
};

537 538
static struct clk core_l3_ck = {	/* Used for ick and fck, interconnect */
	.name		= "core_l3_ck",
539
	.ops		= &clkops_null,
540
	.parent		= &core_ck,
541
	.clkdm_name	= "core_l3_clkdm",
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	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_L3_MASK,
	.clksel		= core_l3_clksel,
545
	.recalc		= &omap2_clksel_recalc,
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};

/* usb_l4_ick */
static const struct clksel_rate usb_l4_ick_core_l3_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
551
	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
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	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
	{ .div = 0 }
};

static const struct clksel usb_l4_ick_clksel[] = {
	{ .parent = &core_l3_ck, .rates = usb_l4_ick_core_l3_rates },
	{ .parent = NULL },
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};

561
/* It is unclear from TRM whether usb_l4_ick is really in L3 or L4 clkdm */
562 563
static struct clk usb_l4_ick = {	/* FS-USB interface clock */
	.name		= "usb_l4_ick",
564
	.ops		= &clkops_omap2_iclk_dflt_wait,
565
	.parent		= &core_l3_ck,
566
	.clkdm_name	= "core_l4_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_USB_MASK,
	.clksel		= usb_l4_ick_clksel,
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	.recalc		= &omap2_clksel_recalc,
};

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/*
 * L4 clock management domain
 *
 * This domain contains lots of interface clocks from the L4 interface, some
 * functional clocks.	Fixed APLL functional source clocks are managed in
 * this domain.
 */
static const struct clksel_rate l4_core_l3_rates[] = {
583
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
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	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
	{ .div = 0 }
};

static const struct clksel l4_clksel[] = {
	{ .parent = &core_l3_ck, .rates = l4_core_l3_rates },
	{ .parent = NULL }
};

static struct clk l4_ck = {		/* used both as an ick and fck */
	.name		= "l4_ck",
595
	.ops		= &clkops_null,
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	.parent		= &core_l3_ck,
	.clkdm_name	= "core_l4_clkdm",
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_L4_MASK,
	.clksel		= l4_clksel,
	.recalc		= &omap2_clksel_recalc,
};

604 605 606 607
/*
 * SSI is in L3 management domain, its direct parent is core not l3,
 * many core power domain entities are grouped into the L3 clock
 * domain.
608
 * SSI_SSR_FCLK, SSI_SST_FCLK, SSI_L4_ICLK
609 610 611
 *
 * ssr = core/1/2/3/4/5, sst = 1/2 ssr.
 */
612 613
static const struct clksel_rate ssi_ssr_sst_fck_core_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
614
	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
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	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
	{ .div = 0 }
};

static const struct clksel ssi_ssr_sst_fck_clksel[] = {
	{ .parent = &core_ck, .rates = ssi_ssr_sst_fck_core_rates },
	{ .parent = NULL }
};

627 628
static struct clk ssi_ssr_sst_fck = {
	.name		= "ssi_fck",
629
	.ops		= &clkops_omap2_dflt_wait,
630
	.parent		= &core_ck,
631
	.clkdm_name	= "core_l3_clkdm",
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	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_SSI_MASK,
	.clksel		= ssi_ssr_sst_fck_clksel,
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	.recalc		= &omap2_clksel_recalc,
};

640 641 642 643 644 645
/*
 * Presumably this is the same as SSI_ICLK.
 * TRM contradicts itself on what clockdomain SSI_ICLK is in
 */
static struct clk ssi_l4_ick = {
	.name		= "ssi_l4_ick",
646
	.ops		= &clkops_omap2_iclk_dflt_wait,
647 648 649 650 651 652 653
	.parent		= &l4_ck,
	.clkdm_name	= "core_l4_clkdm",
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
	.enable_bit	= OMAP24XX_EN_SSI_SHIFT,
	.recalc		= &followparent_recalc,
};

654

655 656 657 658 659 660 661 662 663 664 665
/*
 * GFX clock domain
 *	Clocks:
 * GFX_FCLK, GFX_ICLK
 * GFX_CG1(2d), GFX_CG2(3d)
 *
 * GFX_FCLK runs from L3, and is divided by (1,2,3,4)
 * The 2d and 3d clocks run at a hardware determined
 * divided value of fclk.
 *
 */
666 667 668 669 670 671 672

/* This clksel struct is shared between gfx_3d_fck and gfx_2d_fck */
static const struct clksel gfx_fck_clksel[] = {
	{ .parent = &core_l3_ck, .rates = gfx_l3_rates },
	{ .parent = NULL },
};

673 674
static struct clk gfx_3d_fck = {
	.name		= "gfx_3d_fck",
675
	.ops		= &clkops_omap2_dflt_wait,
676
	.parent		= &core_l3_ck,
677
	.clkdm_name	= "gfx_clkdm",
678 679 680 681 682
	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_EN_3D_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
	.clksel		= gfx_fck_clksel,
683
	.recalc		= &omap2_clksel_recalc,
684 685
	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
686 687 688 689
};

static struct clk gfx_2d_fck = {
	.name		= "gfx_2d_fck",
690
	.ops		= &clkops_omap2_dflt_wait,
691
	.parent		= &core_l3_ck,
692
	.clkdm_name	= "gfx_clkdm",
693 694 695 696 697
	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_EN_2D_SHIFT,
	.clksel_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_CLKSEL),
	.clksel_mask	= OMAP_CLKSEL_GFX_MASK,
	.clksel		= gfx_fck_clksel,
698 699 700
	.recalc		= &omap2_clksel_recalc,
};

701
/* This interface clock does not have a CM_AUTOIDLE bit */
702 703
static struct clk gfx_ick = {
	.name		= "gfx_ick",		/* From l3 */
704
	.ops		= &clkops_omap2_dflt_wait,
705
	.parent		= &core_l3_ck,
706
	.clkdm_name	= "gfx_clkdm",
707 708 709
	.enable_reg	= OMAP_CM_REGADDR(GFX_MOD, CM_ICLKEN),
	.enable_bit	= OMAP_EN_GFX_SHIFT,
	.recalc		= &followparent_recalc,
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};

/*
 * DSS clock domain
 * CLOCKs:
 * DSS_L4_ICLK, DSS_L3_ICLK,
 * DSS_CLK1, DSS_CLK2, DSS_54MHz_CLK
 *
 * DSS is both initiator and target.
 */
720 721 722
/* XXX Add RATE_NOT_VALIDATED */

static const struct clksel_rate dss1_fck_sys_rates[] = {
723
	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel_rate dss1_fck_core_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
	{ .div = 2, .val = 2, .flags = RATE_IN_24XX },
	{ .div = 3, .val = 3, .flags = RATE_IN_24XX },
	{ .div = 4, .val = 4, .flags = RATE_IN_24XX },
	{ .div = 5, .val = 5, .flags = RATE_IN_24XX },
	{ .div = 6, .val = 6, .flags = RATE_IN_24XX },
	{ .div = 8, .val = 8, .flags = RATE_IN_24XX },
	{ .div = 9, .val = 9, .flags = RATE_IN_24XX },
	{ .div = 12, .val = 12, .flags = RATE_IN_24XX },
737
	{ .div = 16, .val = 16, .flags = RATE_IN_24XX },
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	{ .div = 0 }
};

static const struct clksel dss1_fck_clksel[] = {
	{ .parent = &sys_ck,  .rates = dss1_fck_sys_rates },
	{ .parent = &core_ck, .rates = dss1_fck_core_rates },
	{ .parent = NULL },
};

747 748
static struct clk dss_ick = {		/* Enables both L3,L4 ICLK's */
	.name		= "dss_ick",
749
	.ops		= &clkops_omap2_iclk_dflt,
750
	.parent		= &l4_ck,	/* really both l3 and l4 */
751
	.clkdm_name	= "dss_clkdm",
752 753 754
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
	.recalc		= &followparent_recalc,
755 756 757 758
};

static struct clk dss1_fck = {
	.name		= "dss1_fck",
759
	.ops		= &clkops_omap2_dflt,
760
	.parent		= &core_ck,		/* Core or sys */
761
	.clkdm_name	= "dss_clkdm",
762 763 764 765 766 767
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_DSS1_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_DSS1_MASK,
	.clksel		= dss1_fck_clksel,
768
	.recalc		= &omap2_clksel_recalc,
769 770 771
};

static const struct clksel_rate dss2_fck_sys_rates[] = {
772
	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
773 774 775 776
	{ .div = 0 }
};

static const struct clksel_rate dss2_fck_48m_rates[] = {
777
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
778 779 780 781 782 783 784
	{ .div = 0 }
};

static const struct clksel dss2_fck_clksel[] = {
	{ .parent = &sys_ck,	  .rates = dss2_fck_sys_rates },
	{ .parent = &func_48m_ck, .rates = dss2_fck_48m_rates },
	{ .parent = NULL }
785 786 787 788
};

static struct clk dss2_fck = {		/* Alt clk used in power management */
	.name		= "dss2_fck",
789
	.ops		= &clkops_omap2_dflt,
790
	.parent		= &sys_ck,		/* fixed at sys_ck or 48MHz */
791
	.clkdm_name	= "dss_clkdm",
792 793 794 795 796 797
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_DSS2_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_DSS2_MASK,
	.clksel		= dss2_fck_clksel,
798
	.recalc		= &omap2_clksel_recalc,
799 800 801 802
};

static struct clk dss_54m_fck = {	/* Alt clk used in power management */
	.name		= "dss_54m_fck",	/* 54m tv clk */
803
	.ops		= &clkops_omap2_dflt_wait,
804
	.parent		= &func_54m_ck,
805
	.clkdm_name	= "dss_clkdm",
806 807 808
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_TV_SHIFT,
	.recalc		= &followparent_recalc,
809 810
};

811 812 813 814 815 816 817 818
static struct clk wu_l4_ick = {
	.name		= "wu_l4_ick",
	.ops		= &clkops_null,
	.parent		= &sys_ck,
	.clkdm_name	= "wkup_clkdm",
	.recalc		= &followparent_recalc,
};

819 820 821 822 823 824
/*
 * CORE power domain ICLK & FCLK defines.
 * Many of the these can have more than one possible parent. Entries
 * here will likely have an L4 interface parent, and may have multiple
 * functional clock parents.
 */
825
static const struct clksel_rate gpt_alt_rates[] = {
826
	{ .div = 1, .val = 2, .flags = RATE_IN_24XX },
827 828 829 830 831 832 833 834 835 836
	{ .div = 0 }
};

static const struct clksel omap24xx_gpt_clksel[] = {
	{ .parent = &func_32k_ck, .rates = gpt_32k_rates },
	{ .parent = &sys_ck,	  .rates = gpt_sys_rates },
	{ .parent = &alt_ck,	  .rates = gpt_alt_rates },
	{ .parent = NULL },
};

837 838
static struct clk gpt1_ick = {
	.name		= "gpt1_ick",
839
	.ops		= &clkops_omap2_iclk_dflt_wait,
840 841
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
842 843 844
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
	.recalc		= &followparent_recalc,
845 846 847 848
};

static struct clk gpt1_fck = {
	.name		= "gpt1_fck",
849
	.ops		= &clkops_omap2_dflt_wait,
850
	.parent		= &func_32k_ck,
851
	.clkdm_name	= "core_l4_clkdm",
852 853 854 855 856 857 858 859 860
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_EN_GPT1_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT1_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
	.round_rate	= &omap2_clksel_round_rate,
	.set_rate	= &omap2_clksel_set_rate
861 862 863 864
};

static struct clk gpt2_ick = {
	.name		= "gpt2_ick",
865
	.ops		= &clkops_omap2_iclk_dflt_wait,
866
	.parent		= &l4_ck,
867
	.clkdm_name	= "core_l4_clkdm",
868 869 870
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
	.recalc		= &followparent_recalc,
871 872 873 874
};

static struct clk gpt2_fck = {
	.name		= "gpt2_fck",
875
	.ops		= &clkops_omap2_dflt_wait,
876
	.parent		= &func_32k_ck,
877
	.clkdm_name	= "core_l4_clkdm",
878 879 880 881 882 883 884
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT2_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT2_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
885 886 887 888
};

static struct clk gpt3_ick = {
	.name		= "gpt3_ick",
889
	.ops		= &clkops_omap2_iclk_dflt_wait,
890
	.parent		= &l4_ck,
891
	.clkdm_name	= "core_l4_clkdm",
892 893 894
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
	.recalc		= &followparent_recalc,
895 896 897 898
};

static struct clk gpt3_fck = {
	.name		= "gpt3_fck",
899
	.ops		= &clkops_omap2_dflt_wait,
900
	.parent		= &func_32k_ck,
901
	.clkdm_name	= "core_l4_clkdm",
902 903 904 905 906 907 908
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT3_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT3_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
909 910 911 912
};

static struct clk gpt4_ick = {
	.name		= "gpt4_ick",
913
	.ops		= &clkops_omap2_iclk_dflt_wait,
914
	.parent		= &l4_ck,
915
	.clkdm_name	= "core_l4_clkdm",
916 917 918
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
	.recalc		= &followparent_recalc,
919 920 921 922
};

static struct clk gpt4_fck = {
	.name		= "gpt4_fck",
923
	.ops		= &clkops_omap2_dflt_wait,
924
	.parent		= &func_32k_ck,
925
	.clkdm_name	= "core_l4_clkdm",
926 927 928 929 930 931 932
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT4_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT4_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
933 934 935 936
};

static struct clk gpt5_ick = {
	.name		= "gpt5_ick",
937
	.ops		= &clkops_omap2_iclk_dflt_wait,
938
	.parent		= &l4_ck,
939
	.clkdm_name	= "core_l4_clkdm",
940 941 942
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
	.recalc		= &followparent_recalc,
943 944 945 946
};

static struct clk gpt5_fck = {
	.name		= "gpt5_fck",
947
	.ops		= &clkops_omap2_dflt_wait,
948
	.parent		= &func_32k_ck,
949
	.clkdm_name	= "core_l4_clkdm",
950 951 952 953 954 955 956
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT5_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT5_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
957 958 959 960
};

static struct clk gpt6_ick = {
	.name		= "gpt6_ick",
961
	.ops		= &clkops_omap2_iclk_dflt_wait,
962
	.parent		= &l4_ck,
963
	.clkdm_name	= "core_l4_clkdm",
964 965 966
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
	.recalc		= &followparent_recalc,
967 968 969 970
};

static struct clk gpt6_fck = {
	.name		= "gpt6_fck",
971
	.ops		= &clkops_omap2_dflt_wait,
972
	.parent		= &func_32k_ck,
973
	.clkdm_name	= "core_l4_clkdm",
974 975 976 977 978 979 980
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT6_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT6_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
981 982 983 984
};

static struct clk gpt7_ick = {
	.name		= "gpt7_ick",
985
	.ops		= &clkops_omap2_iclk_dflt_wait,
986
	.parent		= &l4_ck,
987
	.clkdm_name	= "core_l4_clkdm",
988 989 990
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
	.recalc		= &followparent_recalc,
991 992 993 994
};

static struct clk gpt7_fck = {
	.name		= "gpt7_fck",
995
	.ops		= &clkops_omap2_dflt_wait,
996
	.parent		= &func_32k_ck,
997
	.clkdm_name	= "core_l4_clkdm",
998 999 1000 1001 1002 1003 1004
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT7_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT7_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1005 1006 1007 1008
};

static struct clk gpt8_ick = {
	.name		= "gpt8_ick",
1009
	.ops		= &clkops_omap2_iclk_dflt_wait,
1010
	.parent		= &l4_ck,
1011
	.clkdm_name	= "core_l4_clkdm",
1012 1013 1014
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
	.recalc		= &followparent_recalc,
1015 1016 1017 1018
};

static struct clk gpt8_fck = {
	.name		= "gpt8_fck",
1019
	.ops		= &clkops_omap2_dflt_wait,
1020
	.parent		= &func_32k_ck,
1021
	.clkdm_name	= "core_l4_clkdm",
1022 1023 1024 1025 1026 1027 1028
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT8_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT8_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1029 1030 1031 1032
};

static struct clk gpt9_ick = {
	.name		= "gpt9_ick",
1033
	.ops		= &clkops_omap2_iclk_dflt_wait,
1034
	.parent		= &l4_ck,
1035
	.clkdm_name	= "core_l4_clkdm",
1036 1037 1038
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
	.recalc		= &followparent_recalc,
1039 1040 1041 1042
};

static struct clk gpt9_fck = {
	.name		= "gpt9_fck",
1043
	.ops		= &clkops_omap2_dflt_wait,
1044
	.parent		= &func_32k_ck,
1045
	.clkdm_name	= "core_l4_clkdm",
1046 1047 1048 1049 1050 1051 1052
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT9_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT9_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1053 1054 1055 1056
};

static struct clk gpt10_ick = {
	.name		= "gpt10_ick",
1057
	.ops		= &clkops_omap2_iclk_dflt_wait,
1058
	.parent		= &l4_ck,
1059
	.clkdm_name	= "core_l4_clkdm",
1060 1061 1062
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
	.recalc		= &followparent_recalc,
1063 1064 1065 1066
};

static struct clk gpt10_fck = {
	.name		= "gpt10_fck",
1067
	.ops		= &clkops_omap2_dflt_wait,
1068
	.parent		= &func_32k_ck,
1069
	.clkdm_name	= "core_l4_clkdm",
1070 1071 1072 1073 1074 1075 1076
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT10_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT10_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1077 1078 1079 1080
};

static struct clk gpt11_ick = {
	.name		= "gpt11_ick",
1081
	.ops		= &clkops_omap2_iclk_dflt_wait,
1082
	.parent		= &l4_ck,
1083
	.clkdm_name	= "core_l4_clkdm",
1084 1085 1086
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
	.recalc		= &followparent_recalc,
1087 1088 1089 1090
};

static struct clk gpt11_fck = {
	.name		= "gpt11_fck",
1091
	.ops		= &clkops_omap2_dflt_wait,
1092
	.parent		= &func_32k_ck,
1093
	.clkdm_name	= "core_l4_clkdm",
1094 1095 1096 1097 1098 1099 1100
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT11_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT11_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1101 1102 1103 1104
};

static struct clk gpt12_ick = {
	.name		= "gpt12_ick",
1105
	.ops		= &clkops_omap2_iclk_dflt_wait,
1106
	.parent		= &l4_ck,
1107
	.clkdm_name	= "core_l4_clkdm",
1108 1109 1110
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
	.recalc		= &followparent_recalc,
1111 1112 1113 1114
};

static struct clk gpt12_fck = {
	.name		= "gpt12_fck",
1115
	.ops		= &clkops_omap2_dflt_wait,
1116
	.parent		= &secure_32k_ck,
1117
	.clkdm_name	= "core_l4_clkdm",
1118 1119 1120 1121 1122 1123 1124
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_GPT12_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL2),
	.clksel_mask	= OMAP24XX_CLKSEL_GPT12_MASK,
	.clksel		= omap24xx_gpt_clksel,
	.recalc		= &omap2_clksel_recalc,
1125 1126 1127
};

static struct clk mcbsp1_ick = {
1128
	.name		= "mcbsp1_ick",
1129
	.ops		= &clkops_omap2_iclk_dflt_wait,
1130
	.parent		= &l4_ck,
1131
	.clkdm_name	= "core_l4_clkdm",
1132 1133 1134
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
	.recalc		= &followparent_recalc,
1135 1136
};

1137 1138 1139 1140 1141 1142 1143 1144 1145 1146 1147 1148 1149 1150 1151 1152
static const struct clksel_rate common_mcbsp_96m_rates[] = {
	{ .div = 1, .val = 0, .flags = RATE_IN_24XX },
	{ .div = 0 }
};

static const struct clksel_rate common_mcbsp_mcbsp_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_24XX },
	{ .div = 0 }
};

static const struct clksel mcbsp_fck_clksel[] = {
	{ .parent = &func_96m_ck,  .rates = common_mcbsp_96m_rates },
	{ .parent = &mcbsp_clks,   .rates = common_mcbsp_mcbsp_rates },
	{ .parent = NULL }
};

1153
static struct clk mcbsp1_fck = {
1154
	.name		= "mcbsp1_fck",
1155
	.ops		= &clkops_omap2_dflt_wait,
1156
	.parent		= &func_96m_ck,
1157
	.init		= &omap2_init_clksel_parent,
1158
	.clkdm_name	= "core_l4_clkdm",
1159 1160
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_MCBSP1_SHIFT,
1161 1162 1163 1164
	.clksel_reg	= OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
	.clksel_mask	= OMAP2_MCBSP1_CLKS_MASK,
	.clksel		= mcbsp_fck_clksel,
	.recalc		= &omap2_clksel_recalc,
1165 1166 1167
};

static struct clk mcbsp2_ick = {
1168
	.name		= "mcbsp2_ick",
1169
	.ops		= &clkops_omap2_iclk_dflt_wait,
1170
	.parent		= &l4_ck,
1171
	.clkdm_name	= "core_l4_clkdm",
1172 1173 1174
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
	.recalc		= &followparent_recalc,
1175 1176 1177
};

static struct clk mcbsp2_fck = {
1178
	.name		= "mcbsp2_fck",
1179
	.ops		= &clkops_omap2_dflt_wait,
1180
	.parent		= &func_96m_ck,
1181
	.init		= &omap2_init_clksel_parent,
1182
	.clkdm_name	= "core_l4_clkdm",
1183 1184
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_MCBSP2_SHIFT,
1185 1186 1187 1188
	.clksel_reg	= OMAP242X_CTRL_REGADDR(OMAP2_CONTROL_DEVCONF0),
	.clksel_mask	= OMAP2_MCBSP2_CLKS_MASK,
	.clksel		= mcbsp_fck_clksel,
	.recalc		= &omap2_clksel_recalc,
1189 1190 1191
};

static struct clk mcspi1_ick = {
1192
	.name		= "mcspi1_ick",
1193
	.ops		= &clkops_omap2_iclk_dflt_wait,
1194
	.parent		= &l4_ck,
1195
	.clkdm_name	= "core_l4_clkdm",
1196 1197 1198
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
	.recalc		= &followparent_recalc,
1199 1200 1201
};

static struct clk mcspi1_fck = {
1202
	.name		= "mcspi1_fck",
1203
	.ops		= &clkops_omap2_dflt_wait,
1204
	.parent		= &func_48m_ck,
1205
	.clkdm_name	= "core_l4_clkdm",
1206 1207 1208
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_MCSPI1_SHIFT,
	.recalc		= &followparent_recalc,
1209 1210 1211
};

static struct clk mcspi2_ick = {
1212
	.name		= "mcspi2_ick",
1213
	.ops		= &clkops_omap2_iclk_dflt_wait,
1214
	.parent		= &l4_ck,
1215
	.clkdm_name	= "core_l4_clkdm",
1216 1217 1218
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
	.recalc		= &followparent_recalc,
1219 1220 1221
};

static struct clk mcspi2_fck = {
1222
	.name		= "mcspi2_fck",
1223
	.ops		= &clkops_omap2_dflt_wait,
1224
	.parent		= &func_48m_ck,
1225
	.clkdm_name	= "core_l4_clkdm",
1226 1227 1228
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_MCSPI2_SHIFT,
	.recalc		= &followparent_recalc,
1229 1230 1231 1232
};

static struct clk uart1_ick = {
	.name		= "uart1_ick",
1233
	.ops		= &clkops_omap2_iclk_dflt_wait,
1234
	.parent		= &l4_ck,
1235
	.clkdm_name	= "core_l4_clkdm",
1236 1237 1238
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
	.recalc		= &followparent_recalc,
1239 1240 1241 1242
};

static struct clk uart1_fck = {
	.name		= "uart1_fck",
1243
	.ops		= &clkops_omap2_dflt_wait,
1244
	.parent		= &func_48m_ck,
1245
	.clkdm_name	= "core_l4_clkdm",
1246 1247 1248
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_UART1_SHIFT,
	.recalc		= &followparent_recalc,
1249 1250 1251 1252
};

static struct clk uart2_ick = {
	.name		= "uart2_ick",
1253
	.ops		= &clkops_omap2_iclk_dflt_wait,
1254
	.parent		= &l4_ck,
1255
	.clkdm_name	= "core_l4_clkdm",
1256 1257 1258
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
	.recalc		= &followparent_recalc,
1259 1260 1261 1262
};

static struct clk uart2_fck = {
	.name		= "uart2_fck",
1263
	.ops		= &clkops_omap2_dflt_wait,
1264
	.parent		= &func_48m_ck,
1265
	.clkdm_name	= "core_l4_clkdm",
1266 1267 1268
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_UART2_SHIFT,
	.recalc		= &followparent_recalc,
1269 1270 1271 1272
};

static struct clk uart3_ick = {
	.name		= "uart3_ick",
1273
	.ops		= &clkops_omap2_iclk_dflt_wait,
1274
	.parent		= &l4_ck,
1275
	.clkdm_name	= "core_l4_clkdm",
1276 1277 1278
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN2),
	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
	.recalc		= &followparent_recalc,
1279 1280 1281 1282
};

static struct clk uart3_fck = {
	.name		= "uart3_fck",
1283
	.ops		= &clkops_omap2_dflt_wait,
1284
	.parent		= &func_48m_ck,
1285
	.clkdm_name	= "core_l4_clkdm",
1286 1287 1288
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
	.enable_bit	= OMAP24XX_EN_UART3_SHIFT,
	.recalc		= &followparent_recalc,
1289 1290 1291 1292
};

static struct clk gpios_ick = {
	.name		= "gpios_ick",
1293
	.ops		= &clkops_omap2_iclk_dflt_wait,
1294 1295
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
1296 1297 1298
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
	.recalc		= &followparent_recalc,
1299 1300 1301 1302
};

static struct clk gpios_fck = {
	.name		= "gpios_fck",
1303
	.ops		= &clkops_omap2_dflt_wait,
1304
	.parent		= &func_32k_ck,
1305
	.clkdm_name	= "wkup_clkdm",
1306 1307 1308
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_EN_GPIOS_SHIFT,
	.recalc		= &followparent_recalc,
1309 1310 1311 1312
};

static struct clk mpu_wdt_ick = {
	.name		= "mpu_wdt_ick",
1313
	.ops		= &clkops_omap2_iclk_dflt_wait,
1314 1315
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
1316 1317 1318
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
	.recalc		= &followparent_recalc,
1319 1320 1321 1322
};

static struct clk mpu_wdt_fck = {
	.name		= "mpu_wdt_fck",
1323
	.ops		= &clkops_omap2_dflt_wait,
1324
	.parent		= &func_32k_ck,
1325
	.clkdm_name	= "wkup_clkdm",
1326 1327 1328
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_FCLKEN),
	.enable_bit	= OMAP24XX_EN_MPU_WDT_SHIFT,
	.recalc		= &followparent_recalc,
1329 1330 1331 1332
};

static struct clk sync_32k_ick = {
	.name		= "sync_32k_ick",
1333
	.ops		= &clkops_omap2_iclk_dflt_wait,
1334 1335
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
1336
	.flags		= ENABLE_ON_INIT,
1337 1338 1339
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_32KSYNC_SHIFT,
	.recalc		= &followparent_recalc,
1340
};
1341

1342 1343
static struct clk wdt1_ick = {
	.name		= "wdt1_ick",
1344
	.ops		= &clkops_omap2_iclk_dflt_wait,
1345 1346
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
1347 1348 1349
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_WDT1_SHIFT,
	.recalc		= &followparent_recalc,
1350
};
1351

1352 1353
static struct clk omapctrl_ick = {
	.name		= "omapctrl_ick",
1354
	.ops		= &clkops_omap2_iclk_dflt_wait,
1355 1356
	.parent		= &wu_l4_ick,
	.clkdm_name	= "wkup_clkdm",
1357
	.flags		= ENABLE_ON_INIT,
1358 1359 1360
	.enable_reg	= OMAP_CM_REGADDR(WKUP_MOD, CM_ICLKEN),
	.enable_bit	= OMAP24XX_EN_OMAPCTRL_SHIFT,
	.recalc		= &followparent_recalc,
1361
};
1362

1363 1364
static struct clk cam_ick = {
	.name		= "cam_ick",
1365
	.ops		= &clkops_omap2_iclk_dflt,
1366
	.parent		= &l4_ck,
1367
	.clkdm_name	= "core_l4_clkdm",
1368 1369 1370
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
	.recalc		= &followparent_recalc,
1371 1372
};

1373 1374 1375 1376 1377
/*
 * cam_fck controls both CAM_MCLK and CAM_FCLK.  It should probably be
 * split into two separate clocks, since the parent clocks are different
 * and the clockdomains are also different.
 */
1378 1379
static struct clk cam_fck = {
	.name		= "cam_fck",
1380
	.ops		= &clkops_omap2_dflt,
1381
	.parent		= &func_96m_ck,
1382
	.clkdm_name	= "core_l3_clkdm",
1383 1384 1385
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_CAM_SHIFT,
	.recalc		= &followparent_recalc,
1386 1387 1388 1389
};

static struct clk mailboxes_ick = {
	.name		= "mailboxes_ick",
1390
	.ops		= &clkops_omap2_iclk_dflt_wait,
1391
	.parent		= &l4_ck,
1392
	.clkdm_name	= "core_l4_clkdm",
1393 1394 1395
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MAILBOXES_SHIFT,
	.recalc		= &followparent_recalc,
1396 1397 1398 1399
};

static struct clk wdt4_ick = {
	.name		= "wdt4_ick",
1400
	.ops		= &clkops_omap2_iclk_dflt_wait,
1401
	.parent		= &l4_ck,
1402
	.clkdm_name	= "core_l4_clkdm",
1403 1404 1405
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
	.recalc		= &followparent_recalc,
1406 1407 1408 1409
};

static struct clk wdt4_fck = {
	.name		= "wdt4_fck",
1410
	.ops		= &clkops_omap2_dflt_wait,
1411
	.parent		= &func_32k_ck,
1412
	.clkdm_name	= "core_l4_clkdm",
1413 1414 1415
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_WDT4_SHIFT,
	.recalc		= &followparent_recalc,
1416 1417 1418 1419
};

static struct clk wdt3_ick = {
	.name		= "wdt3_ick",
1420
	.ops		= &clkops_omap2_iclk_dflt_wait,
1421
	.parent		= &l4_ck,
1422
	.clkdm_name	= "core_l4_clkdm",
1423 1424 1425
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
	.recalc		= &followparent_recalc,
1426 1427 1428 1429
};

static struct clk wdt3_fck = {
	.name		= "wdt3_fck",
1430
	.ops		= &clkops_omap2_dflt_wait,
1431
	.parent		= &func_32k_ck,
1432
	.clkdm_name	= "core_l4_clkdm",
1433 1434 1435
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_WDT3_SHIFT,
	.recalc		= &followparent_recalc,
1436 1437 1438 1439
};

static struct clk mspro_ick = {
	.name		= "mspro_ick",
1440
	.ops		= &clkops_omap2_iclk_dflt_wait,
1441
	.parent		= &l4_ck,
1442
	.clkdm_name	= "core_l4_clkdm",
1443 1444 1445
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
	.recalc		= &followparent_recalc,
1446 1447 1448 1449
};

static struct clk mspro_fck = {
	.name		= "mspro_fck",
1450
	.ops		= &clkops_omap2_dflt_wait,
1451
	.parent		= &func_96m_ck,
1452
	.clkdm_name	= "core_l4_clkdm",
1453 1454 1455
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_MSPRO_SHIFT,
	.recalc		= &followparent_recalc,
1456 1457 1458 1459
};

static struct clk mmc_ick = {
	.name		= "mmc_ick",
1460
	.ops		= &clkops_omap2_iclk_dflt_wait,
1461
	.parent		= &l4_ck,
1462
	.clkdm_name	= "core_l4_clkdm",
1463 1464 1465
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
	.recalc		= &followparent_recalc,
1466 1467 1468 1469
};

static struct clk mmc_fck = {
	.name		= "mmc_fck",
1470
	.ops		= &clkops_omap2_dflt_wait,
1471
	.parent		= &func_96m_ck,
1472
	.clkdm_name	= "core_l4_clkdm",
1473 1474 1475
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_MMC_SHIFT,
	.recalc		= &followparent_recalc,
1476 1477 1478 1479
};

static struct clk fac_ick = {
	.name		= "fac_ick",
1480
	.ops		= &clkops_omap2_iclk_dflt_wait,
1481
	.parent		= &l4_ck,
1482
	.clkdm_name	= "core_l4_clkdm",
1483 1484 1485
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
	.recalc		= &followparent_recalc,
1486 1487 1488 1489
};

static struct clk fac_fck = {
	.name		= "fac_fck",
1490
	.ops		= &clkops_omap2_dflt_wait,
1491
	.parent		= &func_12m_ck,
1492
	.clkdm_name	= "core_l4_clkdm",
1493 1494 1495
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_FAC_SHIFT,
	.recalc		= &followparent_recalc,
1496 1497 1498 1499
};

static struct clk eac_ick = {
	.name		= "eac_ick",
1500
	.ops		= &clkops_omap2_iclk_dflt_wait,
1501
	.parent		= &l4_ck,
1502
	.clkdm_name	= "core_l4_clkdm",
1503 1504 1505
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
	.recalc		= &followparent_recalc,
1506 1507 1508 1509
};

static struct clk eac_fck = {
	.name		= "eac_fck",
1510
	.ops		= &clkops_omap2_dflt_wait,
1511
	.parent		= &func_96m_ck,
1512
	.clkdm_name	= "core_l4_clkdm",
1513 1514 1515
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_EAC_SHIFT,
	.recalc		= &followparent_recalc,
1516 1517 1518 1519
};

static struct clk hdq_ick = {
	.name		= "hdq_ick",
1520
	.ops		= &clkops_omap2_iclk_dflt_wait,
1521
	.parent		= &l4_ck,
1522
	.clkdm_name	= "core_l4_clkdm",
1523 1524 1525
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
	.recalc		= &followparent_recalc,
1526 1527 1528 1529
};

static struct clk hdq_fck = {
	.name		= "hdq_fck",
1530
	.ops		= &clkops_omap2_dflt_wait,
1531
	.parent		= &func_12m_ck,
1532
	.clkdm_name	= "core_l4_clkdm",
1533 1534 1535
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP24XX_EN_HDQ_SHIFT,
	.recalc		= &followparent_recalc,
1536 1537 1538
};

static struct clk i2c2_ick = {
1539
	.name		= "i2c2_ick",
1540
	.ops		= &clkops_omap2_iclk_dflt_wait,
1541
	.parent		= &l4_ck,
1542
	.clkdm_name	= "core_l4_clkdm",
1543 1544 1545
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
	.recalc		= &followparent_recalc,
1546 1547 1548
};

static struct clk i2c2_fck = {
1549
	.name		= "i2c2_fck",
1550
	.ops		= &clkops_omap2_dflt_wait,
1551
	.parent		= &func_12m_ck,
1552
	.clkdm_name	= "core_l4_clkdm",
1553 1554 1555
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_I2C2_SHIFT,
	.recalc		= &followparent_recalc,
1556 1557 1558
};

static struct clk i2c1_ick = {
1559
	.name		= "i2c1_ick",
1560
	.ops		= &clkops_omap2_iclk_dflt_wait,
1561
	.parent		= &l4_ck,
1562
	.clkdm_name	= "core_l4_clkdm",
1563 1564 1565
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
	.recalc		= &followparent_recalc,
1566 1567 1568
};

static struct clk i2c1_fck = {
1569
	.name		= "i2c1_fck",
1570
	.ops		= &clkops_omap2_dflt_wait,
1571
	.parent		= &func_12m_ck,
1572
	.clkdm_name	= "core_l4_clkdm",
1573 1574 1575
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_I2C1_SHIFT,
	.recalc		= &followparent_recalc,
1576 1577
};

1578 1579 1580 1581
/*
 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
 * accesses derived from this data.
 */
1582 1583
static struct clk gpmc_fck = {
	.name		= "gpmc_fck",
1584
	.ops		= &clkops_omap2_iclk_idle_only,
1585
	.parent		= &core_l3_ck,
1586
	.flags		= ENABLE_ON_INIT,
1587
	.clkdm_name	= "core_l3_clkdm",
1588 1589
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
	.enable_bit	= OMAP24XX_AUTO_GPMC_SHIFT,
1590 1591 1592 1593 1594
	.recalc		= &followparent_recalc,
};

static struct clk sdma_fck = {
	.name		= "sdma_fck",
1595
	.ops		= &clkops_null, /* RMK: missing? */
1596
	.parent		= &core_l3_ck,
1597
	.clkdm_name	= "core_l3_clkdm",
1598 1599 1600
	.recalc		= &followparent_recalc,
};

1601 1602 1603 1604
/*
 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
 * accesses derived from this data.
 */
1605 1606
static struct clk sdma_ick = {
	.name		= "sdma_ick",
1607
	.ops		= &clkops_omap2_iclk_idle_only,
1608
	.parent		= &core_l3_ck,
1609
	.clkdm_name	= "core_l3_clkdm",
1610 1611
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
	.enable_bit	= OMAP24XX_AUTO_SDMA_SHIFT,
1612
	.recalc		= &followparent_recalc,
1613 1614
};

P
Paul Walmsley 已提交
1615 1616 1617 1618 1619 1620 1621 1622 1623 1624 1625 1626 1627 1628 1629
/*
 * The enable_reg/enable_bit in this clock is only used for CM_AUTOIDLE
 * accesses derived from this data.
 */
static struct clk sdrc_ick = {
	.name		= "sdrc_ick",
	.ops		= &clkops_omap2_iclk_idle_only,
	.parent		= &core_l3_ck,
	.flags		= ENABLE_ON_INIT,
	.clkdm_name	= "core_l3_clkdm",
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN3),
	.enable_bit	= OMAP24XX_AUTO_SDRC_SHIFT,
	.recalc		= &followparent_recalc,
};

1630 1631
static struct clk vlynq_ick = {
	.name		= "vlynq_ick",
1632
	.ops		= &clkops_omap2_iclk_dflt_wait,
1633
	.parent		= &core_l3_ck,
1634
	.clkdm_name	= "core_l3_clkdm",
1635 1636 1637 1638 1639 1640
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_ICLKEN1),
	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
	.recalc		= &followparent_recalc,
};

static const struct clksel_rate vlynq_fck_96m_rates[] = {
1641
	{ .div = 1, .val = 0, .flags = RATE_IN_242X },
1642 1643 1644 1645 1646 1647 1648 1649 1650 1651 1652 1653
	{ .div = 0 }
};

static const struct clksel_rate vlynq_fck_core_rates[] = {
	{ .div = 1, .val = 1, .flags = RATE_IN_242X },
	{ .div = 2, .val = 2, .flags = RATE_IN_242X },
	{ .div = 3, .val = 3, .flags = RATE_IN_242X },
	{ .div = 4, .val = 4, .flags = RATE_IN_242X },
	{ .div = 6, .val = 6, .flags = RATE_IN_242X },
	{ .div = 8, .val = 8, .flags = RATE_IN_242X },
	{ .div = 9, .val = 9, .flags = RATE_IN_242X },
	{ .div = 12, .val = 12, .flags = RATE_IN_242X },
1654
	{ .div = 16, .val = 16, .flags = RATE_IN_242X },
1655 1656 1657 1658 1659 1660 1661 1662
	{ .div = 18, .val = 18, .flags = RATE_IN_242X },
	{ .div = 0 }
};

static const struct clksel vlynq_fck_clksel[] = {
	{ .parent = &func_96m_ck, .rates = vlynq_fck_96m_rates },
	{ .parent = &core_ck,	  .rates = vlynq_fck_core_rates },
	{ .parent = NULL }
1663 1664 1665 1666
};

static struct clk vlynq_fck = {
	.name		= "vlynq_fck",
1667
	.ops		= &clkops_omap2_dflt_wait,
1668
	.parent		= &func_96m_ck,
1669
	.clkdm_name	= "core_l3_clkdm",
1670 1671 1672 1673 1674 1675 1676
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_FCLKEN1),
	.enable_bit	= OMAP2420_EN_VLYNQ_SHIFT,
	.init		= &omap2_init_clksel_parent,
	.clksel_reg	= OMAP_CM_REGADDR(CORE_MOD, CM_CLKSEL1),
	.clksel_mask	= OMAP2420_CLKSEL_VLYNQ_MASK,
	.clksel		= vlynq_fck_clksel,
	.recalc		= &omap2_clksel_recalc,
1677 1678 1679 1680
};

static struct clk des_ick = {
	.name		= "des_ick",
1681
	.ops		= &clkops_omap2_iclk_dflt_wait,
1682
	.parent		= &l4_ck,
1683
	.clkdm_name	= "core_l4_clkdm",
1684 1685 1686
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
	.enable_bit	= OMAP24XX_EN_DES_SHIFT,
	.recalc		= &followparent_recalc,
1687 1688 1689 1690
};

static struct clk sha_ick = {
	.name		= "sha_ick",
1691
	.ops		= &clkops_omap2_iclk_dflt_wait,
1692
	.parent		= &l4_ck,
1693
	.clkdm_name	= "core_l4_clkdm",
1694 1695 1696
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
	.enable_bit	= OMAP24XX_EN_SHA_SHIFT,
	.recalc		= &followparent_recalc,
1697 1698 1699 1700
};

static struct clk rng_ick = {
	.name		= "rng_ick",
1701
	.ops		= &clkops_omap2_iclk_dflt_wait,
1702
	.parent		= &l4_ck,
1703
	.clkdm_name	= "core_l4_clkdm",
1704 1705 1706
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
	.enable_bit	= OMAP24XX_EN_RNG_SHIFT,
	.recalc		= &followparent_recalc,
1707 1708 1709 1710
};

static struct clk aes_ick = {
	.name		= "aes_ick",
1711
	.ops		= &clkops_omap2_iclk_dflt_wait,
1712
	.parent		= &l4_ck,
1713
	.clkdm_name	= "core_l4_clkdm",
1714 1715 1716
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
	.enable_bit	= OMAP24XX_EN_AES_SHIFT,
	.recalc		= &followparent_recalc,
1717 1718 1719 1720
};

static struct clk pka_ick = {
	.name		= "pka_ick",
1721
	.ops		= &clkops_omap2_iclk_dflt_wait,
1722
	.parent		= &l4_ck,
1723
	.clkdm_name	= "core_l4_clkdm",
1724 1725 1726
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_ICLKEN4),
	.enable_bit	= OMAP24XX_EN_PKA_SHIFT,
	.recalc		= &followparent_recalc,
1727 1728 1729 1730
};

static struct clk usb_fck = {
	.name		= "usb_fck",
1731
	.ops		= &clkops_omap2_dflt_wait,
1732
	.parent		= &func_48m_ck,
1733
	.clkdm_name	= "core_l3_clkdm",
1734 1735 1736
	.enable_reg	= OMAP_CM_REGADDR(CORE_MOD, OMAP24XX_CM_FCLKEN2),
	.enable_bit	= OMAP24XX_EN_USB_SHIFT,
	.recalc		= &followparent_recalc,
1737 1738 1739 1740 1741 1742 1743 1744 1745 1746 1747 1748 1749 1750 1751 1752 1753 1754
};

/*
 * This clock is a composite clock which does entire set changes then
 * forces a rebalance. It keys on the MPU speed, but it really could
 * be any key speed part of a set in the rate table.
 *
 * to really change a set, you need memory table sets which get changed
 * in sram, pre-notifiers & post notifiers, changing the top set, without
 * having low level display recalc's won't work... this is why dpm notifiers
 * work, isr's off, walk a list of clocks already _off_ and not messing with
 * the bus.
 *
 * This clock should have no parent. It embodies the entire upper level
 * active set. A parent will mess up some of the init also.
 */
static struct clk virt_prcm_set = {
	.name		= "virt_prcm_set",
1755
	.ops		= &clkops_null,
1756
	.parent		= &mpu_ck,	/* Indexed by mpu speed, no parent */
1757
	.recalc		= &omap2_table_mpu_recalc,	/* sets are keyed on mpu rate */
1758 1759 1760
	.set_rate	= &omap2_select_table_rate,
	.round_rate	= &omap2_round_to_table_rate,
};
1761

1762 1763 1764 1765 1766

/*
 * clkdev integration
 */

1767
static struct omap_clk omap2420_clks[] = {
1768
	/* external root sources */
1769 1770 1771 1772 1773
	CLK(NULL,	"func_32k_ck",	&func_32k_ck,	CK_242X),
	CLK(NULL,	"secure_32k_ck", &secure_32k_ck, CK_242X),
	CLK(NULL,	"osc_ck",	&osc_ck,	CK_242X),
	CLK(NULL,	"sys_ck",	&sys_ck,	CK_242X),
	CLK(NULL,	"alt_ck",	&alt_ck,	CK_242X),
1774 1775 1776
	CLK("omap-mcbsp.1",	"pad_fck",	&mcbsp_clks,	CK_242X),
	CLK("omap-mcbsp.2",	"pad_fck",	&mcbsp_clks,	CK_242X),
	CLK(NULL,	"mcbsp_clks",	&mcbsp_clks,	CK_242X),
1777
	/* internal analog sources */
1778 1779 1780
	CLK(NULL,	"dpll_ck",	&dpll_ck,	CK_242X),
	CLK(NULL,	"apll96_ck",	&apll96_ck,	CK_242X),
	CLK(NULL,	"apll54_ck",	&apll54_ck,	CK_242X),
1781
	/* internal prcm root sources */
1782 1783
	CLK(NULL,	"func_54m_ck",	&func_54m_ck,	CK_242X),
	CLK(NULL,	"core_ck",	&core_ck,	CK_242X),
1784 1785
	CLK("omap-mcbsp.1",	"prcm_fck",	&func_96m_ck,	CK_242X),
	CLK("omap-mcbsp.2",	"prcm_fck",	&func_96m_ck,	CK_242X),
1786 1787 1788 1789 1790 1791
	CLK(NULL,	"func_96m_ck",	&func_96m_ck,	CK_242X),
	CLK(NULL,	"func_48m_ck",	&func_48m_ck,	CK_242X),
	CLK(NULL,	"func_12m_ck",	&func_12m_ck,	CK_242X),
	CLK(NULL,	"ck_wdt1_osc",	&wdt1_osc_ck,	CK_242X),
	CLK(NULL,	"sys_clkout_src", &sys_clkout_src, CK_242X),
	CLK(NULL,	"sys_clkout",	&sys_clkout,	CK_242X),
1792 1793 1794 1795
	CLK(NULL,	"sys_clkout2_src", &sys_clkout2_src, CK_242X),
	CLK(NULL,	"sys_clkout2",	&sys_clkout2,	CK_242X),
	CLK(NULL,	"emul_ck",	&emul_ck,	CK_242X),
	/* mpu domain clocks */
1796
	CLK(NULL,	"mpu_ck",	&mpu_ck,	CK_242X),
1797
	/* dsp domain clocks */
1798
	CLK(NULL,	"dsp_fck",	&dsp_fck,	CK_242X),
1799 1800 1801 1802
	CLK(NULL,	"dsp_ick",	&dsp_ick,	CK_242X),
	CLK(NULL,	"iva1_ifck",	&iva1_ifck,	CK_242X),
	CLK(NULL,	"iva1_mpu_int_ifck", &iva1_mpu_int_ifck, CK_242X),
	/* GFX domain clocks */
1803 1804 1805
	CLK(NULL,	"gfx_3d_fck",	&gfx_3d_fck,	CK_242X),
	CLK(NULL,	"gfx_2d_fck",	&gfx_2d_fck,	CK_242X),
	CLK(NULL,	"gfx_ick",	&gfx_ick,	CK_242X),
1806
	/* DSS domain clocks */
1807
	CLK("omapdss_dss",	"ick",		&dss_ick,	CK_242X),
1808 1809 1810
	CLK("omapdss_dss",	"fck",		&dss1_fck,	CK_242X),
	CLK("omapdss_dss",	"sys_clk",	&dss2_fck,	CK_242X),
	CLK("omapdss_dss",	"tv_clk",	&dss_54m_fck,	CK_242X),
1811
	/* L3 domain clocks */
1812 1813 1814
	CLK(NULL,	"core_l3_ck",	&core_l3_ck,	CK_242X),
	CLK(NULL,	"ssi_fck",	&ssi_ssr_sst_fck, CK_242X),
	CLK(NULL,	"usb_l4_ick",	&usb_l4_ick,	CK_242X),
1815
	/* L4 domain clocks */
1816 1817
	CLK(NULL,	"l4_ck",	&l4_ck,		CK_242X),
	CLK(NULL,	"ssi_l4_ick",	&ssi_l4_ick,	CK_242X),
1818
	CLK(NULL,	"wu_l4_ick",	&wu_l4_ick,	CK_242X),
1819
	/* virtual meta-group clock */
1820
	CLK(NULL,	"virt_prcm_set", &virt_prcm_set, CK_242X),
1821
	/* general l4 interface ck, multi-parent functional clk */
1822 1823 1824 1825 1826 1827 1828 1829 1830 1831 1832 1833 1834 1835 1836 1837 1838 1839 1840 1841 1842 1843 1844 1845 1846 1847 1848 1849 1850 1851 1852 1853 1854 1855 1856 1857 1858 1859 1860 1861 1862 1863 1864 1865 1866 1867 1868 1869 1870 1871
	CLK(NULL,	"gpt1_ick",	&gpt1_ick,	CK_242X),
	CLK(NULL,	"gpt1_fck",	&gpt1_fck,	CK_242X),
	CLK(NULL,	"gpt2_ick",	&gpt2_ick,	CK_242X),
	CLK(NULL,	"gpt2_fck",	&gpt2_fck,	CK_242X),
	CLK(NULL,	"gpt3_ick",	&gpt3_ick,	CK_242X),
	CLK(NULL,	"gpt3_fck",	&gpt3_fck,	CK_242X),
	CLK(NULL,	"gpt4_ick",	&gpt4_ick,	CK_242X),
	CLK(NULL,	"gpt4_fck",	&gpt4_fck,	CK_242X),
	CLK(NULL,	"gpt5_ick",	&gpt5_ick,	CK_242X),
	CLK(NULL,	"gpt5_fck",	&gpt5_fck,	CK_242X),
	CLK(NULL,	"gpt6_ick",	&gpt6_ick,	CK_242X),
	CLK(NULL,	"gpt6_fck",	&gpt6_fck,	CK_242X),
	CLK(NULL,	"gpt7_ick",	&gpt7_ick,	CK_242X),
	CLK(NULL,	"gpt7_fck",	&gpt7_fck,	CK_242X),
	CLK(NULL,	"gpt8_ick",	&gpt8_ick,	CK_242X),
	CLK(NULL,	"gpt8_fck",	&gpt8_fck,	CK_242X),
	CLK(NULL,	"gpt9_ick",	&gpt9_ick,	CK_242X),
	CLK(NULL,	"gpt9_fck",	&gpt9_fck,	CK_242X),
	CLK(NULL,	"gpt10_ick",	&gpt10_ick,	CK_242X),
	CLK(NULL,	"gpt10_fck",	&gpt10_fck,	CK_242X),
	CLK(NULL,	"gpt11_ick",	&gpt11_ick,	CK_242X),
	CLK(NULL,	"gpt11_fck",	&gpt11_fck,	CK_242X),
	CLK(NULL,	"gpt12_ick",	&gpt12_ick,	CK_242X),
	CLK(NULL,	"gpt12_fck",	&gpt12_fck,	CK_242X),
	CLK("omap-mcbsp.1", "ick",	&mcbsp1_ick,	CK_242X),
	CLK("omap-mcbsp.1", "fck",	&mcbsp1_fck,	CK_242X),
	CLK("omap-mcbsp.2", "ick",	&mcbsp2_ick,	CK_242X),
	CLK("omap-mcbsp.2", "fck",	&mcbsp2_fck,	CK_242X),
	CLK("omap2_mcspi.1", "ick",	&mcspi1_ick,	CK_242X),
	CLK("omap2_mcspi.1", "fck",	&mcspi1_fck,	CK_242X),
	CLK("omap2_mcspi.2", "ick",	&mcspi2_ick,	CK_242X),
	CLK("omap2_mcspi.2", "fck",	&mcspi2_fck,	CK_242X),
	CLK(NULL,	"uart1_ick",	&uart1_ick,	CK_242X),
	CLK(NULL,	"uart1_fck",	&uart1_fck,	CK_242X),
	CLK(NULL,	"uart2_ick",	&uart2_ick,	CK_242X),
	CLK(NULL,	"uart2_fck",	&uart2_fck,	CK_242X),
	CLK(NULL,	"uart3_ick",	&uart3_ick,	CK_242X),
	CLK(NULL,	"uart3_fck",	&uart3_fck,	CK_242X),
	CLK(NULL,	"gpios_ick",	&gpios_ick,	CK_242X),
	CLK(NULL,	"gpios_fck",	&gpios_fck,	CK_242X),
	CLK("omap_wdt",	"ick",		&mpu_wdt_ick,	CK_242X),
	CLK("omap_wdt",	"fck",		&mpu_wdt_fck,	CK_242X),
	CLK(NULL,	"sync_32k_ick",	&sync_32k_ick,	CK_242X),
	CLK(NULL,	"wdt1_ick",	&wdt1_ick,	CK_242X),
	CLK(NULL,	"omapctrl_ick",	&omapctrl_ick,	CK_242X),
	CLK("omap24xxcam", "fck",	&cam_fck,	CK_242X),
	CLK("omap24xxcam", "ick",	&cam_ick,	CK_242X),
	CLK(NULL,	"mailboxes_ick", &mailboxes_ick,	CK_242X),
	CLK(NULL,	"wdt4_ick",	&wdt4_ick,	CK_242X),
	CLK(NULL,	"wdt4_fck",	&wdt4_fck,	CK_242X),
1872 1873
	CLK(NULL,	"wdt3_ick",	&wdt3_ick,	CK_242X),
	CLK(NULL,	"wdt3_fck",	&wdt3_fck,	CK_242X),
1874 1875
	CLK(NULL,	"mspro_ick",	&mspro_ick,	CK_242X),
	CLK(NULL,	"mspro_fck",	&mspro_fck,	CK_242X),
1876 1877
	CLK("mmci-omap.0", "ick",	&mmc_ick,	CK_242X),
	CLK("mmci-omap.0", "fck",	&mmc_fck,	CK_242X),
1878 1879
	CLK(NULL,	"fac_ick",	&fac_ick,	CK_242X),
	CLK(NULL,	"fac_fck",	&fac_fck,	CK_242X),
1880 1881
	CLK(NULL,	"eac_ick",	&eac_ick,	CK_242X),
	CLK(NULL,	"eac_fck",	&eac_fck,	CK_242X),
1882 1883
	CLK("omap_hdq.0", "ick",	&hdq_ick,	CK_242X),
	CLK("omap_hdq.1", "fck",	&hdq_fck,	CK_242X),
1884 1885 1886 1887
	CLK("omap_i2c.1", "ick",	&i2c1_ick,	CK_242X),
	CLK("omap_i2c.1", "fck",	&i2c1_fck,	CK_242X),
	CLK("omap_i2c.2", "ick",	&i2c2_ick,	CK_242X),
	CLK("omap_i2c.2", "fck",	&i2c2_fck,	CK_242X),
1888 1889 1890
	CLK(NULL,	"gpmc_fck",	&gpmc_fck,	CK_242X),
	CLK(NULL,	"sdma_fck",	&sdma_fck,	CK_242X),
	CLK(NULL,	"sdma_ick",	&sdma_ick,	CK_242X),
P
Paul Walmsley 已提交
1891
	CLK(NULL,	"sdrc_ick",	&sdrc_ick,	CK_242X),
1892 1893
	CLK(NULL,	"vlynq_ick",	&vlynq_ick,	CK_242X),
	CLK(NULL,	"vlynq_fck",	&vlynq_fck,	CK_242X),
1894
	CLK(NULL,	"des_ick",	&des_ick,	CK_242X),
1895
	CLK("omap-sham",	"ick",	&sha_ick,	CK_242X),
1896
	CLK("omap_rng",	"ick",		&rng_ick,	CK_242X),
1897
	CLK("omap-aes",	"ick",	&aes_ick,	CK_242X),
1898 1899
	CLK(NULL,	"pka_ick",	&pka_ick,	CK_242X),
	CLK(NULL,	"usb_fck",	&usb_fck,	CK_242X),
1900
	CLK("musb-hdrc",	"fck",	&osc_ck,	CK_242X),
1901 1902 1903 1904 1905 1906
};

/*
 * init code
 */

1907
int __init omap2420_clk_init(void)
1908 1909 1910 1911
{
	const struct prcm_config *prcm;
	struct omap_clk *c;
	u32 clkrate;
1912 1913 1914 1915 1916

	prcm_clksrc_ctrl = OMAP2420_PRCM_CLKSRC_CTRL;
	cm_idlest_pll = OMAP_CM_REGADDR(PLL_MOD, CM_IDLEST);
	cpu_mask = RATE_IN_242X;
	rate_table = omap2420_rate_table;
1917 1918 1919

	clk_init(&omap2_clk_functions);

1920 1921
	for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
	     c++)
1922 1923 1924 1925
		clk_preinit(c->lk.clk);

	osc_ck.rate = omap2_osc_clk_recalc(&osc_ck);
	propagate_rate(&osc_ck);
1926
	sys_ck.rate = omap2xxx_sys_clk_recalc(&sys_ck);
1927 1928
	propagate_rate(&sys_ck);

1929 1930 1931 1932 1933 1934
	for (c = omap2420_clks; c < omap2420_clks + ARRAY_SIZE(omap2420_clks);
	     c++) {
		clkdev_add(&c->lk);
		clk_register(c->lk.clk);
		omap2_init_clk_clkdm(c->lk.clk);
	}
1935

1936 1937 1938
	/* Disable autoidle on all clocks; let the PM code enable it later */
	omap_clk_disable_autoidle_all();

1939 1940 1941 1942 1943 1944 1945 1946 1947 1948 1949 1950 1951 1952
	/* Check the MPU rate set by bootloader */
	clkrate = omap2xxx_clk_get_core_rate(&dpll_ck);
	for (prcm = rate_table; prcm->mpu_speed; prcm++) {
		if (!(prcm->flags & cpu_mask))
			continue;
		if (prcm->xtal_speed != sys_ck.rate)
			continue;
		if (prcm->dpll_speed <= clkrate)
			break;
	}
	curr_prcm_set = prcm;

	recalculate_root_clocks();

1953 1954 1955
	pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n",
		(sys_ck.rate / 1000000), (sys_ck.rate / 100000) % 10,
		(dpll_ck.rate / 1000000), (mpu_ck.rate / 1000000)) ;
1956 1957 1958 1959 1960 1961 1962 1963 1964 1965 1966 1967 1968 1969

	/*
	 * Only enable those clocks we will need, let the drivers
	 * enable other clocks as necessary
	 */
	clk_enable_init_clocks();

	/* Avoid sleeping sleeping during omap2_clk_prepare_for_reboot() */
	vclk = clk_get(NULL, "virt_prcm_set");
	sclk = clk_get(NULL, "sys_ck");
	dclk = clk_get(NULL, "dpll_ck");

	return 0;
}
1970