未验证 提交 97cc8a8f 编写于 作者: mysterywolf's avatar mysterywolf 提交者: GitHub

Merge pull request #14 from RT-Thread/master

pr
......@@ -130,6 +130,7 @@ jobs:
- {RTT_BSP: "at32/at32f403a-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "at32/at32f407-start", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "smartfusion2", RTT_TOOL_CHAIN: "sourcery-arm"}
- {RTT_BSP: "raspberry-pico", RTT_TOOL_CHAIN: "sourcery-arm"}
steps:
- uses: actions/checkout@v2
- name: Set up Python
......
......@@ -24,6 +24,7 @@ documentation/html
*.d
tools/kconfig-frontends/kconfig-mconf
packages
dist
cconfig.h
GPUCache
......
......@@ -114,8 +114,16 @@ CONFIG_DFS_FILESYSTEM_TYPES_MAX=2
CONFIG_DFS_FD_MAX=16
# CONFIG_RT_USING_DFS_MNTTABLE is not set
# CONFIG_RT_USING_DFS_ELMFAT is not set
# CONFIG_RT_DFS_ELM_USE_LFN_0 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_1 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_2 is not set
# CONFIG_RT_DFS_ELM_USE_LFN_3 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_0 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_1 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_2 is not set
# CONFIG_RT_DFS_ELM_LFN_UNICODE_3 is not set
# CONFIG_RT_USING_DFS_DEVFS is not set
CONFIG_RT_USING_DFS_ROMFS=y
# CONFIG_RT_USING_DFS_ROMFS is not set
# CONFIG_RT_USING_DFS_RAMFS is not set
# CONFIG_RT_USING_DFS_UFFS is not set
# CONFIG_RT_USING_DFS_JFFS2 is not set
......@@ -145,10 +153,7 @@ CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
CONFIG_RT_USING_AUDIO=y
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_SIZE=1024
CONFIG_RT_AUDIO_REPLAY_MP_BLOCK_COUNT=2
CONFIG_RT_AUDIO_RECORD_PIPE_SIZE=512
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
......@@ -328,6 +333,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ULOG_FILE is not set
# CONFIG_PKG_USING_LOGMGR is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
......@@ -343,6 +350,8 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_CPU_USAGE is not set
# CONFIG_PKG_USING_GBK2UTF8 is not set
# CONFIG_PKG_USING_VCONSOLE is not set
# CONFIG_PKG_USING_KDB is not set
# CONFIG_PKG_USING_WAMR is not set
#
# system packages
......@@ -381,6 +390,11 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
# CONFIG_PKG_USING_OPENAMP is not set
# CONFIG_PKG_USING_RT_PRINTF is not set
# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
# CONFIG_PKG_USING_QFPLIB_M3 is not set
#
# peripheral libraries and drivers
......@@ -389,6 +403,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_AS7341 is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
......@@ -441,6 +456,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_NES is not set
# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
# CONFIG_PKG_USING_VDEVICE is not set
# CONFIG_PKG_USING_SGM706 is not set
#
# miscellaneous packages
......@@ -490,6 +506,7 @@ CONFIG_RT_USING_LIBC=y
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
# CONFIG_PKG_USING_STATE_MACHINE is not set
#
# Hardware Drivers Config
......@@ -499,13 +516,17 @@ CONFIG_RT_USING_LIBC=y
# Onboard Peripheral Drivers
#
CONFIG_BSP_USING_USB_TO_USART=y
CONFIG_BSP_USING_AUDIO=y
CONFIG_BSP_USING_AUDIO_PLAY=y
# CONFIG_BSP_USING_AUDIO is not set
# CONFIG_BSP_USING_SDCARD is not set
#
# On-chip Peripheral Drivers
#
CONFIG_BSP_USING_UART0=y
# CONFIG_BSP_USING_SDIO is not set
# CONFIG_BSP_USING_I2C1 is not set
# CONFIG_BSP_USING_WDT is not set
# CONFIG_BSP_USING_TIM is not set
#
# Board extended module Drivers
......
......@@ -12,7 +12,7 @@
## 开发板介绍
ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核的开发板,最高主频为 120Mhz,该开发板芯片为 AB5301A
ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核的开发板,最高主频为 120Mhz,该开发板芯片为 AB32VG1
开发板外观如下图所示:
......@@ -20,7 +20,7 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
该开发板常用 **板载资源** 如下:
- MCU:AB5301A,主频 120MHz,可超频至 192MHz,4Mbit FLASH ,192KB RAM。
- MCU:AB32VG1,主频 120MHz,可超频至 192MHz,8Mbit FLASH ,192KB RAM。
- 常用外设
- LED: RGB灯
- 按键: 3 个, USER(s2,s3) and RESET(s1)
......@@ -33,19 +33,20 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
| **板载外设** | **支持情况** | **备注** |
| :----------- | :----------: | :---------- |
| USB 转串口 | 支持 | |
| SD卡 | 即将支持 | |
| SD卡 | 支持 | |
| IRDA | 即将支持 | |
| 音频接口 | 即将支持 | |
| 音频接口 | 支持 | |
| **片上外设** | **支持情况** | **备注** |
| GPIO | 支持 | PA PB PE PF |
| UART | 支持 | UART0/1/2 |
| SDIO | 即将支持 | |
| SDIO | 支持 | |
| ADC | 即将支持 | |
| SPI | 即将支持 | |
| I2C | 即将支持 | 软件 I2C |
| SPI | 即将支持 | 软件 SPI |
| I2C | 支持 | 软件 I2C |
| RTC | 即将支持 | |
| WDT | 即将支持 | |
| WDT | 支持 | |
| FLASH | 即将支持 | |
| TIMER | 支持 | |
| PWM | 即将支持 | |
| USB Device | 暂不支持 | |
| USB Host | 暂不支持 | |
......@@ -73,11 +74,11 @@ ab32vg1-prougen 是 中科蓝讯(Bluetrum) 推出的一款基于 RISC-V 内核
#### 编译下载
运行 `scons` 编译得到 `.dcf` 固件,通过 `downloader` 进行下载
通过 `RT-Thread Studio` 或者 `scons` 编译得到 `.dcf` 固件,通过 `Downloader` 进行下载
#### 运行结果
下载程序成功之后,系统会自动运行,观察开发板上 LED 的运行效果,红色 LED 常亮、绿色 LED 会周期性闪烁。
下载程序成功之后,系统会自动运行,观察开发板上 LED 的运行效果,红色 LED 会周期性闪烁。
连接开发板对应串口到 PC , 在终端工具里打开相应的串口(115200-8-1-N),复位设备后,可以看到 RT-Thread 的输出信息:
......
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
......
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021/01/21 greedyhao The first version
*/
#include <rtthread.h>
#ifdef RT_USING_DFS
#ifdef BSP_USING_SDIO
#include <dfs_elm.h>
#include <dfs_fs.h>
#include "dfs_romfs.h"
#include <dfs_posix.h>
#include "drv_gpio.h"
// #define DRV_DEBUG
#define DBG_TAG "app.card"
#include <rtdbg.h>
void sd_mount(void *parameter)
{
while (1)
{
rt_thread_mdelay(500);
if(rt_device_find("sd0") != RT_NULL)
{
if (dfs_mount("sd0", "/", "elm", 0, 0) == RT_EOK)
{
LOG_I("sd card mount to '/'");
break;
}
else
{
LOG_W("sd card mount to '/' failed!");
}
}
}
}
int mnt_init(void)
int ab32_sdcard_mount(void)
{
if (dfs_mount(RT_NULL, "/", "rom", 0, &(romfs_root)) == 0)
rt_thread_t tid;
tid = rt_thread_create("sd_mount", sd_mount, RT_NULL,
1024, RT_THREAD_PRIORITY_MAX - 2, 20);
if (tid != RT_NULL)
{
rt_kprintf("ROM file system initializated!\n");
rt_thread_startup(tid);
}
else
{
rt_kprintf("ROM file system initializate failed!\n");
LOG_E("create sd_mount thread err!");
}
return 0;
return RT_EOK;
}
INIT_ENV_EXPORT(mnt_init);
INIT_APP_EXPORT(ab32_sdcard_mount);
#endif
/* Generated by mkromfs. Edit with caution. */
#include <rtthread.h>
#ifdef RT_USING_DFS
#include <dfs_romfs.h>
static const struct romfs_dirent _romfs_root[] = {
{ROMFS_DIRENT_FILE, "ab32vg1", RT_NULL, 0}
};
const struct romfs_dirent romfs_root = {
ROMFS_DIRENT_DIR, "/", (rt_uint8_t *)_romfs_root, sizeof(_romfs_root)/sizeof(_romfs_root[0])
};
#endif
......@@ -19,6 +19,18 @@ menu "Onboard Peripheral Drivers"
default y
endif
config BSP_USING_SDCARD
bool "Enable SDCARD"
select BSP_USING_SDIO
default n
if BSP_USING_SDCARD
config SDIO_MAX_FREQ
int "sdio max freq"
range 0 24000000
default 24000000
endif
endmenu
menu "On-chip Peripheral Drivers"
......@@ -28,6 +40,62 @@ menu "On-chip Peripheral Drivers"
select RT_USING_SERIAL
default y
config BSP_USING_SDIO
bool "Enable SDIO"
select RT_USING_SDIO
select RT_USING_DFS
select RT_USING_DFS_ELMFAT
default n
menuconfig BSP_USING_I2C1
bool "Enable I2C1 BUS (software simulation)"
default n
select RT_USING_I2C
select RT_USING_I2C_BITOPS
select RT_USING_PIN
if BSP_USING_I2C1
comment "Notice: PE3 --> 16; PE2 --> 15"
config BSP_I2C1_SCL_PIN
int "I2C1 scl pin number"
range 1 27
default 16
config BSP_I2C1_SDA_PIN
int "I2C1 sda pin number"
range 1 27
default 15
endif
config BSP_USING_WDT
bool "Enable Watchdog Timer"
select RT_USING_WDT
default n
menuconfig BSP_USING_TIM
bool "Enable timer"
default n
select RT_USING_HWTIMER
if BSP_USING_TIM
config BSP_USING_TIM1
bool "Enable TIM1"
default n
config BSP_USING_TIM2
bool "Enable TIM2"
default n
config BSP_USING_TIM3
bool "Enable TIM3"
default n
config BSP_USING_TIM4
bool "Enable TIM4"
default n
config BSP_USING_TIM5
bool "Enable TIM5"
default n
endif
endmenu
menu "Board extended module Drivers"
......
......@@ -34,12 +34,6 @@ SECTIONS
} > init
.ram1 __ram1_vma : {
*components*drivers**.o(.text* .rodata*)
*device.o(.text*)
. = ALIGN(32);
} > ram1 AT > flash
.rti : {
. = ALIGN(4);
/* section information for initial */
__rt_init_start = .;
......@@ -56,19 +50,38 @@ SECTIONS
KEEP(*(VSymTab))
__vsymtab_end = .;
. = ALIGN(32);
. = ALIGN(4);
PROVIDE(__ctors_start__ = .);
KEEP (*(SORT(.init_array.*)))
KEEP (*(.init_array))
PROVIDE(__ctors_end__ = .);
. = ALIGN(4);
*components*drivers**.o (.text*)
*components.o (.text*)
*idle.o (.text*)
*object.o (.text*)
*scheduler.o (.text*)
} > ram1 AT > flash
.comm : {
.comm __comm_vma : {
. = ALIGN(4);
KEEP(*(.vector))
EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *romfs.o *lib_a**.o) *(.text*)
EXCLUDE_FILE(*components*finsh**.o *components*libc**.o *dfs*filesystems**.o
*romfs.o *lib_a**.o *divdi3.o *moddi3.o *divdf3.o *muldf3.o *eqtf2.o *getf2.o
*letf2.o *multf3.o *subtf3.o *fixtfsi.o *floatsitf.o *extenddftf2.o
*trunctfdf2.o *_clzsi2.o *cp-demangle.o *unwind*.o) *(.text)
*finsh*shell.o (.text*)
EXCLUDE_FILE (*components*libc**.o *romfs.o *lib_a**.o) *(.rodata*)
*(.srodata*)
*(.text.unlikely)
*(.text.startup)
EXCLUDE_FILE (*components*libc**.o *dfs*filesystems**.o *romfs.o *lib_a**.o
*cp-demangle.o *divdf3.o *muldf3.o *multf3.o *unwind*.o *_clz.o) *(.rodata)
*(.rodata.name)
EXCLUDE_FILE(*lib_a**.o *cp-demangle.o *cp-demangle.o) *(.rodata.str1.4)
EXCLUDE_FILE(*lib_a**.o *unwind*.o) *(.srodata)
*(.rela*)
*(.data*)
*(.sdata*)
. = ALIGN(512);
*(.sdata*)
} > comm AT > flash
.bss (NOLOAD):
......@@ -98,6 +111,7 @@ SECTIONS
.flash : {
*(.text*)
*(.rodata*)
*(.srodata*)
. = ALIGN(512);
} > flash
}
......@@ -107,4 +121,4 @@ __bank_size = SIZEOF(.flash);
__comm_lma = LOADADDR(.comm);
__comm_size = SIZEOF(.comm);
__ram1_lma = LOADADDR(.ram1);
__ram1_size = SIZEOF(.ram1) + SIZEOF(.rti);
__ram1_size = SIZEOF(.ram1);
rtthread.siz:
riscv64-unknown-elf-size --format=berkeley "rtthread.elf"
all2: all
sh ../pre_build.sh
riscv32-elf-xmaker -b rtthread.xm
riscv32-elf-xmaker -b download.xm
clean2:
-$(RM) $(CC_DEPS)$(C++_DEPS)$(C_UPPER_DEPS)$(CXX_DEPS)$(SECONDARY_FLASH)$(SECONDARY_SIZE)$(ASM_DEPS)$(S_UPPER_DEPS)$(C_DEPS)$(CPP_DEPS)
-$(RM) $(OBJS) *.elf
-@echo ' '
*.elf: $(wildcard D:/Softwares/RT-ThreadStudio/workspace/ab32vg1/link.lds)
......@@ -77,7 +77,6 @@
#define DFS_FILESYSTEMS_MAX 2
#define DFS_FILESYSTEM_TYPES_MAX 2
#define DFS_FD_MAX 16
#define RT_USING_DFS_ROMFS
/* Device Drivers */
......@@ -86,10 +85,6 @@
#define RT_USING_SERIAL
#define RT_SERIAL_RB_BUFSZ 64
#define RT_USING_PIN
#define RT_USING_AUDIO
#define RT_AUDIO_REPLAY_MP_BLOCK_SIZE 1024
#define RT_AUDIO_REPLAY_MP_BLOCK_COUNT 2
#define RT_AUDIO_RECORD_PIPE_SIZE 512
/* Using USB */
......@@ -169,8 +164,6 @@
/* Onboard Peripheral Drivers */
#define BSP_USING_USB_TO_USART
#define BSP_USING_AUDIO
#define BSP_USING_AUDIO_PLAY
/* On-chip Peripheral Drivers */
......
......@@ -4,7 +4,8 @@ from building import *
cwd = GetCurrentDir()
src = []
CPPPATH = [cwd]
path = [cwd]
path += [cwd + '/config']
if GetDepend('RT_USING_PIN'):
src += ['drv_gpio.c']
......@@ -12,7 +13,19 @@ if GetDepend('RT_USING_PIN'):
if GetDepend('RT_USING_SERIAL'):
src += ['drv_usart.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
if GetDepend('RT_USING_SDIO'):
src += ['drv_sdio.c']
if GetDepend('RT_USING_I2C'):
src += ['drv_soft_i2c.c']
if GetDepend('RT_USING_WDT'):
src += ['drv_wdt.c']
if GetDepend('RT_USING_HWTIMER'):
src += ['drv_hwtimer.c']
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = path)
objs = [group]
......
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021/01/18 greedyhao The first version
*/
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-22 greedyhao first version
*/
#ifndef __TIM_CONFIG_H__
#define __TIM_CONFIG_H__
#include <rtthread.h>
#ifdef __cplusplus
extern "C" {
#endif
#ifndef TIM_DEV_INFO_CONFIG
#define TIM_DEV_INFO_CONFIG \
{ \
.maxfreq = 1000000, \
.minfreq = 3000, \
.maxcnt = 0xFFFFFFFF, \
.cntmode = HWTIMER_CNTMODE_UP, \
}
#endif /* TIM_DEV_INFO_CONFIG */
#ifdef BSP_USING_TIM1
#ifndef TIM1_CONFIG
#define TIM1_CONFIG \
{ \
.tim_handle = TIM1_BASE, \
.tim_irqn = IRQ_TMR1_VECTOR, \
.name = "timer1", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM1 */
#ifdef BSP_USING_TIM2
#ifndef TIM2_CONFIG
#define TIM2_CONFIG \
{ \
.tim_handle = TIM2_BASE, \
.tim_irqn = IRQ_TMR2_4_5_VECTOR, \
.name = "timer2", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM2 */
#ifdef BSP_USING_TIM3
#ifndef TIM3_CONFIG
#define TIM3_CONFIG \
{ \
.tim_handle = TIM3_BASE, \
.tim_irqn = IRQ_IRRX_VECTOR, \
.name = "timer3", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM3 */
#ifdef BSP_USING_TIM4
#ifndef TIM4_CONFIG
#define TIM4_CONFIG \
{ \
.tim_handle = TIM4_BASE, \
.tim_irqn = IRQ_TMR2_4_5_VECTOR, \
.name = "timer4", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM4 */
#ifdef BSP_USING_TIM5
#ifndef TIM5_CONFIG
#define TIM5_CONFIG \
{ \
.tim_handle = TIM5_BASE, \
.tim_irqn = IRQ_TMR2_4_5_VECTOR, \
.name = "timer5", \
}
#endif /* TIM1_CONFIG */
#endif /* BSP_USING_TIM5 */
#ifdef __cplusplus
}
#endif
#endif /* __TIM_CONFIG_H__ */
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-22 greedyhao first version
*/
#include "board.h"
#ifdef BSP_USING_TIM
#include "tim_config.h"
//#define DRV_DEBUG
#define LOG_TAG "drv.hwtimer"
#include <drv_log.h>
#ifdef RT_USING_HWTIMER
enum
{
#ifdef BSP_USING_TIM1
TIM1_INDEX,
#endif
#ifdef BSP_USING_TIM2
TIM2_INDEX,
#endif
#ifdef BSP_USING_TIM3
TIM3_INDEX,
#endif
#ifdef BSP_USING_TIM4
TIM4_INDEX,
#endif
#ifdef BSP_USING_TIM5
TIM5_INDEX,
#endif
};
struct ab32_hwtimer
{
rt_hwtimer_t time_device;
hal_sfr_t tim_handle;
char *name;
irq_type tim_irqn;
};
static struct ab32_hwtimer ab32_hwtimer_obj[] =
{
#ifdef BSP_USING_TIM1
TIM1_CONFIG,
#endif
#ifdef BSP_USING_TIM2
TIM2_CONFIG,
#endif
#ifdef BSP_USING_TIM3
TIM3_CONFIG,
#endif
#ifdef BSP_USING_TIM4
TIM4_CONFIG,
#endif
#ifdef BSP_USING_TIM5
TIM5_CONFIG,
#endif
};
static void timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state)
{
uint32_t prescaler_value = 0;
hal_sfr_t tim = RT_NULL;
struct ab32_hwtimer *tim_device = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim = (hal_sfr_t)timer->parent.user_data;
if (state)
{
tim_device = (struct ab32_hwtimer *)timer;
if (timer->info->cntmode != HWTIMER_CNTMODE_UP)
{
LOG_E("Only support HWTIMER_CNTMODE_UP!");
}
/* set tim int */
tim[TMRxCON] = BIT(7);
LOG_D("%s init success", tim_device->name);
} else {
/* stop timer */
tim[TMRxCON] = 0;
}
}
static rt_err_t timer_start(rt_hwtimer_t *timer, rt_uint32_t t, rt_hwtimer_mode_t opmode)
{
rt_err_t result = RT_EOK;
hal_sfr_t tim = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim = (hal_sfr_t)timer->parent.user_data;
/* set tim cnt */
tim[TMRxCNT] = 0;
tim[TMRxPR] = t * (get_sysclk_nhz() / timer->freq) - 1;
if (opmode != HWTIMER_MODE_PERIOD)
{
LOG_E("Opmode only support HWTIMER_MODE_PERIOD!");
return -RT_EINVAL;
}
/* start timer */
tim[TMRxCON] |= BIT(0);
return result;
}
static void timer_stop(rt_hwtimer_t *timer)
{
hal_sfr_t tim = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim = (hal_sfr_t)timer->parent.user_data;
/* stop timer */
tim[TMRxCON] &= ~BIT(0);
/* set tim cnt */
tim[TMRxCNT] = 0;
}
static rt_err_t timer_ctrl(rt_hwtimer_t *timer, rt_uint32_t cmd, void *arg)
{
hal_sfr_t tim = RT_NULL;
rt_err_t result = RT_EOK;
RT_ASSERT(timer != RT_NULL);
RT_ASSERT(arg != RT_NULL);
tim = (hal_sfr_t)timer->parent.user_data;
switch (cmd)
{
case HWTIMER_CTRL_FREQ_SET:
{
}
break;
default:
{
result = -RT_ENOSYS;
}
break;
}
return result;
}
static rt_uint32_t timer_counter_get(rt_hwtimer_t *timer)
{
hal_sfr_t tim = RT_NULL;
RT_ASSERT(timer != RT_NULL);
tim = (hal_sfr_t)timer->parent.user_data;
return tim[TMRxCNT] / (get_sysclk_nhz() / timer->freq);
}
static const struct rt_hwtimer_info _info = TIM_DEV_INFO_CONFIG;
static const struct rt_hwtimer_ops _ops =
{
.init = timer_init,
.start = timer_start,
.stop = timer_stop,
.count_get = timer_counter_get,
.control = timer_ctrl,
};
#if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5)
void timer2_4_5_isr(int vector, void *param)
{
rt_interrupt_enter();
#ifdef BSP_USING_TIM2
if (ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM2_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM2_INDEX].time_device);
}
#endif
#ifdef BSP_USING_TIM4
if (ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM4_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM4_INDEX].time_device);
}
#endif
#ifdef BSP_USING_TIM5
if (ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCON] != 0) {
ab32_hwtimer_obj[TIM5_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM5_INDEX].time_device);
}
#endif
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIM3
void timer3_isr(int vector, void *param)
{
rt_interrupt_enter();
ab32_hwtimer_obj[TIM3_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM3_INDEX].time_device);
rt_interrupt_leave();
}
#endif
#ifdef BSP_USING_TIM1
void timer1_isr(int vector, void *param)
{
rt_interrupt_enter();
ab32_hwtimer_obj[TIM1_INDEX].tim_handle[TMRxCPND] = BIT(9);
rt_device_hwtimer_isr(&ab32_hwtimer_obj[TIM1_INDEX].time_device);
rt_interrupt_leave();
}
#endif
static int ab32_hwtimer_init(void)
{
int i = 0;
int result = RT_EOK;
for (i = 0; i < sizeof(ab32_hwtimer_obj) / sizeof(ab32_hwtimer_obj[0]); i++)
{
ab32_hwtimer_obj[i].time_device.info = &_info;
ab32_hwtimer_obj[i].time_device.ops = &_ops;
if (rt_device_hwtimer_register(&ab32_hwtimer_obj[i].time_device, ab32_hwtimer_obj[i].name, (void *)ab32_hwtimer_obj[i].tim_handle) == RT_EOK)
{
LOG_D("%s register success", ab32_hwtimer_obj[i].name);
}
else
{
LOG_E("%s register failed", ab32_hwtimer_obj[i].name);
result = -RT_ERROR;
}
}
#ifdef BSP_USING_TIM1
rt_hw_interrupt_install(IRQ_TMR1_VECTOR, timer1_isr, RT_NULL, "t1_isr");
#endif
#if defined(BSP_USING_TIM2) || defined(BSP_USING_TIM4) || defined(BSP_USING_TIM5)
rt_hw_interrupt_install(IRQ_TMR2_4_5_VECTOR, timer2_4_5_isr, RT_NULL, "t245_isr");
#endif
#ifdef BSP_USING_TIM3
rt_hw_interrupt_install(IRQ_IRRX_VECTOR, timer3_isr, RT_NULL, "t3_isr");
#endif
return result;
}
INIT_BOARD_EXPORT(ab32_hwtimer_init);
#endif /* RT_USING_HWTIMER */
#endif /* BSP_USING_TIM */
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-30 greedyhao first version
*/
#include "drv_sdio.h"
#include "interrupt.h"
#include <rthw.h>
#ifdef BSP_USING_SDIO
// #define DRV_DEBUG
#define LOG_TAG "drv.sdio"
#include <drv_log.h>
#define SDIO_USING_1_BIT
static struct ab32_sdio_config sdio_config[] =
{
{.instance = SDMMC0_BASE,
},
};
static struct rt_mmcsd_host *host = RT_NULL;
#define RTHW_SDIO_LOCK(_sdio) rt_mutex_take(&(_sdio)->mutex, RT_WAITING_FOREVER)
#define RTHW_SDIO_UNLOCK(_sdio) rt_mutex_release(&(_sdio)->mutex);
struct sdio_pkg
{
struct rt_mmcsd_cmd *cmd;
void *buff;
rt_uint32_t flag;
rt_uint32_t xfer_blks;
};
struct rthw_sdio
{
struct rt_mmcsd_host *host;
struct ab32_sdio_des sdio_des;
struct rt_event event;
struct rt_mutex mutex;
struct sdio_pkg *pkg;
};
ALIGN(SDIO_ALIGN_LEN)
static rt_uint8_t cache_buf[SDIO_BUFF_SIZE];
static uint8_t sd_baud = 119;
uint8_t sysclk_update_baud(uint8_t baud);
static rt_uint32_t ab32_sdio_clk_get(hal_sfr_t hw_sdio)
{
return (get_sysclk_nhz() / (sd_baud+1));
}
/**
* @brief This function get order from sdio.
* @param data
* @retval sdio order
*/
static int get_order(rt_uint32_t data)
{
int order = 0;
switch (data)
{
case 1:
order = 0;
break;
case 2:
order = 1;
break;
case 4:
order = 2;
break;
case 8:
order = 3;
break;
case 16:
order = 4;
break;
case 32:
order = 5;
break;
case 64:
order = 6;
break;
case 128:
order = 7;
break;
case 256:
order = 8;
break;
case 512:
order = 9;
break;
case 1024:
order = 10;
break;
case 2048:
order = 11;
break;
case 4096:
order = 12;
break;
case 8192:
order = 13;
break;
case 16384:
order = 14;
break;
default :
order = 0;
break;
}
return order;
}
/**
* @brief This function wait sdio completed.
* @param sdio rthw_sdio
* @retval None
*/
static void rthw_sdio_wait_completed(struct rthw_sdio *sdio)
{
rt_uint32_t status = 0;
struct rt_mmcsd_cmd *cmd = sdio->pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
rt_err_t tx_finish = -RT_ERROR;
if (rt_event_recv(&sdio->event, 0xFFFFFFFF & ~HW_SDIO_CON_DFLAG, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait completed timeout");
cmd->err = -RT_ETIMEOUT;
return;
}
if (sdio->pkg == RT_NULL)
{
return;
}
cmd->resp[0] = hw_sdio[SDxARG3];
cmd->resp[1] = hw_sdio[SDxARG2];
cmd->resp[2] = hw_sdio[SDxARG1];
cmd->resp[3] = hw_sdio[SDxARG0];
if (!(status & HW_SDIO_CON_NRPS)) {
cmd->err = RT_EOK;
LOG_D("sta:0x%08X [%08X %08X %08X %08X]", status, cmd->resp[0], cmd->resp[1], cmd->resp[2], cmd->resp[3]);
} else {
cmd->err = -RT_ERROR;
}
}
/**
* @brief This function transfer data by dma.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_transfer_by_dma(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_data *data;
int size;
void *buff;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
if ((RT_NULL == pkg) || (RT_NULL == sdio))
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
data = pkg->cmd->data;
if (RT_NULL == data)
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
buff = pkg->buff;
if (RT_NULL == buff)
{
LOG_E("rthw_sdio_transfer_by_dma invalid args");
return;
}
hw_sdio = sdio->sdio_des.hw_sdio;
size = data->blks * data->blksize;
if (data->flags & DATA_DIR_WRITE)
{
LOG_D("DATA_DIR_WRITE %d", pkg->xfer_blks);
sdio->sdio_des.txconfig((rt_uint32_t *)((rt_uint8_t *)buff + (pkg->xfer_blks * data->blksize)), 512);
}
else if (data->flags & DATA_DIR_READ)
{
LOG_D("DATA_DIR_WRITE %d", pkg->xfer_blks);
sdio->sdio_des.rxconfig((rt_uint32_t *)((rt_uint8_t *)buff + (pkg->xfer_blks * data->blksize)), data->blksize);
}
}
/**
* @brief This function send command.
* @param sdio rthw_sdio
* @param pkg sdio package
* @retval None
*/
static void rthw_sdio_send_command(struct rthw_sdio *sdio, struct sdio_pkg *pkg)
{
struct rt_mmcsd_cmd *cmd = pkg->cmd;
struct rt_mmcsd_data *data = cmd->data;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t reg_cmd = 0;
rt_uint32_t data_flag = 0;
/* save pkg */
sdio->pkg = pkg;
#define CK8E BIT(11) //在命令/数据包后加上8CLK
#define CBUSY BIT(10) //Busy Check
#define CLRSP BIT(9) //17Byte Long Rsp
#define CRSP BIT(8) //Need Rsp
/* config cmd reg */
if (cmd->cmd_code != 18) {
reg_cmd = cmd->cmd_code | 0x40 | CK8E;
} else {
reg_cmd = cmd->cmd_code | 0x40;
}
switch (resp_type(cmd))
{
case RESP_R1B:
reg_cmd |= CBUSY | CRSP;
break;
case RESP_R2:
reg_cmd |= CLRSP | CRSP;
break;
default:
reg_cmd |= CRSP;
break;
}
LOG_D("CMD:%d 0x%04X ARG:0x%08x RES:%s%s%s%s%s%s%s%s%s rw:%c len:%d blksize:%d",
cmd->cmd_code,
reg_cmd,
cmd->arg,
resp_type(cmd) == RESP_NONE ? "NONE" : "",
resp_type(cmd) == RESP_R1 ? "R1" : "",
resp_type(cmd) == RESP_R1B ? "R1B" : "",
resp_type(cmd) == RESP_R2 ? "R2" : "",
resp_type(cmd) == RESP_R3 ? "R3" : "",
resp_type(cmd) == RESP_R4 ? "R4" : "",
resp_type(cmd) == RESP_R5 ? "R5" : "",
resp_type(cmd) == RESP_R6 ? "R6" : "",
resp_type(cmd) == RESP_R7 ? "R7" : "",
data ? (data->flags & DATA_DIR_WRITE ? 'w' : 'r') : '-',
data ? data->blks * data->blksize : 0,
data ? data->blksize : 0
);
/* config data reg */
if (data != RT_NULL)
{
rt_uint32_t dir = 0;
rt_uint32_t size = data->blks * data->blksize;
int order;
order = get_order(data->blksize);
dir = (data->flags & DATA_DIR_READ) ? HW_SDIO_TO_HOST : 0;
data_flag = data->flags;
}
/* transfer config */
if (data_flag & DATA_DIR_READ)
{
rthw_sdio_transfer_by_dma(sdio, pkg);
}
/* send cmd */
hw_sdio[SDxARG3] = cmd->arg;
hw_sdio[SDxCMD] = reg_cmd;
/* wait cmd completed */
rthw_sdio_wait_completed(sdio);
/* transfer config */
if (data != RT_NULL)
{
do {
if ((data_flag & DATA_DIR_WRITE) || ((data_flag & DATA_DIR_READ) && (pkg->xfer_blks != 0))) {
rthw_sdio_transfer_by_dma(sdio, pkg);
}
rt_uint32_t status = 0;
if (rt_event_recv(&sdio->event, 0xFFFFFFFF & ~HW_SDIO_CON_DFLAG, RT_EVENT_FLAG_OR | RT_EVENT_FLAG_CLEAR,
rt_tick_from_millisecond(5000), &status) != RT_EOK)
{
LOG_E("wait completed timeout");
LOG_E("SDxCON=0x%X SDxCMD=0x%X\n", hw_sdio[SDxCON], hw_sdio[SDxCMD]);
cmd->err = -RT_ETIMEOUT;
}
if (data_flag & DATA_DIR_WRITE) {
if (((hw_sdio[SDxCON] & HW_SDIO_CON_CRCS) >> 17) != 2) {
LOG_E("Write CRC error!");
cmd->err = -RT_ERROR;
hw_sdio[SDxCPND] = HW_SDIO_CON_DFLAG;
}
}
} while(++pkg->xfer_blks != data->blks);
}
/* clear pkg */
sdio->pkg = RT_NULL;
}
/**
* @brief This function send sdio request.
* @param host rt_mmcsd_host
* @param req request
* @retval None
*/
static void rthw_sdio_request(struct rt_mmcsd_host *host, struct rt_mmcsd_req *req)
{
struct sdio_pkg pkg;
struct rthw_sdio *sdio = host->private_data;
struct rt_mmcsd_data *data;
RTHW_SDIO_LOCK(sdio);
if (req->cmd != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
data = req->cmd->data;
pkg.cmd = req->cmd;
if (data != RT_NULL)
{
rt_uint32_t size = data->blks * data->blksize;
RT_ASSERT(size <= SDIO_BUFF_SIZE);
pkg.buff = data->buf;
if ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1))
{
pkg.buff = cache_buf;
if (data->flags & DATA_DIR_WRITE)
{
rt_memcpy(cache_buf, data->buf, size);
}
}
}
rthw_sdio_send_command(sdio, &pkg);
if ((data != RT_NULL) && (data->flags & DATA_DIR_READ) && ((rt_uint32_t)data->buf & (SDIO_ALIGN_LEN - 1)))
{
rt_memcpy(data->buf, cache_buf, data->blksize * data->blks);
}
}
if (req->stop != RT_NULL)
{
rt_memset(&pkg, 0, sizeof(pkg));
pkg.cmd = req->stop;
rthw_sdio_send_command(sdio, &pkg);
}
RTHW_SDIO_UNLOCK(sdio);
mmcsd_req_complete(sdio->host);
}
/**
* @brief This function config sdio.
* @param host rt_mmcsd_host
* @param io_cfg rt_mmcsd_io_cfg
* @retval None
*/
static void rthw_sdio_iocfg(struct rt_mmcsd_host *host, struct rt_mmcsd_io_cfg *io_cfg)
{
rt_uint32_t clkcr, div, clk_src;
rt_uint32_t clk = io_cfg->clock;
struct rthw_sdio *sdio = host->private_data;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
clk_src = sdio->sdio_des.clk_get(sdio->sdio_des.hw_sdio);
if (clk_src < 240 * 1000)
{
LOG_E("The clock rate is too low! rata:%d", clk_src);
return;
}
if (clk > host->freq_max) clk = host->freq_max;
if (clk > clk_src)
{
// LOG_W("Setting rate(%d) is greater than clock source rate(%d).", clk, clk_src);
// clk = clk_src;
}
LOG_D("clk:%d width:%s%s%s power:%s%s%s",
clk,
io_cfg->bus_width == MMCSD_BUS_WIDTH_8 ? "8" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_4 ? "4" : "",
io_cfg->bus_width == MMCSD_BUS_WIDTH_1 ? "1" : "",
io_cfg->power_mode == MMCSD_POWER_OFF ? "OFF" : "",
io_cfg->power_mode == MMCSD_POWER_UP ? "UP" : "",
io_cfg->power_mode == MMCSD_POWER_ON ? "ON" : ""
);
RTHW_SDIO_LOCK(sdio);
switch (io_cfg->power_mode)
{
case MMCSD_POWER_OFF:
hw_sdio[SDxCON] &= ~BIT(0);
break;
case MMCSD_POWER_UP:
sd_baud = 199;
hw_sdio[SDxCON] = 0;
rt_thread_mdelay(1);
hw_sdio[SDxCON] |= BIT(0); /* SD control enable */
hw_sdio[SDxBAUD] = sysclk_update_baud(sd_baud);
hw_sdio[SDxCON] |= BIT(3); /* Keep clock output */
hw_sdio[SDxCON] |= BIT(4);
hw_sdio[SDxCON] |= BIT(5); /* Data interrupt enable */
hal_mdelay(40);
break;
case MMCSD_POWER_ON:
if (clk == SDIO_MAX_FREQ) {
hw_sdio[SDxCON] &= ~BIT(3);
sd_baud = 3;
hw_sdio[SDxBAUD] = sysclk_update_baud(sd_baud);
}
break;
default:
LOG_W("unknown power_mode %d", io_cfg->power_mode);
break;
}
RTHW_SDIO_UNLOCK(sdio);
}
/**
* @brief This function update sdio interrupt.
* @param host rt_mmcsd_host
* @param enable
* @retval None
*/
void rthw_sdio_irq_update(struct rt_mmcsd_host *host, rt_int32_t enable)
{
struct rthw_sdio *sdio = host->private_data;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
if (enable)
{
LOG_D("enable sdio irq");
rt_hw_irq_enable(IRQ_SD_VECTOR);
}
else
{
LOG_D("disable sdio irq");
rt_hw_irq_disable(IRQ_SD_VECTOR);
}
}
/**
* @brief This function detect sdcard.
* @param host rt_mmcsd_host
* @retval 0x01
*/
static rt_int32_t rthw_sd_detect(struct rt_mmcsd_host *host)
{
LOG_D("try to detect device");
return 0x01;
}
/**
* @brief This function interrupt process function.
* @param host rt_mmcsd_host
* @retval None
*/
void rthw_sdio_irq_process(struct rt_mmcsd_host *host)
{
int complete = 0;
struct rthw_sdio *sdio = host->private_data;
hal_sfr_t hw_sdio = sdio->sdio_des.hw_sdio;
rt_uint32_t intstatus = hw_sdio[SDxCON];
/* clear flag */
if (intstatus & HW_SDIO_CON_CFLAG) {
complete = 1;
hw_sdio[SDxCPND] = HW_SDIO_CON_CFLAG;
}
if (intstatus & HW_SDIO_CON_DFLAG) {
complete = 1;
hw_sdio[SDxCPND] = HW_SDIO_CON_DFLAG;
}
if (complete)
{
rt_event_send(&sdio->event, intstatus);
}
}
static const struct rt_mmcsd_host_ops ab32_sdio_ops =
{
rthw_sdio_request,
rthw_sdio_iocfg,
rthw_sd_detect,
rthw_sdio_irq_update,
};
/**
* @brief This function create mmcsd host.
* @param sdio_des ab32_sdio_des
* @retval rt_mmcsd_host
*/
struct rt_mmcsd_host *sdio_host_create(struct ab32_sdio_des *sdio_des)
{
struct rt_mmcsd_host *host;
struct rthw_sdio *sdio = RT_NULL;
if ((sdio_des == RT_NULL) || (sdio_des->txconfig == RT_NULL) || (sdio_des->rxconfig == RT_NULL))
{
LOG_E("L:%d F:%s %s %s %s",
(sdio_des == RT_NULL ? "sdio_des is NULL" : ""),
(sdio_des ? (sdio_des->txconfig ? "txconfig is NULL" : "") : ""),
(sdio_des ? (sdio_des->rxconfig ? "rxconfig is NULL" : "") : "")
);
return RT_NULL;
}
sdio = rt_malloc(sizeof(struct rthw_sdio));
if (sdio == RT_NULL)
{
LOG_E("L:%d F:%s malloc rthw_sdio fail");
return RT_NULL;
}
rt_memset(sdio, 0, sizeof(struct rthw_sdio));
host = mmcsd_alloc_host();
if (host == RT_NULL)
{
LOG_E("L:%d F:%s mmcsd alloc host fail");
rt_free(sdio);
return RT_NULL;
}
rt_memcpy(&sdio->sdio_des, sdio_des, sizeof(struct ab32_sdio_des));
sdio->sdio_des.hw_sdio = (sdio_des->hw_sdio == RT_NULL ? SDMMC0_BASE : sdio_des->hw_sdio);
sdio->sdio_des.clk_get = (sdio_des->clk_get == RT_NULL ? ab32_sdio_clk_get : sdio_des->clk_get);
rt_event_init(&sdio->event, "sdio", RT_IPC_FLAG_FIFO);
rt_mutex_init(&sdio->mutex, "sdio", RT_IPC_FLAG_FIFO);
/* set host defautl attributes */
host->ops = &ab32_sdio_ops;
host->freq_min = 240 * 1000;
host->freq_max = SDIO_MAX_FREQ;
host->valid_ocr = 0X00FFFF80;/* The voltage range supported is 1.65v-3.6v */
#ifndef SDIO_USING_1_BIT
host->flags = MMCSD_BUSWIDTH_4 | MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#else
host->flags = MMCSD_MUTBLKWRITE | MMCSD_SUP_SDIO_IRQ;
#endif
host->max_seg_size = SDIO_BUFF_SIZE;
host->max_dma_segs = 1;
host->max_blk_size = 512;
host->max_blk_count = 512;
/* link up host and sdio */
sdio->host = host;
host->private_data = sdio;
rthw_sdio_irq_update(host, 1);
/* ready to change */
mmcsd_change(host);
return host;
}
static rt_err_t _dma_txconfig(rt_uint32_t *src, int Size)
{
hal_sfr_t sdiox = sdio_config->instance;
sdiox[SDxDMAADR] = DMA_ADR(src);
sdiox[SDxDMACNT] = BIT(18) | BIT(17) | BIT(16) | Size;
return RT_EOK;
}
static rt_err_t _dma_rxconfig(rt_uint32_t *dst, int Size)
{
hal_sfr_t sdiox = sdio_config->instance;
sdiox[SDxDMAADR] = DMA_ADR(dst);
sdiox[SDxDMACNT] = (Size);
return RT_EOK;
}
void sdio_isr(int vector, void *param)
{
/* enter interrupt */
rt_interrupt_enter();
/* Process All SDIO Interrupt Sources */
rthw_sdio_irq_process(host);
/* leave interrupt */
rt_interrupt_leave();
}
int rt_hw_sdio_init(void)
{
struct ab32_sdio_des sdio_des = {0};
struct sd_handle hsd = {0};
uint8_t param = 0;
hsd.instance = SDMMC0_BASE;
hal_rcu_periph_clk_enable(RCU_SD0);
hal_sd_mspinit(&hsd);
rt_hw_interrupt_install(IRQ_SD_VECTOR, sdio_isr, &param, "sd_isr");
sdio_des.clk_get = ab32_sdio_clk_get;
sdio_des.hw_sdio = SDMMC0_BASE;
sdio_des.rxconfig = _dma_rxconfig;
sdio_des.txconfig = _dma_txconfig;
host = sdio_host_create(&sdio_des);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_sdio_init);
void ab32_mmcsd_change(void)
{
mmcsd_change(host);
}
#endif // 0
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-30 greedyhao first version
*/
#ifndef DEV_SDIO_H__
#define DEV_SDIO_H__
#include "drv_common.h"
#include "board.h"
#include "drivers/mmcsd_core.h"
#include "drivers/sdio.h"
#define SDIO_BUFF_SIZE 1024
#define SDIO_ALIGN_LEN 32
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (1000000)
#endif
#ifndef SDIO_BASE_ADDRESS
#define SDIO_BASE_ADDRESS (0x40012800U)
#endif
#ifndef SDIO_CLOCK_FREQ
#define SDIO_CLOCK_FREQ (48U * 1000 * 1000)
#endif
#ifndef SDIO_BUFF_SIZE
#define SDIO_BUFF_SIZE (4096)
#endif
#ifndef SDIO_ALIGN_LEN
#define SDIO_ALIGN_LEN (32)
#endif
#ifndef SDIO_MAX_FREQ
#define SDIO_MAX_FREQ (24 * 1000 * 1000)
#endif
#define HW_SDIO_CON_
#define HW_SDIO_CON_CFLAG (0x01u << 12) /*!< 0:send command or received response not finish \
1:send command or received response finish */
#define HW_SDIO_CON_DFLAG (0x01u << 13) /*!< 0:send or received data not finish \
1:send or received data finish */
#define HW_SDIO_CON_CCRCE (0x01u << 14) /*!< 0:command crc no error \
1:command crc error detected */
#define HW_SDIO_CON_NRPS (0x01u << 15) /*!< 0:response received 1:no response received */
#define HW_SDIO_CON_DCRCE (0x01u << 16) /*!< 0:read data crc no error \
1:read data crc error detected */
#define HW_SDIO_CON_CRCS (0x07u << 17) /*!< 101:error transmission \
010:non-erroneous transmission \
111:flash error */
#define HW_SDIO_CON_BUSY (0x01u << 20) /*!< 0:device busy 1:device not busy */
#define HW_SDIO_ERRORS \
(0)
#define HW_SDIO_POWER_OFF (0x00U)
#define HW_SDIO_POWER_UP (0x02U)
#define HW_SDIO_POWER_ON (0x03U)
#define HW_SDIO_FLOW_ENABLE (0x01U << 14)
#define HW_SDIO_BUSWIDE_1B (0x00U << 11)
#define HW_SDIO_BUSWIDE_4B (0x01U << 11)
#define HW_SDIO_BUSWIDE_8B (0x02U << 11)
#define HW_SDIO_BYPASS_ENABLE (0x01U << 10)
#define HW_SDIO_IDLE_ENABLE (0x01U << 9)
#define HW_SDIO_CLK_ENABLE (0x01U << 8)
#define HW_SDIO_SUSPEND_CMD (0x01U << 11)
#define HW_SDIO_CPSM_ENABLE (0x01U << 10)
#define HW_SDIO_WAIT_END (0x01U << 9)
#define HW_SDIO_WAIT_INT (0x01U << 8)
#define HW_SDIO_RESPONSE_NO (0x00U << 6)
#define HW_SDIO_RESPONSE_SHORT (0x01U << 6)
#define HW_SDIO_RESPONSE_LONG (0x03U << 6)
#define HW_SDIO_DATA_LEN_MASK (0x01FFFFFFU)
#define HW_SDIO_IO_ENABLE (0x01U << 11)
#define HW_SDIO_RWMOD_CK (0x01U << 10)
#define HW_SDIO_RWSTOP_ENABLE (0x01U << 9)
#define HW_SDIO_RWSTART_ENABLE (0x01U << 8)
#define HW_SDIO_DBLOCKSIZE_1 (0x00U << 4)
#define HW_SDIO_DBLOCKSIZE_2 (0x01U << 4)
#define HW_SDIO_DBLOCKSIZE_4 (0x02U << 4)
#define HW_SDIO_DBLOCKSIZE_8 (0x03U << 4)
#define HW_SDIO_DBLOCKSIZE_16 (0x04U << 4)
#define HW_SDIO_DBLOCKSIZE_32 (0x05U << 4)
#define HW_SDIO_DBLOCKSIZE_64 (0x06U << 4)
#define HW_SDIO_DBLOCKSIZE_128 (0x07U << 4)
#define HW_SDIO_DBLOCKSIZE_256 (0x08U << 4)
#define HW_SDIO_DBLOCKSIZE_512 (0x09U << 4)
#define HW_SDIO_DBLOCKSIZE_1024 (0x0AU << 4)
#define HW_SDIO_DBLOCKSIZE_2048 (0x0BU << 4)
#define HW_SDIO_DBLOCKSIZE_4096 (0x0CU << 4)
#define HW_SDIO_DBLOCKSIZE_8192 (0x0DU << 4)
#define HW_SDIO_DBLOCKSIZE_16384 (0x0EU << 4)
#define HW_SDIO_DMA_ENABLE (0x01U << 3)
#define HW_SDIO_STREAM_ENABLE (0x01U << 2)
#define HW_SDIO_TO_HOST (0x01U << 1)
#define HW_SDIO_DPSM_ENABLE (0x01U << 0)
#define HW_SDIO_DATATIMEOUT (0xF0000000U)
// struct ab32_sdio
// {};
typedef rt_err_t (*dma_txconfig)(rt_uint32_t *src, int size);
typedef rt_err_t (*dma_rxconfig)(rt_uint32_t *dst, int size);
typedef rt_uint32_t (*sdio_clk_get)(hal_sfr_t hw_sdio);
struct ab32_sdio_des
{
hal_sfr_t hw_sdio;
dma_txconfig txconfig;
dma_rxconfig rxconfig;
sdio_clk_get clk_get;
};
struct ab32_sdio_config
{
hal_sfr_t instance;
// struct dma_config dma_rx, dma_tx;
};
struct ab32_sdio_class
{
const struct ab32_sdio_config *cfg;
struct rt_mmcsd_host host;
};
#endif
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-07 greedyhao first version
*/
#include <board.h>
#include "drv_soft_i2c.h"
#ifdef RT_USING_I2C
// #define DRV_DEBUG
#define LOG_TAG "drv.i2c"
#include <drv_log.h>
#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4)
#error "Please define at least one BSP_USING_I2Cx"
/* this driver can be disabled at menuconfig → RT-Thread Components → Device Drivers */
#endif
static const struct ab32_soft_i2c_config soft_i2c_config[] =
{
#ifdef BSP_USING_I2C1
I2C1_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C2
I2C2_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C3
I2C3_BUS_CONFIG,
#endif
#ifdef BSP_USING_I2C4
I2C4_BUS_CONFIG,
#endif
};
static struct ab32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])] = {0};
/**
* This function initializes the i2c pin.
*
* @param ab32 i2c dirver class.
*/
static void ab32_i2c_gpio_init(struct ab32_i2c *i2c)
{
struct ab32_soft_i2c_config* cfg = (struct ab32_soft_i2c_config*)i2c->ops.data;
cfg->scl_mode = PIN_MODE_OUTPUT_OD;
cfg->sda_mode = PIN_MODE_OUTPUT_OD;
rt_pin_mode(cfg->scl, cfg->scl_mode);
rt_pin_mode(cfg->sda, cfg->sda_mode);
rt_pin_write(cfg->scl, PIN_HIGH);
rt_pin_write(cfg->sda, PIN_HIGH);
}
/**
* This function sets the sda pin.
*
* @param data ab32 config class.
* @param state The sda pin state.
*/
static void ab32_set_sda(void *data, rt_int32_t state)
{
struct ab32_soft_i2c_config* cfg = (struct ab32_soft_i2c_config*)data;
if (cfg->sda_mode == PIN_MODE_INPUT_PULLUP) {
cfg->sda_mode = PIN_MODE_OUTPUT_OD;
rt_pin_mode(cfg->sda, cfg->sda_mode);
}
if (state)
{
rt_pin_write(cfg->sda, PIN_HIGH);
}
else
{
rt_pin_write(cfg->sda, PIN_LOW);
}
}
/**
* This function sets the scl pin.
*
* @param data ab32 config class.
* @param state The scl pin state.
*/
static void ab32_set_scl(void *data, rt_int32_t state)
{
struct ab32_soft_i2c_config* cfg = (struct ab32_soft_i2c_config*)data;
if (cfg->scl_mode == PIN_MODE_INPUT_PULLUP) {
cfg->scl_mode = PIN_MODE_OUTPUT_OD;
rt_pin_mode(cfg->scl, cfg->scl_mode);
}
if (state)
{
rt_pin_write(cfg->scl, PIN_HIGH);
}
else
{
rt_pin_write(cfg->scl, PIN_LOW);
}
}
/**
* This function gets the sda pin state.
*
* @param data The sda pin state.
*/
static rt_int32_t ab32_get_sda(void *data)
{
struct ab32_soft_i2c_config* cfg = (struct ab32_soft_i2c_config*)data;
if (cfg->sda_mode != PIN_MODE_INPUT_PULLUP) {
cfg->sda_mode = PIN_MODE_INPUT_PULLUP;
rt_pin_mode(cfg->sda, cfg->sda_mode);
}
return rt_pin_read(cfg->sda);
}
/**
* This function gets the scl pin state.
*
* @param data The scl pin state.
*/
static rt_int32_t ab32_get_scl(void *data)
{
struct ab32_soft_i2c_config* cfg = (struct ab32_soft_i2c_config*)data;
if (cfg->scl_mode == PIN_MODE_INPUT_PULLUP) {
cfg->scl_mode = PIN_MODE_INPUT_PULLUP;
rt_pin_mode(cfg->scl, cfg->scl_mode);
}
return rt_pin_read(cfg->scl);
}
/**
* The time delay function.
*
* @param us microseconds.
*/
static void ab32_udelay(rt_uint32_t us)
{
rt_uint32_t ticks;
rt_uint32_t told, tnow, tcnt = 0;
rt_uint32_t reload = TMR0PR;
ticks = us * reload / (1000 / RT_TICK_PER_SECOND);
told = TMR0CNT;
while (1)
{
tnow = TMR0CNT;
if (tnow != told)
{
if (tnow < told)
{
tcnt += told - tnow;
}
else
{
tcnt += reload - tnow + told;
}
told = tnow;
if (tcnt >= ticks)
{
break;
}
}
}
}
static const struct rt_i2c_bit_ops ab32_bit_ops_default =
{
.data = RT_NULL,
.set_sda = ab32_set_sda,
.set_scl = ab32_set_scl,
.get_sda = ab32_get_sda,
.get_scl = ab32_get_scl,
.udelay = ab32_udelay,
.delay_us = 1,
.timeout = 100
};
/**
* if i2c is locked, this function will unlock it
*
* @param cfg ab32 config class
*
* @return RT_EOK indicates successful unlock.
*/
static rt_err_t ab32_i2c_bus_unlock(const struct ab32_soft_i2c_config *cfg)
{
rt_int32_t i = 0;
if (PIN_LOW == rt_pin_read(cfg->sda))
{
while (i++ < 9)
{
rt_pin_write(cfg->scl, PIN_HIGH);
ab32_udelay(100);
rt_pin_write(cfg->scl, PIN_LOW);
ab32_udelay(100);
}
}
if (PIN_LOW == rt_pin_read(cfg->sda))
{
return -RT_ERROR;
}
return RT_EOK;
}
/* I2C initialization function */
int rt_hw_i2c_init(void)
{
rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct ab32_i2c);
rt_err_t result;
for (int i = 0; i < obj_num; i++)
{
i2c_obj[i].ops = ab32_bit_ops_default;
i2c_obj[i].ops.data = (void*)&soft_i2c_config[i];
i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops;
ab32_i2c_gpio_init(&i2c_obj[i]);
result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name);
RT_ASSERT(result == RT_EOK);
ab32_i2c_bus_unlock(&soft_i2c_config[i]);
LOG_D("software simulation %s init done, pin scl: %d, pin sda %d",
soft_i2c_config[i].bus_name,
soft_i2c_config[i].scl,
soft_i2c_config[i].sda);
}
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_hw_i2c_init);
#endif
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-07 greedyhao first version
*/
#ifndef __DRV_I2C__
#define __DRV_I2C__
#include <rtthread.h>
#include <rthw.h>
#include <rtdevice.h>
/* ab32 config class */
struct ab32_soft_i2c_config
{
rt_uint8_t scl;
rt_uint8_t sda;
rt_uint8_t sda_mode;
rt_uint8_t scl_mode;
const char *bus_name;
};
/* ab32 i2c dirver class */
struct ab32_i2c
{
struct rt_i2c_bit_ops ops;
struct rt_i2c_bus_device i2c2_bus;
};
#ifdef BSP_USING_I2C1
#define I2C1_BUS_CONFIG \
{ \
.scl = BSP_I2C1_SCL_PIN, \
.sda = BSP_I2C1_SDA_PIN, \
.bus_name = "i2c1", \
}
#endif
#ifdef BSP_USING_I2C2
#define I2C2_BUS_CONFIG \
{ \
.scl = BSP_I2C2_SCL_PIN, \
.sda = BSP_I2C2_SDA_PIN, \
.bus_name = "i2c2", \
}
#endif
#ifdef BSP_USING_I2C3
#define I2C3_BUS_CONFIG \
{ \
.scl = BSP_I2C3_SCL_PIN, \
.sda = BSP_I2C3_SDA_PIN, \
.bus_name = "i2c3", \
}
#endif
#ifdef BSP_USING_I2C4
#define I2C4_BUS_CONFIG \
{ \
.scl = BSP_I2C4_SCL_PIN, \
.sda = BSP_I2C4_SDA_PIN, \
.bus_name = "i2c4", \
}
#endif
int rt_hw_i2c_init(void);
#endif
/*
* Copyright (c) 2020-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2006-2020, Bluetrum Development Team
*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
......
/*
* Copyright (c) 2020-2021, Bluetrum Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2020-11-30 greedyhao first version
*/
#include <board.h>
#ifdef RT_USING_WDT
// #define DRV_DEBUG
#define LOG_TAG "drv.wdt"
#include <drv_log.h>
struct ab32_wdt_obj
{
rt_watchdog_t watchdog;
};
static struct ab32_wdt_obj ab32_wdt;
static struct rt_watchdog_ops ops;
static rt_err_t wdt_init(rt_watchdog_t *wdt)
{
return RT_EOK;
}
static rt_err_t wdt_control(rt_watchdog_t *wdt, int cmd, void *arg)
{
rt_uint32_t tmp = 0;
switch (cmd)
{
/* feed the watchdog */
case RT_DEVICE_CTRL_WDT_KEEPALIVE:
WDTCON = 0xa;
break;
/* set watchdog timeout */
case RT_DEVICE_CTRL_WDT_SET_TIMEOUT:
if (arg == RT_NULL) {
LOG_E("The watchdog timeout argument cannot be NULL!");
break;
}
tmp = WDTCON & ~(0x7 << 20);
switch (*((rt_uint32_t *)arg))
{
case 0:
LOG_I("The watchdog timeout is set to 1ms");
tmp |= (0xa << 24) | (0x00 << 20);
break;
case 1:
LOG_I("The watchdog timeout is set to 256ms");
tmp |= (0xa << 24) | (0x01 << 20);
break;
case 2:
LOG_I("The watchdog timeout is set to 512ms");
tmp |= (0xa << 24) | (0x02 << 20);
break;
case 3:
LOG_I("The watchdog timeout is set to 1024ms");
tmp |= (0xa << 24) | (0x03 << 20);
break;
case 4:
LOG_I("The watchdog timeout is set to 2048ms");
tmp |= (0xa << 24) | (0x04 << 20);
break;
case 5:
LOG_I("The watchdog timeout is set to 4096ms");
tmp |= (0xa << 24) | (0x05 << 20);
break;
case 6:
LOG_I("The watchdog timeout is set to 8192ms");
tmp |= (0xa << 24) | (0x06 << 20);
break;
case 7:
LOG_I("The watchdog timeout is set to 16384ms");
tmp |= (0xa << 24) | (0x07 << 20);
break;
default:
LOG_W("The watchdog timeout argument range from 0 to 7!");
tmp = WDTCON;
break;
}
WDTCON = tmp;
LOG_D("WDTCON=%X", WDTCON);
break;
case RT_DEVICE_CTRL_WDT_GET_TIMEOUT:
switch ((WDTCON >> 20) & 0x7)
{
case 0:
LOG_D("The watchdog timeout is set to 1ms");
break;
case 1:
LOG_D("The watchdog timeout is set to 256ms");
break;
case 2:
LOG_D("The watchdog timeout is set to 512ms");
break;
case 3:
LOG_D("The watchdog timeout is set to 1024ms");
break;
case 4:
LOG_D("The watchdog timeout is set to 2048ms");
break;
case 5:
LOG_D("The watchdog timeout is set to 4096ms");
break;
case 6:
LOG_D("The watchdog timeout is set to 8192ms");
break;
case 7:
LOG_D("The watchdog timeout is set to 16384ms");
break;
default:
break;
}
break;
case RT_DEVICE_CTRL_WDT_START:
WDTCON = 0x110;
break;
default:
LOG_W("This command is not supported.");
return -RT_ERROR;
}
return RT_EOK;
}
int rt_wdt_init(void)
{
ops.init = &wdt_init;
ops.control = &wdt_control;
ab32_wdt.watchdog.ops = &ops;
/* register watchdog device */
if (rt_hw_watchdog_register(&ab32_wdt.watchdog, "wdt", RT_DEVICE_FLAG_DEACTIVATE, RT_NULL) != RT_EOK)
{
LOG_E("wdt device register failed.");
return -RT_ERROR;
}
LOG_D("wdt device register success.");
return RT_EOK;
}
INIT_BOARD_EXPORT(rt_wdt_init);
#endif /* RT_USING_WDT */
......@@ -13,7 +13,8 @@
#define HAL_RCU_MODULE_ENABLED
#define HAL_WDT_MODULE_ENABLED
// #define HAL_DAC_MODULE_ENABLED
// #define HAL_SD_MODULE_ENABLED
#define HAL_SD_MODULE_ENABLED
#define HAL_TIM_MODULE_ENABLED
/* Includes */
#ifdef HAL_GPIO_MODULE_ENABLED
......@@ -40,6 +41,10 @@
#include "ab32vg1_hal_sd.h"
#endif
#ifdef HAL_TIM_MODULE_ENABLED
#include "ab32vg1_hal_tim.h"
#endif
#include <assert.h>
#endif
......@@ -8,35 +8,73 @@
#define AB32VG1_HAL_SD_H__
#include "ab32vg1_hal_def.h"
#include "ab32vg1_ll_sdio.h"
#include <stdbool.h>
struct sd_init
struct sd_card_info
{
// uint8_t
uint32_t rca; /*!< Specifies the Relative Card Address */
uint32_t capacity; /*!< Specifies the capacity of the card */
uint8_t abend; /*!< Specifies if the card is abnormal end */
uint8_t flag_sdhc; /*!< Specifies if the card is SDHC card */
uint8_t type; /*!< Specifies the card type */
uint8_t state; /*!< Specifies the card state */
uint8_t rw_state; /*!< Specifies the last r/w state of the card */
};
typedef struct sd_card_info* sd_card_info_t;
struct sd_card_info
struct sd_cfg
{
uint32_t rca; /*!< Specifies the Relative Card Address */
uint8_t type; /*!< Specifies the card type */
uint16_t go_ready_retry;
uint8_t identification_retry;
uint8_t rw_retry;
uint8_t rw_init_retry;
uint8_t stop_retry;
uint8_t rw_need_stop;
};
typedef struct sd_card_info* sd_card_info_t;
struct sd_handle
{
hal_sfr_t instance;
struct sd_init init;
struct sdio_init init;
struct sd_card_info sdcard;
struct sd_cfg cfg;
};
typedef struct sd_handle* sd_handle_t;
#define SD0N (0x00u)
#define SD0N (0x00u)
// #define CARD_SDSC (0x00u)
// #define CARD_SDHC (0x01u)
// #define CARD_SECURED (0x03u)
enum
{
CARD_INVAL = 0x00,
CARD_V1,
CARD_V2,
CARD_MMC
};
enum
{
HAL_SD_RW_STATE_IDLE = 0x00,
HAL_SD_RW_STATE_READ,
HAL_SD_RW_STATE_WRITE,
};
#define CARD_V1 (0x01u)
#define CARD_V2 (0x02u)
#define CARD_MMC (0x03u)
enum
{
HAL_SD_STATE_RESET = 0x00,
HAL_SD_STATE_NEW,
HAL_SD_STATE_OK,
HAL_SD_STATE_INVAL,
};
#define SDMMC_CHECK_PATTERM (0x000001AAu)
#define SDMMC0_BASE ((hal_sfr_t)&SD0CON)
/* Initialization functions */
hal_error_t hal_sd_init(sd_handle_t hsd);
void hal_sd_deinit(uint32_t sdx);
......@@ -44,7 +82,7 @@ void hal_sd_mspinit(sd_handle_t hsd);
hal_error_t hal_sd_control(uint32_t control, uint32_t arg);
void hal_sd_write(uint32_t sdx, uint32_t data);
uint32_t hal_sd_read(uint32_t sdx);
bool hal_sd_read(sd_handle_t hsd, void *buf, uint32_t lba);
// void hal_uart_write_it(uint32_t uartx, uint8_t data);
// uint8_t hal_uart_read_it(uint32_t uartx);
......
/*
* Copyright (c) 2020-2020, BLUETRUM Development Team
*
* SPDX-License-Identifier: Apache-2.0
*/
#ifndef AB32VG1_HAL_TIM_H__
#define AB32VG1_HAL_TIM_H__
#include "ab32vg1_hal_def.h"
enum
{
TMRxCON,
TMRxCPND,
TMRxCNT,
TMRxPR,
TMRxCPT,
TMRxDUTY0,
TMRxDUTY1,
TMRxDUTY2
};
#define TIM0_BASE ((hal_sfr_t)&TMR0CON)
#define TIM1_BASE ((hal_sfr_t)&TMR1CON)
#define TIM2_BASE ((hal_sfr_t)&TMR2CON)
#define TIM3_BASE ((hal_sfr_t)&TMR3CON)
#define TIM4_BASE ((hal_sfr_t)&TMR4CON)
#define TIM5_BASE ((hal_sfr_t)&TMR5CON)
#endif
......@@ -11,8 +11,28 @@
struct sdio_init
{
uint32_t tmp;
uint32_t clock_power_save; /*!< Specifies whether SDMMC Clock output is enabled or
disabled when the bus is idle. */
uint32_t clock_div; /*!< Specifies the clock frequency of the SDMMC controller.
This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
};
typedef struct sdio_init* sdio_init_t;
#define SDMMC_CLOCK_POWER_SAVE_DISABLE (0x00u)
#define SDMMC_CLOCK_POWER_SAVE_ENABLE (0x01u)
enum
{
SDxCON = 0, /* [20]:BUSY [19:17]:CRCS [16]:DCRCE [15]:NRPS [1]:Data bus width [0]:SD enable */
SDxCPND,
SDxBAUD,
SDxCMD,
SDxARG3,
SDxARG2,
SDxARG1,
SDxARG0,
SDxDMAADR,
SDxDMACNT,
};
#endif
#include "ab32vg1_hal.h"
#include "ab32vg1_ll_sdio.h"
#ifdef HAL_SD_MODULE_ENABLED
#include <stdbool.h>
#define HAL_LOG(...) hal_printf(__VA_ARGS__)
/************************* LL ************************************/
......@@ -27,37 +24,27 @@
#define RSP_BUSY_TIMEOUT 2400000 //大约2s
#define RSP_TIMEOUT 6000 //大约5ms
enum
{
SDCON = 0, /* [20]:BUSY [19:17]:CRCS [16]:DCRCE [15]:NRPS [1]:Data bus width [0]:SD enable */
SDCPND,
SDBAUD,
SDCMD,
SDARG3,
SDARG2,
SDARG1,
SDARG0,
SDDMAADR,
SDDMACNT,
};
uint8_t sysclk_update_baud(uint8_t baud);
void sdio_setbaud(hal_sfr_t sdiox, uint8_t baud)
{
sdiox[SDBAUD] = sysclk_update_baud(baud);
sdiox[SDxBAUD] = sysclk_update_baud(baud);
}
void sdio_init(hal_sfr_t sdiox, sdio_init_t init)
{
/* Set clock */
sdio_setbaud(sdiox, 199);
sdiox[SDxCON] = 0;
sdiox[SDCON] = 0;
hal_udelay(20);
sdiox[SDCON] |= BIT(0); /* SD control enable */
sdiox[SDCON] |= BIT(3); /* Keep clock output */
sdiox[SDCON] |= BIT(5); /* Data interrupt enable */
sdiox[SDxCON] |= BIT(0); /* SD control enable */
sdio_setbaud(sdiox, init->clock_div); /* Set clock */
if (init->clock_power_save == SDMMC_CLOCK_POWER_SAVE_DISABLE) {
sdiox[SDxCON] |= BIT(3); /* Keep clock output */
} else {
sdiox[SDxCON] &= ~BIT(3); /* Keep clock output */
}
sdiox[SDxCON] |= BIT(5); /* Data interrupt enable */
hal_mdelay(40);
}
......@@ -70,8 +57,8 @@ void sdio_init(hal_sfr_t sdiox, sdio_init_t init)
*/
bool sdio_check_finish(hal_sfr_t sdiox)
{
if (sdiox[SDCON] & BIT(12)) {
sdiox[SDCPND] = BIT(12);
if (sdiox[SDxCON] & BIT(12)) {
sdiox[SDxCPND] = BIT(12);
return true;
}
return false;
......@@ -86,19 +73,21 @@ bool sdio_check_finish(hal_sfr_t sdiox)
*/
bool sdio_check_rsp(hal_sfr_t sdiox)
{
return !(sdiox[SDCON] & BIT(15));
return !(sdiox[SDxCON] & BIT(15));
}
bool sdio_send_cmd(hal_sfr_t sdiox, uint32_t cmd, uint32_t arg)
bool sdio_send_cmd(hal_sfr_t sdiox, uint32_t cmd, uint32_t arg, uint8_t *abend)
{
uint32_t time_out = (cmd & CBUSY) ? RSP_BUSY_TIMEOUT : RSP_TIMEOUT;
sdiox[SDCMD] = cmd;
sdiox[SDARG3] = arg;
sdiox[SDxARG3] = arg;
sdiox[SDxCMD] = cmd;
while (sdio_check_finish(sdiox) == false) {
if (--time_out == 0) {
HAL_LOG("cmd time out\n");
// card.abend = 1;
if (abend != HAL_NULL) {
*abend = 1;
}
return false;
}
}
......@@ -108,57 +97,258 @@ bool sdio_send_cmd(hal_sfr_t sdiox, uint32_t cmd, uint32_t arg)
uint8_t sdio_get_cmd_rsp(hal_sfr_t sdiox)
{
return -1;
return sdiox[SDxCMD];
}
uint32_t sdio_get_rsp(hal_sfr_t sdiox, uint32_t rsp)
uint32_t sdio_get_rsp(hal_sfr_t sdiox, uint32_t rsp_reg)
{
return -1;
return sdiox[rsp_reg];
}
void sdio_read_kick(hal_sfr_t sdiox, void* buf)
{}
{
sdiox[SDxDMAADR] = DMA_ADR(buf);
sdiox[SDxDMACNT] = 512;
}
void sdio_write_kick(hal_sfr_t sdiox, void* buf)
{}
{
sdiox[SDxDMAADR] = DMA_ADR(buf);
sdiox[SDxDMACNT] = BIT(18) | BIT(17) | BIT(16) | 512;
}
bool sdio_isbusy(hal_sfr_t sdiox)
{
return false;
}
void sdmmc_go_idle_state(hal_sfr_t sdiox)
bool sdmmc_cmd_go_idle_state(sd_handle_t hsd)
{
return sdio_send_cmd(hsd->instance, 0 | RSP_NO, hsd->sdcard.rca, &(hsd->sdcard.abend));
}
bool sdmmc_cmd_send_if_cond(sd_handle_t hsd)
{
return sdio_send_cmd(hsd->instance, 8 | RSP_7, SDMMC_CHECK_PATTERM, &(hsd->sdcard.abend));
}
bool sdmmc_cmd_all_send_cid(sd_handle_t hsd)
{
return sdio_send_cmd(hsd->instance, 2 | RSP_2, 0, &(hsd->sdcard.abend));
}
void sdmmc_cmd_set_rel_addr(sd_handle_t hsd)
{
hal_sfr_t sdiox = hsd->instance;
if (hsd->sdcard.type == CARD_MMC) {
hsd->sdcard.rca = 0x00010000;
sdio_send_cmd(sdiox, 3 | RSP_1, hsd->sdcard.rca, &(hsd->sdcard.abend));
} else {
sdio_send_cmd(sdiox, 3 | RSP_6, 0, &(hsd->sdcard.abend));
hsd->sdcard.rca = sdio_get_rsp(sdiox, SDxARG3) & 0xffff0000;
}
}
void sdmmc_cmd_send_csd(sd_handle_t hsd)
{
hal_sfr_t sdiox = hsd->instance;
sdio_send_cmd(sdiox, 9 | RSP_2, hsd->sdcard.rca, &(hsd->sdcard.abend));
if (hsd->sdcard.type == CARD_MMC) {
//
} else {
if (hsd->sdcard.flag_sdhc == 1) {
hsd->sdcard.capacity = (sdio_get_rsp(sdiox, SDxARG2) << 24) & 0x00ff0000; /* rspbuf[8] */
hsd->sdcard.capacity |= ((sdio_get_rsp(sdiox, SDxARG1) >> 16) & 0x0000ffff); /* rspbuf[9] rspbuf[10] */
hsd->sdcard.capacity += 1;
hsd->sdcard.capacity <<= 10;
}
}
HAL_LOG("sd capacity=%d\n", hsd->sdcard.capacity);
}
void sdmmc_cmd_select_card(sd_handle_t hsd)
{
// hal_sfr_t sdiox = hsd->instance;
sdio_send_cmd(sdiox, 0x00 | RSP_NO, 0);
sdio_send_cmd(hsd->instance, 7 | RSP_1B, hsd->sdcard.rca, &(hsd->sdcard.abend));
}
void sdmmc_send_if_cond(hal_sfr_t sdiox)
bool sdmmc_cmd_read_multiblock(sd_handle_t hsd)
{
// hal_sfr_t sdiox = hsd->instance;
sdio_send_cmd(sdiox, 0x08 | RSP_7, SDMMC_CHECK_PATTERM);
return sdio_send_cmd(hsd->instance, REQ_MULTREAD, hsd->sdcard.rca, &(hsd->sdcard.abend));
}
bool sdmmc_cmd_app(sd_handle_t hsd)
{
return sdio_send_cmd(hsd->instance, 55 | RSP_1, hsd->sdcard.rca, &(hsd->sdcard.abend));
}
bool sdmmc_acmd_op_cond(sd_handle_t hsd, uint32_t voltage)
{
/* SEND CMD55 APP_CMD with RCA */
if (sdmmc_cmd_app(hsd)) {
/* Send CMD41 */
if (sdio_send_cmd(hsd->instance, 41 | RSP_3, voltage, &(hsd->sdcard.abend))) {
return true;
}
}
return false;
}
/************************* HAL ************************************/
static bool sd_type_identification(sd_handle_t hsd)
{
uint8_t retry = hsd->cfg.identification_retry;
while (retry-- > 0)
{
/* CMD0: GO_IDLE_STATE */
sdmmc_cmd_go_idle_state(hsd);
/* CMD8: SEND_IF_COND: Command available only on V2.0 cards */
if (sdmmc_cmd_send_if_cond(hsd)) {
if (sdio_get_cmd_rsp(hsd->instance) == 0x08) {
hsd->sdcard.type = CARD_V2;
HAL_LOG("SD 2.0\n");
return true;
}
continue;
}
if (sdmmc_acmd_op_cond(hsd, 0x00ff8000)) {
hsd->sdcard.type = CARD_V1;
HAL_LOG("SD 1.0\n");
return true;
}
hal_mdelay(20);
}
return false;
}
static void sd_poweron(sd_handle_t hsd)
static bool sd_go_ready_try(sd_handle_t hsd)
{
sdmmc_go_idle_state(hsd->instance);
sdmmc_send_if_cond(hsd->instance);
if (hsd->instance[SDCMD] == 0x08) {
hsd->sdcard.type = CARD_V2;
HAL_LOG("SD 2.0\n");
uint32_t tmp = 0;
switch (hsd->sdcard.type)
{
case CARD_V1:
sdmmc_acmd_op_cond(hsd, 0x00ff8000);
break;
case CARD_V2:
sdmmc_acmd_op_cond(hsd, 0x40ff8000);
break;
default:
break;
}
if (0 == (hsd->instance[SDxARG3] & BIT(31))) {
return false; // no ready
}
if ((hsd->sdcard.type == CARD_V2) && (hsd->instance[SDxARG3] & BIT(30))) {
HAL_LOG("SDHC\n");
hsd->sdcard.flag_sdhc = 1;
}
return true;
}
static bool sd_go_ready(sd_handle_t hsd)
{
if (hsd->sdcard.type == CARD_INVAL) {
return false;
}
uint8_t retry = hsd->cfg.go_ready_retry;
while (retry-- > 0)
{
if (sd_go_ready_try(hsd) == true) {
return true;
}
hal_mdelay(20);
}
return false;
}
static bool sd_poweron(sd_handle_t hsd)
{
if (sd_type_identification(hsd) == false) {
HAL_LOG("card invalid\n");
return false;
}
if (sd_go_ready(hsd) == false) {
HAL_LOG("no ready\n");
return false;
}
return true;
}
static void sd_init_card(sd_handle_t hsd)
{
/* Send CMD2 ALL_SEND_CID */
sdmmc_cmd_all_send_cid(hsd);
/* Send CMD3 SET_REL_ADDR */
sdmmc_cmd_set_rel_addr(hsd);
/* Send CMD9 SEND_CSD */
sdmmc_cmd_send_csd(hsd);
/* Select the Card */
sdmmc_cmd_select_card(hsd);
hsd->init.clock_div = 3;
hsd->init.clock_power_save = SDMMC_CLOCK_POWER_SAVE_ENABLE;
sdio_init(hsd->instance, &(hsd->init));
}
static bool sd_read_wait(sd_handle_t hsd)
{
bool ret = false;
hal_sfr_t sdiox = hsd->instance;
return ret;
}
static void sd_read_start(sd_handle_t hsd, void *buf, uint32_t lba)
{
if (hsd->sdcard.rw_state == HAL_SD_RW_STATE_READ) {
} else {
if (hsd->sdcard.rw_state == HAL_SD_RW_STATE_WRITE) {
}
sdio_read_kick(hsd->instance, buf);
sdmmc_cmd_read_multiblock(hsd);
}
hsd->sdcard.rw_state = HAL_SD_RW_STATE_READ;
// hsd->sdcard.rw_lba
}
static bool sd_read_try(sd_handle_t hsd, void *buf, uint32_t lba)
{
HAL_LOG("read: %08x\n", lba);
if (hsd->sdcard.capacity < lba) {
lba = hsd->sdcard.capacity - 1;
}
sd_read_start(hsd, buf, lba);
return 0;
}
void hal_sd_initcard(sd_handle_t hsd)
{
struct sdio_init init = {0};
hal_sfr_t sdiox = hsd->instance;
sdio_init(sdiox, &init);
hsd->init.clock_div = 119; /* SD clk 240KHz when system clk is 48MHz */
hsd->init.clock_power_save = SDMMC_CLOCK_POWER_SAVE_DISABLE;
sdio_init(sdiox, &(hsd->init));
sd_poweron(hsd);
sd_init_card(hsd);
}
WEAK void hal_sd_mspinit(sd_handle_t hsd)
......@@ -171,6 +361,11 @@ hal_error_t hal_sd_init(sd_handle_t hsd)
return -HAL_ERROR;
}
hsd->cfg.go_ready_retry = 200;
hsd->cfg.identification_retry = 5;
hsd->cfg.rw_init_retry = 3;
hsd->cfg.rw_retry = 3;
hal_sd_mspinit(hsd);
hal_sd_initcard(hsd);
......@@ -181,4 +376,25 @@ void hal_sd_deinit(uint32_t sdx)
{
}
bool hal_sd_read(sd_handle_t hsd, void *buf, uint32_t lba)
{
uint8_t init_retry = hsd->cfg.rw_init_retry;
while (init_retry-- > 0)
{
uint8_t retry = hsd->cfg.rw_retry;
while (retry-- > 0)
{
if (sd_read_try(hsd, buf, lba)) {
return true;
}
}
hsd->sdcard.state = HAL_SD_STATE_INVAL;
hal_mdelay(20);
}
return false;
}
#endif
......@@ -14,8 +14,8 @@ define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM_end__];
define region IROM_region = mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
......@@ -31,6 +31,4 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
place in EROM_region { readonly section application_specific_ro };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
place in ERAM_region { readwrite section application_specific_rw };
\ No newline at end of file
......@@ -14,8 +14,8 @@ define symbol __ICFEDIT_size_proc_stack__ = 0x0;
define symbol __ICFEDIT_size_heap__ = 0x0800;
/**** End of ICF editor section. ###ICF###*/
define memory mem with size = 4G;
define region IROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM_end__];
define region IROM_region = mem:[from __ICFEDIT_region_IROM_start__ to __ICFEDIT_region_IROM_end__];
define region IRAM_region = mem:[from __ICFEDIT_region_IRAM_start__ to __ICFEDIT_region_IRAM_end__];
define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { };
define block PROC_STACK with alignment = 8, size = __ICFEDIT_size_proc_stack__ { };
define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { };
......@@ -31,6 +31,4 @@ if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec };
place in IROM_region { readonly };
place in EROM_region { readonly section application_specific_ro };
place in IRAM_region { readwrite, block CSTACK, block PROC_STACK, block HEAP };
place in ERAM_region { readwrite section application_specific_rw };
\ No newline at end of file
#
# Automatically generated file; DO NOT EDIT.
# RT-Thread Configuration
#
#
# RT-Thread Kernel
#
CONFIG_RT_NAME_MAX=8
# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
# CONFIG_RT_USING_SMP is not set
CONFIG_RT_ALIGN_SIZE=4
# CONFIG_RT_THREAD_PRIORITY_8 is not set
CONFIG_RT_THREAD_PRIORITY_32=y
# CONFIG_RT_THREAD_PRIORITY_256 is not set
CONFIG_RT_THREAD_PRIORITY_MAX=32
CONFIG_RT_TICK_PER_SECOND=100
CONFIG_RT_USING_OVERFLOW_CHECK=y
CONFIG_RT_USING_HOOK=y
CONFIG_RT_USING_IDLE_HOOK=y
CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
CONFIG_IDLE_THREAD_STACK_SIZE=256
# CONFIG_RT_USING_TIMER_SOFT is not set
CONFIG_RT_DEBUG=y
CONFIG_RT_DEBUG_COLOR=y
# CONFIG_RT_DEBUG_INIT_CONFIG is not set
# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
# CONFIG_RT_DEBUG_IPC_CONFIG is not set
# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
# CONFIG_RT_DEBUG_MEM_CONFIG is not set
# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
#
# Inter-Thread communication
#
CONFIG_RT_USING_SEMAPHORE=y
CONFIG_RT_USING_MUTEX=y
CONFIG_RT_USING_EVENT=y
CONFIG_RT_USING_MAILBOX=y
CONFIG_RT_USING_MESSAGEQUEUE=y
# CONFIG_RT_USING_SIGNALS is not set
#
# Memory Management
#
CONFIG_RT_USING_MEMPOOL=y
# CONFIG_RT_USING_MEMHEAP is not set
# CONFIG_RT_USING_NOHEAP is not set
CONFIG_RT_USING_SMALL_MEM=y
# CONFIG_RT_USING_SLAB is not set
# CONFIG_RT_USING_USERHEAP is not set
# CONFIG_RT_USING_MEMTRACE is not set
CONFIG_RT_USING_HEAP=y
#
# Kernel Device Object
#
CONFIG_RT_USING_DEVICE=y
# CONFIG_RT_USING_DEVICE_OPS is not set
# CONFIG_RT_USING_INTERRUPT_INFO is not set
CONFIG_RT_USING_CONSOLE=y
CONFIG_RT_CONSOLEBUF_SIZE=128
CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
CONFIG_RT_VER_NUM=0x40003
CONFIG_ARCH_ARM=y
# CONFIG_RT_USING_CPU_FFS is not set
CONFIG_ARCH_ARM_CORTEX_M=y
CONFIG_ARCH_ARM_CORTEX_M0=y
# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
#
# RT-Thread Components
#
CONFIG_RT_USING_COMPONENTS_INIT=y
CONFIG_RT_USING_USER_MAIN=y
CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
CONFIG_RT_MAIN_THREAD_PRIORITY=10
#
# C++ features
#
# CONFIG_RT_USING_CPLUSPLUS is not set
#
# Command shell
#
CONFIG_RT_USING_FINSH=y
CONFIG_FINSH_THREAD_NAME="tshell"
CONFIG_FINSH_USING_HISTORY=y
CONFIG_FINSH_HISTORY_LINES=5
CONFIG_FINSH_USING_SYMTAB=y
CONFIG_FINSH_USING_DESCRIPTION=y
# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
CONFIG_FINSH_THREAD_PRIORITY=20
CONFIG_FINSH_THREAD_STACK_SIZE=4096
CONFIG_FINSH_CMD_SIZE=80
# CONFIG_FINSH_USING_AUTH is not set
CONFIG_FINSH_USING_MSH=y
CONFIG_FINSH_USING_MSH_DEFAULT=y
CONFIG_FINSH_USING_MSH_ONLY=y
CONFIG_FINSH_ARG_MAX=10
#
# Device virtual file system
#
# CONFIG_RT_USING_DFS is not set
#
# Device Drivers
#
CONFIG_RT_USING_DEVICE_IPC=y
CONFIG_RT_PIPE_BUFSZ=512
# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
CONFIG_RT_USING_SERIAL=y
CONFIG_RT_SERIAL_USING_DMA=y
CONFIG_RT_SERIAL_RB_BUFSZ=64
# CONFIG_RT_USING_CAN is not set
# CONFIG_RT_USING_HWTIMER is not set
# CONFIG_RT_USING_CPUTIME is not set
# CONFIG_RT_USING_I2C is not set
# CONFIG_RT_USING_PHY is not set
CONFIG_RT_USING_PIN=y
# CONFIG_RT_USING_ADC is not set
# CONFIG_RT_USING_DAC is not set
# CONFIG_RT_USING_PWM is not set
# CONFIG_RT_USING_MTD_NOR is not set
# CONFIG_RT_USING_MTD_NAND is not set
# CONFIG_RT_USING_PM is not set
# CONFIG_RT_USING_RTC is not set
# CONFIG_RT_USING_SDIO is not set
# CONFIG_RT_USING_SPI is not set
# CONFIG_RT_USING_WDT is not set
# CONFIG_RT_USING_AUDIO is not set
# CONFIG_RT_USING_SENSOR is not set
# CONFIG_RT_USING_TOUCH is not set
# CONFIG_RT_USING_HWCRYPTO is not set
# CONFIG_RT_USING_PULSE_ENCODER is not set
# CONFIG_RT_USING_INPUT_CAPTURE is not set
# CONFIG_RT_USING_WIFI is not set
#
# Using USB
#
# CONFIG_RT_USING_USB_HOST is not set
# CONFIG_RT_USING_USB_DEVICE is not set
#
# POSIX layer and C standard library
#
# CONFIG_RT_USING_LIBC is not set
# CONFIG_RT_USING_PTHREADS is not set
CONFIG_RT_LIBC_USING_TIME=y
#
# Network
#
#
# Socket abstraction layer
#
# CONFIG_RT_USING_SAL is not set
#
# Network interface device
#
# CONFIG_RT_USING_NETDEV is not set
#
# light weight TCP/IP stack
#
# CONFIG_RT_USING_LWIP is not set
#
# AT commands
#
# CONFIG_RT_USING_AT is not set
#
# VBUS(Virtual Software BUS)
#
# CONFIG_RT_USING_VBUS is not set
#
# Utilities
#
# CONFIG_RT_USING_RYM is not set
# CONFIG_RT_USING_ULOG is not set
# CONFIG_RT_USING_UTEST is not set
# CONFIG_RT_USING_LWP is not set
#
# RT-Thread online packages
#
#
# IoT - internet of things
#
# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
# CONFIG_PKG_USING_PAHOMQTT is not set
# CONFIG_PKG_USING_UMQTT is not set
# CONFIG_PKG_USING_WEBCLIENT is not set
# CONFIG_PKG_USING_WEBNET is not set
# CONFIG_PKG_USING_MONGOOSE is not set
# CONFIG_PKG_USING_MYMQTT is not set
# CONFIG_PKG_USING_KAWAII_MQTT is not set
# CONFIG_PKG_USING_BC28_MQTT is not set
# CONFIG_PKG_USING_WEBTERMINAL is not set
# CONFIG_PKG_USING_CJSON is not set
# CONFIG_PKG_USING_JSMN is not set
# CONFIG_PKG_USING_LIBMODBUS is not set
# CONFIG_PKG_USING_FREEMODBUS is not set
# CONFIG_PKG_USING_LJSON is not set
# CONFIG_PKG_USING_EZXML is not set
# CONFIG_PKG_USING_NANOPB is not set
#
# Wi-Fi
#
#
# Marvell WiFi
#
# CONFIG_PKG_USING_WLANMARVELL is not set
#
# Wiced WiFi
#
# CONFIG_PKG_USING_WLAN_WICED is not set
# CONFIG_PKG_USING_RW007 is not set
# CONFIG_PKG_USING_COAP is not set
# CONFIG_PKG_USING_NOPOLL is not set
# CONFIG_PKG_USING_NETUTILS is not set
# CONFIG_PKG_USING_CMUX is not set
# CONFIG_PKG_USING_PPP_DEVICE is not set
# CONFIG_PKG_USING_AT_DEVICE is not set
# CONFIG_PKG_USING_ATSRV_SOCKET is not set
# CONFIG_PKG_USING_WIZNET is not set
#
# IoT Cloud
#
# CONFIG_PKG_USING_ONENET is not set
# CONFIG_PKG_USING_GAGENT_CLOUD is not set
# CONFIG_PKG_USING_ALI_IOTKIT is not set
# CONFIG_PKG_USING_AZURE is not set
# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
# CONFIG_PKG_USING_JIOT-C-SDK is not set
# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
# CONFIG_PKG_USING_JOYLINK is not set
# CONFIG_PKG_USING_NIMBLE is not set
# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
# CONFIG_PKG_USING_IPMSG is not set
# CONFIG_PKG_USING_LSSDP is not set
# CONFIG_PKG_USING_AIRKISS_OPEN is not set
# CONFIG_PKG_USING_LIBRWS is not set
# CONFIG_PKG_USING_TCPSERVER is not set
# CONFIG_PKG_USING_PROTOBUF_C is not set
# CONFIG_PKG_USING_ONNX_PARSER is not set
# CONFIG_PKG_USING_ONNX_BACKEND is not set
# CONFIG_PKG_USING_DLT645 is not set
# CONFIG_PKG_USING_QXWZ is not set
# CONFIG_PKG_USING_SMTP_CLIENT is not set
# CONFIG_PKG_USING_ABUP_FOTA is not set
# CONFIG_PKG_USING_LIBCURL2RTT is not set
# CONFIG_PKG_USING_CAPNP is not set
# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
# CONFIG_PKG_USING_AGILE_TELNET is not set
# CONFIG_PKG_USING_NMEALIB is not set
# CONFIG_PKG_USING_AGILE_JSMN is not set
# CONFIG_PKG_USING_PDULIB is not set
# CONFIG_PKG_USING_BTSTACK is not set
# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
#
# security packages
#
# CONFIG_PKG_USING_MBEDTLS is not set
# CONFIG_PKG_USING_libsodium is not set
# CONFIG_PKG_USING_TINYCRYPT is not set
# CONFIG_PKG_USING_TFM is not set
# CONFIG_PKG_USING_YD_CRYPTO is not set
#
# language packages
#
# CONFIG_PKG_USING_LUA is not set
# CONFIG_PKG_USING_JERRYSCRIPT is not set
# CONFIG_PKG_USING_MICROPYTHON is not set
#
# multimedia packages
#
# CONFIG_PKG_USING_OPENMV is not set
# CONFIG_PKG_USING_MUPDF is not set
# CONFIG_PKG_USING_STEMWIN is not set
# CONFIG_PKG_USING_WAVPLAYER is not set
# CONFIG_PKG_USING_TJPGD is not set
# CONFIG_PKG_USING_HELIX is not set
# CONFIG_PKG_USING_AZUREGUIX is not set
# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
#
# tools packages
#
# CONFIG_PKG_USING_CMBACKTRACE is not set
# CONFIG_PKG_USING_EASYFLASH is not set
# CONFIG_PKG_USING_EASYLOGGER is not set
# CONFIG_PKG_USING_SYSTEMVIEW is not set
# CONFIG_PKG_USING_RDB is not set
# CONFIG_PKG_USING_QRCODE is not set
# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
# CONFIG_PKG_USING_ADBD is not set
# CONFIG_PKG_USING_COREMARK is not set
# CONFIG_PKG_USING_DHRYSTONE is not set
# CONFIG_PKG_USING_MEMORYPERF is not set
# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
# CONFIG_PKG_USING_BS8116A is not set
# CONFIG_PKG_USING_GPS_RMC is not set
# CONFIG_PKG_USING_URLENCODE is not set
# CONFIG_PKG_USING_UMCN is not set
# CONFIG_PKG_USING_LWRB2RTT is not set
#
# system packages
#
# CONFIG_PKG_USING_GUIENGINE is not set
# CONFIG_PKG_USING_CAIRO is not set
# CONFIG_PKG_USING_PIXMAN is not set
# CONFIG_PKG_USING_LWEXT4 is not set
# CONFIG_PKG_USING_PARTITION is not set
# CONFIG_PKG_USING_FAL is not set
# CONFIG_PKG_USING_FLASHDB is not set
# CONFIG_PKG_USING_SQLITE is not set
# CONFIG_PKG_USING_RTI is not set
# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
# CONFIG_PKG_USING_CMSIS is not set
# CONFIG_PKG_USING_DFS_YAFFS is not set
# CONFIG_PKG_USING_LITTLEFS is not set
# CONFIG_PKG_USING_THREAD_POOL is not set
# CONFIG_PKG_USING_ROBOTS is not set
# CONFIG_PKG_USING_EV is not set
# CONFIG_PKG_USING_SYSWATCH is not set
# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
# CONFIG_PKG_USING_PLCCORE is not set
# CONFIG_PKG_USING_RAMDISK is not set
# CONFIG_PKG_USING_MININI is not set
# CONFIG_PKG_USING_QBOOT is not set
#
# Micrium: Micrium software products porting for RT-Thread
#
# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
# CONFIG_PKG_USING_UC_CRC is not set
# CONFIG_PKG_USING_UC_CLK is not set
# CONFIG_PKG_USING_UC_COMMON is not set
# CONFIG_PKG_USING_UC_MODBUS is not set
# CONFIG_PKG_USING_PPOOL is not set
#
# peripheral libraries and drivers
#
# CONFIG_PKG_USING_SENSORS_DRIVERS is not set
# CONFIG_PKG_USING_REALTEK_AMEBA is not set
# CONFIG_PKG_USING_SHT2X is not set
# CONFIG_PKG_USING_SHT3X is not set
# CONFIG_PKG_USING_STM32_SDIO is not set
# CONFIG_PKG_USING_ICM20608 is not set
# CONFIG_PKG_USING_U8G2 is not set
# CONFIG_PKG_USING_BUTTON is not set
# CONFIG_PKG_USING_PCF8574 is not set
# CONFIG_PKG_USING_SX12XX is not set
# CONFIG_PKG_USING_SIGNAL_LED is not set
# CONFIG_PKG_USING_LEDBLINK is not set
# CONFIG_PKG_USING_LITTLED is not set
# CONFIG_PKG_USING_LKDGUI is not set
# CONFIG_PKG_USING_NRF5X_SDK is not set
# CONFIG_PKG_USING_NRFX is not set
# CONFIG_PKG_USING_WM_LIBRARIES is not set
# CONFIG_PKG_USING_KENDRYTE_SDK is not set
# CONFIG_PKG_USING_INFRARED is not set
# CONFIG_PKG_USING_ROSSERIAL is not set
# CONFIG_PKG_USING_AGILE_BUTTON is not set
# CONFIG_PKG_USING_AGILE_LED is not set
# CONFIG_PKG_USING_AT24CXX is not set
# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
# CONFIG_PKG_USING_AD7746 is not set
# CONFIG_PKG_USING_PCA9685 is not set
# CONFIG_PKG_USING_I2C_TOOLS is not set
# CONFIG_PKG_USING_NRF24L01 is not set
# CONFIG_PKG_USING_TOUCH_DRIVERS is not set
# CONFIG_PKG_USING_MAX17048 is not set
# CONFIG_PKG_USING_RPLIDAR is not set
# CONFIG_PKG_USING_AS608 is not set
# CONFIG_PKG_USING_RC522 is not set
# CONFIG_PKG_USING_WS2812B is not set
# CONFIG_PKG_USING_EMBARC_BSP is not set
# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
# CONFIG_PKG_USING_MULTI_RTIMER is not set
# CONFIG_PKG_USING_MAX7219 is not set
# CONFIG_PKG_USING_BEEP is not set
# CONFIG_PKG_USING_EASYBLINK is not set
# CONFIG_PKG_USING_PMS_SERIES is not set
# CONFIG_PKG_USING_CAN_YMODEM is not set
# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
# CONFIG_PKG_USING_QLED is not set
# CONFIG_PKG_USING_PAJ7620 is not set
# CONFIG_PKG_USING_AGILE_CONSOLE is not set
# CONFIG_PKG_USING_LD3320 is not set
# CONFIG_PKG_USING_WK2124 is not set
# CONFIG_PKG_USING_LY68L6400 is not set
# CONFIG_PKG_USING_DM9051 is not set
# CONFIG_PKG_USING_SSD1306 is not set
# CONFIG_PKG_USING_QKEY is not set
# CONFIG_PKG_USING_RS485 is not set
#
# miscellaneous packages
#
# CONFIG_PKG_USING_LIBCSV is not set
# CONFIG_PKG_USING_OPTPARSE is not set
# CONFIG_PKG_USING_FASTLZ is not set
# CONFIG_PKG_USING_MINILZO is not set
# CONFIG_PKG_USING_QUICKLZ is not set
# CONFIG_PKG_USING_MULTIBUTTON is not set
# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
# CONFIG_PKG_USING_CANFESTIVAL is not set
# CONFIG_PKG_USING_ZLIB is not set
# CONFIG_PKG_USING_DSTR is not set
# CONFIG_PKG_USING_TINYFRAME is not set
# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
# CONFIG_PKG_USING_DIGITALCTRL is not set
# CONFIG_PKG_USING_UPACKER is not set
# CONFIG_PKG_USING_UPARAM is not set
#
# samples: kernel and components samples
#
# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
# CONFIG_PKG_USING_HELLO is not set
# CONFIG_PKG_USING_VI is not set
# CONFIG_PKG_USING_KI is not set
# CONFIG_PKG_USING_NNOM is not set
# CONFIG_PKG_USING_LIBANN is not set
# CONFIG_PKG_USING_ELAPACK is not set
# CONFIG_PKG_USING_ARMv7M_DWT is not set
# CONFIG_PKG_USING_VT100 is not set
# CONFIG_PKG_USING_ULAPACK is not set
# CONFIG_PKG_USING_UKAL is not set
# CONFIG_PKG_USING_CRCLIB is not set
#
# games: games run on RT-Thread console
#
# CONFIG_PKG_USING_THREES is not set
# CONFIG_PKG_USING_2048 is not set
# CONFIG_PKG_USING_TETRIS is not set
# CONFIG_PKG_USING_LWGPS is not set
# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
#
# Privated Packages of RealThread
#
# CONFIG_PKG_USING_CODEC is not set
# CONFIG_PKG_USING_PLAYER is not set
# CONFIG_PKG_USING_MPLAYER is not set
# CONFIG_PKG_USING_PERSIMMON_SRC is not set
# CONFIG_PKG_USING_JS_PERSIMMON is not set
# CONFIG_PKG_USING_JERRYSCRIPT_WIN32 is not set
#
# Network Utilities
#
# CONFIG_PKG_USING_WICED is not set
# CONFIG_PKG_USING_CLOUDSDK is not set
# CONFIG_PKG_USING_POWER_MANAGER is not set
# CONFIG_PKG_USING_RT_OTA is not set
# CONFIG_PKG_USING_RDBD_SRC is not set
# CONFIG_PKG_USING_RTINSIGHT is not set
# CONFIG_PKG_USING_SMARTCONFIG is not set
# CONFIG_PKG_USING_RTX is not set
# CONFIG_RT_USING_TESTCASE is not set
# CONFIG_PKG_USING_NGHTTP2 is not set
# CONFIG_PKG_USING_AVS is not set
# CONFIG_PKG_USING_ALI_LINKKIT is not set
# CONFIG_PKG_USING_STS is not set
# CONFIG_PKG_USING_DLMS is not set
# CONFIG_PKG_USING_AUDIO_FRAMEWORK is not set
# CONFIG_PKG_USING_ZBAR is not set
# CONFIG_PKG_USING_MCF is not set
# CONFIG_PKG_USING_URPC is not set
# CONFIG_PKG_USING_BSAL is not set
# CONFIG_PKG_USING_DCM is not set
# CONFIG_PKG_USING_EMQ is not set
# CONFIG_PKG_USING_CFGM is not set
# CONFIG_PKG_USING_RT_CMSIS_DAP is not set
# CONFIG_PKG_USING_VIRTUAL_DEVICE is not set
# CONFIG_PKG_USING_SMODULE is not set
CONFIG_SOC_RP2040=y
mainmenu "RT-Thread Configuration"
config BSP_DIR
string
option env="BSP_ROOT"
default "."
config RTT_DIR
string
option env="RTT_ROOT"
default "../.."
config PKGS_DIR
string
option env="PKGS_ROOT"
default "packages"
source "$RTT_DIR/Kconfig"
source "$PKGS_DIR/Kconfig"
config SOC_RP2040
bool
select ARCH_ARM_CORTEX_M0
select RT_USING_COMPONENTS_INIT
select RT_USING_USER_MAIN
default y
# Raspberry PICO
## Introduction
**Raspberry Pi Pico is a low-cost, high-performance microcontroller board with flexible digital interfaces.**
**Key features include:**
- RP2040 microcontroller chip designed by Raspberry Pi in the United Kingdom
- Dual-core Arm Cortex M0+ processor, flexible clock running up to 133 MHz
- 264KB of SRAM, and 2MB of on-board Flash memory
- Castellated module allows soldering direct to carrier boards
- USB 1.1 with device and host support
- Low-power sleep and dormant modes
- Drag-and-drop programming using mass storage over USB
- 26 × multi-function GPIO pins
- 2 × SPI, 2 × I2C, 2 × UART, 3 × 12-bit ADC, 16 × controllable PWM channels
- Accurate clock and timer on-chip
- Temperature sensor
- Accelerated floating-point libraries on-chip
- 8 × Programmable I/O (PIO) state machines for custom peripheral support
![Pico-R3-Pinout](figures/Pico-R3-Pinout.svg)
## Supported compiler
Support GCC 6 and above compilers.
## Program firmware
### Step 1: build
```
scons -c
scons
```
**gcc version >= 6.x.x**
### Step 2: flash
Run the following command in the linux environment.
```
./libraries/generated/elf2uf2 rtthread-pico.elf rtthread-pico.uf2
```
- Copy the rtthread-pico.uf2 file to the "RPI-RP2" disk
- Then led blink.
## Running Result
The output information on serial port should be like this:
```
\ | /
- RT - Thread Operating System
/ | \ 4.0.3 build Jan 28 2021
2006 - 2021 Copyright by rt-thread team
Hello, RT-Thread!
msh >
```
## Peripheral Condition
| Drive | Support | Remark |
| ----- | ------- | ------ |
| UART | Support | UART0 |
| GPIO | Support | 0-29 |
| I2C | - | - |
| RTC | - | - |
| SDIO | - | - |
| SPI | - | - |
| TIMER | - | - |
| WDT | - | - |
from building import *
cwd = GetCurrentDir()
objs = []
list = os.listdir(cwd)
for d in list:
path = os.path.join(cwd, d)
if os.path.isfile(os.path.join(path, 'SConscript')):
objs = objs + SConscript(os.path.join(d, 'SConscript'))
Return('objs')
import os
import sys
import rtconfig
if os.getenv('RTT_ROOT'):
RTT_ROOT = os.getenv('RTT_ROOT')
else:
RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
from building import *
TARGET = 'rtthread-pico.' + rtconfig.TARGET_EXT
DefaultEnvironment(tools=[])
env = Environment(tools = ['mingw'],
AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
CXX = rtconfig.CXX,
AR = rtconfig.AR, ARFLAGS = '-rc',
LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
Export('RTT_ROOT')
Export('rtconfig')
# prepare building environment
objs = PrepareBuilding(env, RTT_ROOT)
# make a building
DoBuilding(TARGET, objs)
Import('RTT_ROOT')
Import('rtconfig')
from building import *
cwd = os.path.join(str(Dir('#')), 'applications')
src = Glob('*.c')
CPPPATH = [cwd, str(Dir('#'))]
group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#include <rtthread.h>
#include <rtdevice.h>
#define LED_PIN 25
int main(void)
{
rt_kprintf("Hello, RT-Thread!\n");
rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT);
while (1)
{
rt_pin_write(LED_PIN, 1);
rt_thread_mdelay(1000);
rt_pin_write(LED_PIN, 0);
rt_thread_mdelay(1000);
}
}
from building import *
cwd = GetCurrentDir()
src = Glob('*.c')
CPPPATH = [cwd]
group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH)
Return('group')
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#include <rthw.h>
#include <rtthread.h>
#include <stdio.h>
#include "board.h"
#include "hardware/structs/systick.h"
uint8_t heap[1024 * 80];
void isr_systick(void)
{
/* enter interrupt */
rt_interrupt_enter();
rt_tick_increase();
/* leave interrupt */
rt_interrupt_leave();
}
uint32_t systick_config(uint32_t ticks)
{
if ((ticks - 1UL) > M0PLUS_SYST_RVR_RELOAD_BITS)
{
return (1UL); /* Reload value impossible */
}
mpu_hw->rvr = (uint32_t)(ticks - 1UL); /* set reload register */
mpu_hw->csr = M0PLUS_SYST_CSR_CLKSOURCE_BITS |
M0PLUS_SYST_CSR_TICKINT_BITS |
M0PLUS_SYST_CSR_ENABLE_BITS; /* Enable SysTick IRQ and SysTick Timer */
return (0UL); /* Function successful */
}
void rt_hw_board_init()
{
/* Configure the SysTick */
systick_config(frequency_count_khz(CLOCKS_FC0_SRC_VALUE_ROSC_CLKSRC)*10000/RT_TICK_PER_SECOND);
rt_system_heap_init(heap, (uint8_t *)heap + sizeof(heap));
stdio_init_all();
rt_hw_uart_init();
#ifdef RT_USING_CONSOLE
rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
#endif
}
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#ifndef __BOARD_H__
#define __BOARD_H__
#include "pico/stdlib.h"
#include "hardware/pll.h"
#include "hardware/clocks.h"
#include "hardware/structs/pll.h"
#include "hardware/structs/clocks.h"
#define PICO_SRAM_SIZE 256
#define PICO_SRAM_END (0x20000000 + PICO_SRAM_SIZE * 1024)
extern int __bss_end;
#define HEAP_BEGIN (&__bss_end)
#define HEAP_END PICO_SRAM_END
int rt_hw_uart_init(void);
#endif
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#include "drv_gpio.h"
static void pico_pin_mode(struct rt_device *dev, rt_base_t pin, rt_base_t mode)
{
RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
gpio_init(pin);
switch (mode)
{
case PIN_MODE_OUTPUT:
gpio_set_dir(pin, GPIO_OUT);
break;
case PIN_MODE_INPUT:
gpio_set_dir(pin, GPIO_IN);
break;
case PIN_MODE_INPUT_PULLUP:
gpio_pull_up(pin);
break;
case PIN_MODE_INPUT_PULLDOWN:
gpio_pull_down(pin);
break;
case PIN_MODE_OUTPUT_OD:
gpio_disable_pulls(pin);
break;
}
}
static void pico_pin_write(struct rt_device *dev, rt_base_t pin, rt_base_t value)
{
RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
gpio_put(pin, value);
}
static int pico_pin_read(struct rt_device *device, rt_base_t pin)
{
RT_ASSERT((0 <= pin) && (pin < N_GPIOS));
return (gpio_get(pin)? PIN_HIGH : PIN_LOW);
}
static const struct rt_pin_ops ops =
{
pico_pin_mode,
pico_pin_write,
pico_pin_read,
RT_NULL,
RT_NULL,
RT_NULL,
RT_NULL,
};
int rt_hw_gpio_init(void)
{
rt_device_pin_register("gpio", &ops, RT_NULL);
return 0;
}
INIT_DEVICE_EXPORT(rt_hw_gpio_init);
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#ifndef __DRV_GPIO_H__
#define __DRV_GPIO_H__
#include <rtdevice.h>
#include <rtthread.h>
#include "board.h"
int rt_hw_gpio_init(void);
#endif /* __DRV_GPIO_H__ */
/*
* Copyright (c) 2006-2018, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
*/
#include <rthw.h>
#include <rtthread.h>
#include <rtdevice.h>
#include "board.h"
#include "drv_uart.h"
#include "hardware/uart.h"
#include "hardware/irq.h"
#define UART_ID uart0
#define BAUD_RATE 115200
#define DATA_BITS 8
#define STOP_BITS 1
#define PARITY UART_PARITY_NONE
// We are using pins 0 and 1, but see the GPIO function select table in the
// datasheet for information on which other pins can be used.
#define UART_TX_PIN 0
#define UART_RX_PIN 1
#define PICO_UART_DEVICE(uart) (struct pico_uart_dev *)(uart)
static struct pico_uart_dev uart0_dev;
struct pico_uart_dev
{
struct rt_serial_device parent;
rt_uint32_t uart_periph;
rt_uint32_t irqno;
};
void pico_uart_isr(void)
{
rt_interrupt_enter();
/* read interrupt status and clear it */
if (uart_is_readable(uart0)) /* rx ind */
{
rt_hw_serial_isr(&uart0_dev.parent, RT_SERIAL_EVENT_RX_IND);
}
rt_interrupt_leave();
}
/*
* UART interface
*/
static rt_err_t pico_uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg)
{
return RT_EOK;
}
static rt_err_t pico_uart_control(struct rt_serial_device *serial, int cmd, void *arg)
{
return RT_EOK;
}
static int pico_uart_putc(struct rt_serial_device *serial, char c)
{
uart_putc_raw(uart0, c);
return 1;
}
static int pico_uart_getc(struct rt_serial_device *serial)
{
int ch;
if (uart_is_readable(uart0))
{
ch = uart_get_hw(uart0)->dr;
}
else
{
ch =-1;
}
return ch;
}
const static struct rt_uart_ops _uart_ops =
{
pico_uart_configure,
pico_uart_control,
pico_uart_putc,
pico_uart_getc,
RT_NULL,
};
/*
* UART Initiation
*/
int rt_hw_uart_init(void)
{
rt_err_t ret = RT_EOK;
struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
uart_init(UART_ID, 115200);
// Set the TX and RX pins by using the function select on the GPIO
// Set datasheet for more information on function select
gpio_set_function(UART_TX_PIN, GPIO_FUNC_UART);
gpio_set_function(UART_RX_PIN, GPIO_FUNC_UART);
// Actually, we want a different speed
// The call will return the actual baud rate selected, which will be as close as
// possible to that requested
uart_set_baudrate(UART_ID, BAUD_RATE);
// Set UART flow control CTS/RTS, we don't want these, so turn them off
uart_set_hw_flow(UART_ID, false, false);
// Set our data format
uart_set_format(UART_ID, DATA_BITS, STOP_BITS, PARITY);
// Turn off FIFO's - we want to do this character by character
uart_set_fifo_enabled(UART_ID, false);
// Set up a RX interrupt
// We need to set up the handler first
// Select correct interrupt for the UART we are using
int UART_IRQ = UART_ID == uart0 ? UART0_IRQ : UART1_IRQ;
// And set up and enable the interrupt handlers
irq_set_exclusive_handler(UART_IRQ, pico_uart_isr);
irq_set_enabled(UART_IRQ, true);
// Now enable the UART to send interrupts - RX only
uart_set_irq_enables(UART_ID, true, false);
uart0_dev.parent.ops = &_uart_ops;
uart0_dev.parent.config = config;
ret = rt_hw_serial_register(&uart0_dev.parent,
"uart0",
RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
&uart0_dev);
return ret;
}
// INIT_DEVICE_EXPORT(rt_hw_uart_init);
/*
* Copyright (c) 2006-2021, RT-Thread Development Team
*
* SPDX-License-Identifier: Apache-2.0
*
* Change Logs:
* Date Author Notes
* 2021-01-28 flybreak first version
*/
#ifndef __USART_H__
#define __USART_H__
#include <rthw.h>
#include <rtthread.h>
int rt_hw_uart_init(void);
#endif
此差异已折叠。
import rtconfig
Import('RTT_ROOT')
from building import *
# get current directory
cwd = GetCurrentDir()
# The set of source files associated with this SConscript file.
src = Split("""
pico-sdk/src/rp2_common/pico_stdlib/stdlib.c
pico-sdk/src/rp2_common/hardware_gpio/gpio.c
pico-sdk/src/rp2_common/hardware_claim/claim.c
pico-sdk/src/rp2_common/hardware_sync/sync.c
pico-sdk/src/rp2_common/pico_platform/platform.c
pico-sdk/src/rp2_common/hardware_uart/uart.c
pico-sdk/src/common/pico_time/time.c
pico-sdk/src/common/pico_time/timeout_helper.c
pico-sdk/src/rp2_common/hardware_timer/timer.c
pico-sdk/src/common/pico_sync/sem.c
pico-sdk/src/common/pico_sync/lock_core.c
pico-sdk/src/common/pico_sync/mutex.c
pico-sdk/src/common/pico_sync/critical_section.c
pico-sdk/src/common/pico_util/datetime.c
pico-sdk/src/common/pico_util/pheap.c
pico-sdk/src/common/pico_util/queue.c
pico-sdk/src/rp2_common/pico_runtime/runtime.c
pico-sdk/src/rp2_common/hardware_clocks/clocks.c
pico-sdk/src/rp2_common/hardware_watchdog/watchdog.c
pico-sdk/src/rp2_common/hardware_xosc/xosc.c
pico-sdk/src/rp2_common/hardware_pll/pll.c
pico-sdk/src/rp2_common/hardware_vreg/vreg.c
pico-sdk/src/rp2_common/hardware_irq/irq.c
pico-sdk/src/rp2_common/pico_printf/printf.c
pico-sdk/src/rp2_common/pico_bootrom/bootrom.c
pico-sdk/src/rp2_common/pico_double/double_init_rom.c
pico-sdk/src/rp2_common/pico_double/double_math.c
pico-sdk/src/rp2_common/pico_float/float_aeabi.S
pico-sdk/src/rp2_common/pico_float/float_init_rom.c
pico-sdk/src/rp2_common/pico_float/float_math.c
pico-sdk/src/rp2_common/pico_malloc/pico_malloc.c
pico-sdk/src/rp2_common/pico_standard_link/binary_info.c
pico-sdk/src/rp2_common/pico_stdio/stdio.c
pico-sdk/src/rp2_common/pico_stdio_uart/stdio_uart.c
pico-sdk/src/rp2_common/pico_standard_link/new_delete.cpp
pico-sdk/src/rp2_common/hardware_irq/irq_handler_chain.S
pico-sdk/src/rp2_common/pico_bit_ops/bit_ops_aeabi.S
pico-sdk/src/rp2_common/pico_divider/divider.S
pico-sdk/src/rp2_common/pico_double/double_aeabi.S
pico-sdk/src/rp2_common/pico_double/double_v1_rom_shim.S
pico-sdk/src/rp2_common/pico_int64_ops/pico_int64_ops_aeabi.S
pico-sdk/src/rp2_common/pico_float/float_v1_rom_shim.S
pico-sdk/src/rp2_common/hardware_divider/divider.S
pico-sdk/src/rp2_common/pico_mem_ops/mem_ops_aeabi.S
pico-sdk/src/rp2_common/pico_standard_link/crt0.S
generated/bs2_default_padded_checksummed.S
""")
path = [
cwd + '/pico-sdk/src/common/pico_stdlib/include',
cwd + '/pico-sdk/src/rp2_common/hardware_gpio/include',
cwd + '/pico-sdk/src/common/pico_base/include',
cwd + '/pico-sdk/src/boards/include',
cwd + '/pico-sdk/src/rp2_common/pico_platform/include',
cwd + '/pico-sdk/src/rp2040/hardware_regs/include',
cwd + '/pico-sdk/src/rp2_common/hardware_base/include',
cwd + '/pico-sdk/src/rp2040/hardware_structs/include',
cwd + '/pico-sdk/src/rp2_common/hardware_claim/include',
cwd + '/pico-sdk/src/rp2_common/hardware_sync/include',
cwd + '/pico-sdk/src/rp2_common/hardware_uart/include',
cwd + '/pico-sdk/src/rp2_common/hardware_divider/include',
cwd + '/pico-sdk/src/common/pico_time/include',
cwd + '/pico-sdk/src/rp2_common/hardware_timer/include',
cwd + '/pico-sdk/src/common/pico_sync/include',
cwd + '/pico-sdk/src/common/pico_util/include',
cwd + '/pico-sdk/src/rp2_common/pico_runtime/include',
cwd + '/pico-sdk/src/rp2_common/hardware_clocks/include',
cwd + '/pico-sdk/src/rp2_common/hardware_resets/include',
cwd + '/pico-sdk/src/rp2_common/hardware_watchdog/include',
cwd + '/pico-sdk/src/rp2_common/hardware_xosc/include',
cwd + '/pico-sdk/src/rp2_common/hardware_pll/include',
cwd + '/pico-sdk/src/rp2_common/hardware_vreg/include',
cwd + '/pico-sdk/src/rp2_common/hardware_irq/include',
cwd + '/pico-sdk/src/rp2_common/pico_printf/include',
cwd + '/pico-sdk/src/rp2_common/pico_bootrom/include',
cwd + '/pico-sdk/src/common/pico_bit_ops/include',
cwd + '/pico-sdk/src/common/pico_divider/include',
cwd + '/pico-sdk/src/rp2_common/pico_double/include',
cwd + '/pico-sdk/src/rp2_common/pico_int64_ops/include',
cwd + '/pico-sdk/src/rp2_common/pico_float/include',
cwd + '/pico-sdk/src/common/pico_binary_info/include',
cwd + '/pico-sdk/src/rp2_common/pico_stdio/include',
cwd + '/pico-sdk/src/rp2_common/pico_stdio_uart/include',
cwd + '/generated/pico_base'
]
CPPDEFINES = [
'PICO_NO_BINARY_INFO',
'PICO_NO_PROGRAM_INFO',
'PICO_BIT_OPS_PICO=1',
'PICO_BUILD=1',
# 'PICO_CMAKE_BUILD_TYPE=\\"Release\\"',
'PICO_COPY_TO_RAM=0',
'PICO_CXX_ENABLE_EXCEPTIONS=0',
'PICO_DIVIDER_HARDWARE=1',
'PICO_DOUBLE_PICO=1',
'PICO_FLOAT_PICO=1',
'PICO_INT64_OPS_PICO=1',
'PICO_MEM_OPS_PICO=1',
'PICO_NO_FLASH=0',
'PICO_NO_HARDWARE=0',
'PICO_ON_DEVICE=1',
'PICO_PRINTF_PICO=1',
'PICO_STDIO_UART=1',
'PICO_USE_BLOCKED_RAM=0'
]
group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
Return('group')
// Padded and checksummed version of: /home/henson/Documents/rasp-pico/pico/pico-examples/build/pico_sdk/src/rp2_common/boot_stage2/bs2_default.bin
.section .boot2, "a"
.byte 0x00, 0xb5, 0x2f, 0x4b, 0x21, 0x20, 0x58, 0x60, 0x98, 0x68, 0x02, 0x21, 0x88, 0x43, 0x98, 0x60
.byte 0xd8, 0x60, 0x18, 0x61, 0x58, 0x61, 0x2b, 0x4b, 0x00, 0x21, 0x99, 0x60, 0x02, 0x21, 0x59, 0x61
.byte 0x01, 0x21, 0xf0, 0x22, 0x99, 0x50, 0x28, 0x49, 0x19, 0x60, 0x01, 0x21, 0x99, 0x60, 0x35, 0x20
.byte 0x00, 0xf0, 0x3e, 0xf8, 0x02, 0x22, 0x90, 0x42, 0x14, 0xd0, 0x06, 0x21, 0x19, 0x66, 0x00, 0xf0
.byte 0x2e, 0xf8, 0x19, 0x6e, 0x01, 0x21, 0x19, 0x66, 0x00, 0x20, 0x18, 0x66, 0x1a, 0x66, 0x00, 0xf0
.byte 0x26, 0xf8, 0x19, 0x6e, 0x19, 0x6e, 0x19, 0x6e, 0x05, 0x20, 0x00, 0xf0, 0x29, 0xf8, 0x01, 0x21
.byte 0x08, 0x42, 0xf9, 0xd1, 0x00, 0x21, 0x99, 0x60, 0x18, 0x49, 0x19, 0x60, 0x00, 0x21, 0x59, 0x60
.byte 0x17, 0x49, 0x18, 0x48, 0x01, 0x60, 0x01, 0x21, 0x99, 0x60, 0xeb, 0x21, 0x19, 0x66, 0xa0, 0x21
.byte 0x19, 0x66, 0x00, 0xf0, 0x0c, 0xf8, 0x00, 0x21, 0x99, 0x60, 0x13, 0x49, 0x11, 0x48, 0x01, 0x60
.byte 0x01, 0x21, 0x99, 0x60, 0x01, 0xbc, 0x00, 0x28, 0x00, 0xd1, 0x10, 0x48, 0x00, 0x47, 0x03, 0xb5
.byte 0x99, 0x6a, 0x04, 0x20, 0x01, 0x42, 0xfb, 0xd0, 0x01, 0x20, 0x01, 0x42, 0xf8, 0xd1, 0x03, 0xbd
.byte 0x02, 0xb5, 0x18, 0x66, 0x18, 0x66, 0xff, 0xf7, 0xf2, 0xff, 0x18, 0x6e, 0x18, 0x6e, 0x02, 0xbd
.byte 0x00, 0x00, 0x02, 0x40, 0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x07, 0x00, 0x00, 0x03, 0x5f, 0x00
.byte 0x21, 0x22, 0x00, 0x00, 0xf4, 0x00, 0x00, 0x18, 0x22, 0x20, 0x00, 0xa0, 0x01, 0x01, 0x00, 0x10
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
.byte 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3e, 0x27, 0x2a, 0x60
// AUTOGENERATED FROM PICO_CONFIG_HEADER_FILES and then PICO_<PLATFORM>_CONFIG_HEADER_FILES
// DO NOT EDIT!
// based on PICO_CONFIG_HEADER_FILES:
#include "boards/pico.h"
// based on PICO_RP2040_CONFIG_HEADER_FILES:
/*
* Copyright (c) 2020 Raspberry Pi (Trading) Ltd.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
// ---------------------------------------
// THIS FILE IS AUTOGENERATED; DO NOT EDIT
// ---------------------------------------
#ifndef _PICO_VERSION_H
#define _PICO_VERSION_H
#define PICO_SDK_VERSION_MAJOR 1
#define PICO_SDK_VERSION_MINOR 0
#define PICO_SDK_VERSION_REVISION 0
#define PICO_SDK_VERSION_STRING "1.0.0"
#endif
.idea
.vscode
cmake-*
.DS_Store
build
[submodule "tinyusb"]
path = lib/tinyusb
url = https://github.com/raspberrypi/tinyusb.git
branch = pico
cmake_minimum_required(VERSION 3.12)
if (NOT TARGET _pico_sdk_inclusion_marker)
add_library(_pico_sdk_inclusion_marker INTERFACE)
include(pico_sdk_init.cmake)
project(pico_sdk C CXX ASM)
if ("${CMAKE_BUILD_TYPE}" STREQUAL "Debug")
if (PICO_DEOPTIMIZED_DEBUG)
message("Using fully de-optimized debug build (set PICO_DEOPTIMIZED_DEBUG=0 to optimize)")
else()
message("Using regular optimized debug build (set PICO_DEOPTIMIZED_DEBUG=1 to de-optimize)")
endif()
endif()
pico_is_top_level_project(PICO_SDK_TOP_LEVEL_PROJECT)
set(CMAKE_C_STANDARD 11)
set(CMAKE_CXX_STANDARD 11)
if (NOT PICO_SDK_TOP_LEVEL_PROJECT)
set(PICO_SDK 1 PARENT_SCOPE)
endif()
# allow customization
add_sub_list_dirs(PICO_SDK_PRE_LIST_DIRS)
add_subdirectory(tools)
add_subdirectory(src)
add_compile_options(-Winline)
if (PICO_SDK_TOP_LEVEL_PROJECT AND NOT DEFINED PICO_SDK_TESTS_ENABLED)
set(PICO_SDK_TESTS_ENABLED 1)
endif()
if (PICO_SDK_TESTS_ENABLED)
add_subdirectory(test)
endif ()
set(PICO_SDK_TESTS_ENABLED "${PICO_SDK_TESTS_ENABLED}" CACHE INTERNAL "Enable build of SDK tests")
# allow customization
add_sub_list_dirs(PICO_SDK_POST_LIST_DIRS)
# add docs at the end, as we gather documentation dirs as we go
add_subdirectory(docs)
endif()
Copyright 2020 (c) 2020 Raspberry Pi (Trading) Ltd.
Redistribution and use in source and binary forms, with or without modification, are permitted provided that the
following conditions are met:
1. Redistributions of source code must retain the above copyright notice, this list of conditions and the following
disclaimer.
2. Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following
disclaimer in the documentation and/or other materials provided with the distribution.
3. Neither the name of the copyright holder nor the names of its contributors may be used to endorse or promote products
derived from this software without specific prior written permission.
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
\ No newline at end of file
# Pico SDK
The Pico SDK provides the headers, libraries and build system
necessary to write programs for the RP2040 based devices such as the Raspberry Pi Pico
in C, C++ or assembly language.
The Pico SDK is designed to provide an API and programming environment that is familiar both to non-embedded C developers and embedded C developers alike.
A single program runs on the device at a time and starts with a conventional `main()` method. Standard C/C++ libraries are supported along with
C level libraries/APIs for accessing all of the RP2040's hardware include PIO (Programmable IO)
Additionally the Pico SDK provides higher level libraries for dealing with timers, synchronization, USB (TinyUSB) and multi-core programming
along with various utilities.
The Pico SDK can be used to build anything from simple applications, full fledged runtime environments such as MicroPython, to low level software
such as RP2040's on chip bootrom itself.
Additional libraries/APIs that are not yet ready for inclusion in the Pico SDK can be found in [pico-extras](https://github.com/raspberrypi/pico-extras).
# Documentation
See [Getting Started with the Raspberry Pi Pico](https://rptl.io/pico-get-started) for information on how to setup your
hardware, IDE/environment and for how to build and debug software for the Raspberry Pi Pico
and other RP2040 based devices.
See [Pico C/C++ SDK](https://rptl.io/pico-c-sdk) to learn more about programming using the
Pico SDK, exploring more advanced features, and complete PDF based API documentation.
See [Online Pico SDK API docs](https://rptl.io/pico-doxygen) for HTML based API documentation.
# Example code
See [pico-examples](https://github.com/raspberrypi/pico-examples) for example code you can build.
# Quick-start your own project
These instructions are exteremly terse, and Linux based only. For detailed steps,
instructions for other platforms, and just in general, we recommend you see [Pico C/C++ SDK](https://rptl.io/pico-c-sdk)
1. Install CMake (at least version 3.12), and GCC cross compiler
```
sudo apt install cmake gcc-arm-none-eabi libnewlib-arm-none-eabi
```
1. Set up your project to point to use the Pico SDK
* By cloning the Pico SDK locally (most common)
1. `git clone` this Pico SDK repository
1. Copy [pico_sdk_import.cmake](https://github.com/raspberrypi/pico-sdk/blob/master/external/pico_sdk_import.cmake)
from the SDK into your project directory
2. Set `PICO_SDK_PATH` to the SDK location in your environment, or pass it (`-DPICO_SDK_PATH=`) to cmake later.
3. Setup a `CMakeLists.txt` like:
```cmake
cmake_minimum_required(VERSION 3.12)
# initialize the SDK based on PICO_SDK_PATH
# note: this must happen before project()
include(pico_sdk_import.cmake)
project(my_project)
# initialize the Pico SDK
pico_sdk_init()
# rest of your project
```
* With Pico SDK as a submodule
1. Clone the SDK as a submodule called `pico-sdk`
1. Setup a `CMakeLists.txt` like:
```cmake
cmake_minimum_required(VERSION 3.12)
# initialize pico_sdk from submodule
# note: this must happen before project()
include(pico-sdk/pico_sdk_init.cmake)
project(my_project)
# initialize the Pico SDK
pico_sdk_init()
# rest of your project
```
* With automatic download from github
1. Copy [pico_sdk_import.cmake](https://github.com/raspberrypi/pico-sdk/blob/master/external/pico_sdk_import.cmake)
from the SDK into your project directory
1. Setup a `CMakeLists.txt` like:
```cmake
cmake_minimum_required(VERSION 3.12)
# initialize pico_sdk from GIT
# (note this can come from environment, CMake cache etc)
set(PICO_SDK_FETCH_FROM_GIT on)
# pico_sdk_import.cmake is a single file copied from this SDK
# note: this must happen before project()
include(pico_sdk_import.cmake)
project(my_project)
# initialize the Pico SDK
pico_sdk_init()
# rest of your project
```
3. Setup a CMake build directory.
For example, if not using an IDE:
```
$ mkdir build
$ cd build
$ cmake ..
```
4. Write your code (see [pico-examples](https://github.com/raspberrypi/pico-examples) or the [Pico C/C++ SDK](https://rptl.io/pico-c-sdk) documentation
for more information)
About the simplest you can do is a single source file (e.g. hello_world.c)
```c
#include <stdio.h>
#include "pico/stdlib.h"
int main() {
setup_default_uart();
printf("Hello, world!\n");
return 0;
}
```
And add the following to your `CMakeLists.txt`:
```cmake
add_executable(hello_world
hello_world.c
)
# Add pico_stdlib library which aggregates commonly used features
target_link_libraries(hello_world pico_stdlib)
# create map/bin/hex/uf2 file in addition to ELF.
pico_add_extra_outputs(hello_world)
```
Note this example uses the default UART for _stdout_;
if you want ot use the default USB see the [hello-usb](https://github.com/raspberrypi/pico-examples/tree/master/hello_world/usb) example.
5. Make your target from the build directory you created.
```sh
$ make hello_world
```
6. You now have `hello_world.elf` to load via a debugger, or `hello_world.uf2` that can be installed and
run on your Raspberry Pi Pico via drag and drop.
# this is included because toolchain file sets SYSTEM_NAME=PICO
set_property(GLOBAL PROPERTY TARGET_SUPPORTS_SHARED_LIBS FALSE)
set(CMAKE_EXECUTABLE_SUFFIX .elf)
\ No newline at end of file
# PICO_CMAKE_CONFIG: PICO_PLATFORM, platform to build for e.g. rp2040/host, default=rp2040 or environment value, group=build
if (DEFINED ENV{PICO_PLATFORM} AND (NOT PICO_PLATFORM))
set(PICO_PLATFORM $ENV{PICO_PLATFORM})
message("Using PICO_PLATFORM from environment ('${PICO_PLATFORM}')")
else()
if (NOT PICO_PLATFORM)
set(PICO_PLATFORM "rp2040")
pico_message("Defaulting PICO_PLATFORM to ${PICO_PLATFORM} since not specified.")
else()
message("PICO platform is ${PICO_PLATFORM}.")
endif()
endif ()
set(PICO_PLATFORM ${PICO_PLATFORM} CACHE STRING "PICO Build platform (e.g. rp2040, host)")
# PICO_CMAKE_CONFIG: PICO_CMAKE_RELOAD_PLATFORM_FILE, custom CMake file to use to set up the platform environment, default=none, group=build
set(PICO_CMAKE_PRELOAD_PLATFORM_FILE "" CACHE INTERNAL "")
set(PICO_CMAKE_PRELOAD_PLATFORM_DIR "${CMAKE_CURRENT_LIST_DIR}/preload/platforms" CACHE INTERNAL "")
if (NOT PICO_CMAKE_PRELOAD_PLATFORM_FILE)
set(PICO_CMAKE_PRELOAD_PLATFORM_FILE ${PICO_CMAKE_PRELOAD_PLATFORM_DIR}/${PICO_PLATFORM}.cmake CACHE INTERNAL "")
endif ()
if (NOT EXISTS "${PICO_CMAKE_PRELOAD_PLATFORM_FILE}")
message(FATAL_ERROR "${PICO_CMAKE_PRELOAD_PLATFORM_FILE} does not exist. \
Either specify a valid PICO_PLATFORM (or PICO_CMAKE_PRELOAD_PLATFORM_FILE).")
endif ()
include(${PICO_CMAKE_PRELOAD_PLATFORM_FILE})
# PICO_CMAKE_CONFIG: PICO_TOOLCHAIN_PATH, Path to search for compiler, default=none (i.e. search system paths), group=build
# Set your compiler path here if it's not in the PATH environment variable.
set(PICO_TOOLCHAIN_PATH "" CACHE INTERNAL "")
# Set a default build type if none was specified
set(default_build_type "Release")
if(NOT CMAKE_BUILD_TYPE AND NOT CMAKE_CONFIGURATION_TYPES)
message(STATUS "Defaulting build type to '${default_build_type}' since not specified.")
set(CMAKE_BUILD_TYPE "${default_build_type}" CACHE STRING "Choose the type of build, options are: 'Debug', 'Release', 'MinSizeRel', 'RelWithDebInfo'." FORCE)
# Set the possible values of build type for cmake-gui
set_property(CACHE CMAKE_BUILD_TYPE PROPERTY STRINGS
"Debug" "Release" "MinSizeRel" "RelWithDebInfo")
endif()
if (CMAKE_BUILD_TYPE STREQUAL "Default")
error("Default build type is NOT supported")
endif()
# PICO_CMAKE_CONFIG: PICO_COMPILER, Optionally specifies a different compiler (other than pico_arm_gcc.cmake) - this is not yet fully supported, default=none, group=build
# If PICO_COMPILER is specified, set toolchain file to ${PICO_COMPILER}.cmake.
if (DEFINED PICO_COMPILER)
if (DEFINED CMAKE_TOOLCHAIN_FILE)
get_filename_component(toolchain "${CMAKE_TOOLCHAIN_FILE}" NAME_WE)
if (NOT "${PICO_COMPILER}" STREQUAL "${toolchain}")
message(WARNING "CMAKE_TOOLCHAIN_FILE is already defined to ${toolchain}.cmake, you\
need to delete cache and reconfigure if you want to switch compiler.")
endif ()
else ()
set(toolchain_dir "${CMAKE_CURRENT_LIST_DIR}/preload/toolchains")
set(toolchain_file "${toolchain_dir}/${PICO_COMPILER}.cmake")
if (EXISTS "${toolchain_file}")
set(CMAKE_TOOLCHAIN_FILE "${toolchain_file}" CACHE INTERNAL "")
else ()
# todo improve message
message(FATAL_ERROR "Toolchain file \"${PICO_COMPILER}.cmake\" does not exist, please\
select one from \"cmake/toolchains\" folder.")
endif ()
endif ()
endif ()
message("PICO compiler is ${PICO_COMPILER}")
unset(PICO_COMPILER CACHE)
function(pico_message param)
if (${ARGC} EQUAL 1)
message("${param}")
return()
endif ()
if (NOT ${ARGC} EQUAL 2)
message(FATAL_ERROR "Expect at most 2 arguments")
endif ()
message("${param}" "${ARGV1}")
endfunction()
macro(assert VAR MSG)
if (NOT ${VAR})
message(FATAL_ERROR "${MSG}")
endif ()
endmacro()
function(pico_find_in_paths OUT PATHS NAME)
foreach(PATH IN LISTS ${PATHS})
if (EXISTS ${PATH}/${NAME})
get_filename_component(FULLNAME ${PATH}/${NAME} ABSOLUTE)
set(${OUT} ${FULLNAME} PARENT_SCOPE)
return()
endif()
endforeach()
set(${OUT} "" PARENT_SCOPE)
endfunction()
\ No newline at end of file
if (NOT (DEFINED PICO_COMPILER OR DEFINED CMAKE_TOOLCHAIN_FILE))
pico_message("Defaulting PICO platform compiler to pico_arm_gcc since not specified.")
set(PICO_COMPILER "pico_arm_gcc")
endif ()
include(${CMAKE_CURRENT_LIST_DIR}/pico/pico.cmake)
\ No newline at end of file
# Toolchain file is processed multiple times, however, it cannot access CMake cache on some runs.
# We store the search path in an environment variable so that we can always access it.
if (NOT "${PICO_TOOLCHAIN_PATH}" STREQUAL "")
set(ENV{PICO_TOOLCHAIN_PATH} "${PICO_TOOLCHAIN_PATH}")
endif ()
# Find the compiler executable and store its path in a cache entry ${compiler_path}.
# If not found, issue a fatal message and stop processing. PICO_TOOLCHAIN_PATH can be provided from
# commandline as additional search path.
function(pico_find_compiler compiler_path compiler_exe)
# Search user provided path first.
find_program(
${compiler_path} ${compiler_exe}
PATHS ENV PICO_TOOLCHAIN_PATH
PATH_SUFFIXES bin
NO_DEFAULT_PATH
)
# If not then search system paths.
if ("${${compiler_path}}" STREQUAL "${compiler_path}-NOTFOUND")
if (DEFINED ENV{PICO_TOOLCHAIN_PATH})
message(WARNING "PICO_TOOLCHAIN_PATH specified ($ENV{PICO_TOOLCHAIN_PATH}), but ${compiler_exe} not found there")
endif()
find_program(${compiler_path} ${compiler_exe})
endif ()
if ("${${compiler_path}}" STREQUAL "${compiler_path}-NOTFOUND")
set(PICO_TOOLCHAIN_PATH "" CACHE PATH "Path to search for compiler.")
message(FATAL_ERROR "Compiler '${compiler_exe}' not found, you can specify search path with\
\"PICO_TOOLCHAIN_PATH\".")
endif ()
endfunction()
# NOTE: THIS IS A WIP ONLY PICO_ARM_GCC IS CURRENTLY SUPPORTED
# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform
# i.e. CMake<Lang>Information and whatnot
include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake)
# include our Platform/pico.cmake
set(CMAKE_SYSTEM_NAME PICO)
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus)
# Find CLANG
pico_find_compiler(PICO_COMPILER_CC clang)
pico_find_compiler(PICO_COMPILER_CXX clang)
#pico_find_compiler(PICO_COMPILER_ASM armasm)
set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "")
pico_find_compiler(PICO_OBJCOPY llvm-objcopy)
pico_find_compiler(PICO_OBJDUMP llvm-objdump)
# Specify the cross compiler.
set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler")
set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler")
set(CMAKE_C_OUTPUT_EXTENSION .o)
# todo should we be including CMakeASMInformation anyway - i guess that is host side
set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler")
set(CMAKE_ASM_COMPILE_OBJECT "<CMAKE_ASM_COMPILER> <DEFINES> <INCLUDES> <FLAGS> -o <OBJECT> -c <SOURCE>")
set(CMAKE_INCLUDE_FLAG_ASM "-I")
set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "")
set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "")
# Disable compiler checks.
set(CMAKE_C_COMPILER_FORCED TRUE)
set(CMAKE_CXX_COMPILER_FORCED TRUE)
# Add target system root to cmake find path.
get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY)
get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY)
# Look for includes and libraries only in the target system prefix.
set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
include_directories(/usr/include/newlib)
# todo move to platform/Generix-xxx
set(ARM_CLANG_COMMON_FLAGS " --target=arm-none-eabi -mcpu=cortex-m0plus -mthumb")
set(CMAKE_C_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
set(CMAKE_CXX_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
set(CMAKE_ASM_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
set(CMAKE_C_FLAGS_DEBUG_INIT "${ARM_CLANG_COMMON_FLAGS} -Og")
set(CMAKE_CXX_FLAGS_DEBUG_INIT "${ARM_CLANG_COMMON_FLAGS} -Og")
# NOTE: THIS IS A WIP ONLY PICO_ARM_GCC IS CURRENTLY SUPPORTED
# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform
# i.e. CMake<Lang>Information and whatnot
include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake)
# include our Platform/PICO.cmake
set(CMAKE_SYSTEM_NAME PICO)
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus)
# Find ARMClang.
pico_find_compiler(PICO_COMPILER_CC armclang)
pico_find_compiler(PICO_COMPILER_CXX armclang)
pico_find_compiler(PICO_COMPILER_ASM armasm)
set(PICO_COMPILER_ASM "${PICO_COMPILER_ASM}" CACHE INTERNAL "")
pico_find_compiler(PICO_OBJCOPY llvm-objcopy)
pico_find_compiler(PICO_OBJDUMP llvm-objdump)
# Specify the cross compiler.
set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler")
set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler")
set(CMAKE_C_OUTPUT_EXTENSION .o)
# todo should we be including CMakeASMInformation anyway - i guess that is host side
set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler")
set(CMAKE_ASM_COMPILE_OBJECT "<CMAKE_ASM_COMPILER> <DEFINES> <INCLUDES> <FLAGS> -o <OBJECT> -c <SOURCE>")
set(CMAKE_INCLUDE_FLAG_ASM "-I")
set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "")
set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "")
# Disable compiler checks.
set(CMAKE_C_COMPILER_FORCED TRUE)
set(CMAKE_CXX_COMPILER_FORCED TRUE)
# Add target system root to cmake find path.
get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY)
get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY)
# Look for includes and libraries only in the target system prefix.
set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
# todo move to platform/Generix-xxx
set(ARM_CLANG_COMMON_FLAGS " --cpu=Cortex-M0plus")
string(APPEND CMAKE_C_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
string(APPEND CMAKE_CXX_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
string(APPEND CMAKE_ASM_FLAGS_INIT "${ARM_CLANG_COMMON_FLAGS}")
string(APPEND CMAKE_C_FLAGS_DEBUG_INIT "${ARM_CLANG_COMMON_FLAGS} -Og")
string(APPEND CMAKE_CXX_FLAGS_DEBUG_INIT "${ARM_CLANG_COMMON_FLAGS} -Og")
# todo there is probably a more "cmake" way of doing this going thru the standard path with our "PICO" platform
# i.e. CMake<Lang>Information and whatnot
include(${CMAKE_CURRENT_LIST_DIR}/find_compiler.cmake)
# include our Platform/PICO.cmake
set(CMAKE_SYSTEM_NAME PICO)
set(CMAKE_SYSTEM_PROCESSOR cortex-m0plus)
if (NOT PICO_GCC_TRIPLE)
if (DEFINED ENV{PICO_GCC_TRIPLE})
set(PICO_GCC_TRIPLE $ENV{PICO_GCC_TRIPLE})
message("PICO_GCC_TRIPLE set from environment: $ENV{PICO_GCC_TRIPLE}")
else()
set(PICO_GCC_TRIPLE arm-none-eabi)
message("PICO_GCC_TRIPLE defaulted to arm-none-eabi")
endif()
endif()
# Find GCC for ARM.
pico_find_compiler(PICO_COMPILER_CC ${PICO_GCC_TRIPLE}-gcc)
pico_find_compiler(PICO_COMPILER_CXX ${PICO_GCC_TRIPLE}-g++)
set(PICO_COMPILER_ASM "${PICO_COMPILER_CC}" CACHE INTERNAL "")
pico_find_compiler(PICO_OBJCOPY ${PICO_GCC_TRIPLE}-objcopy)
pico_find_compiler(PICO_OBJDUMP ${PICO_GCC_TRIPLE}-objdump)
# Specify the cross compiler.
set(CMAKE_C_COMPILER ${PICO_COMPILER_CC} CACHE FILEPATH "C compiler")
set(CMAKE_CXX_COMPILER ${PICO_COMPILER_CXX} CACHE FILEPATH "C++ compiler")
set(CMAKE_C_OUTPUT_EXTENSION .o)
# todo should we be including CMakeASMInformation anyway - i guess that is host side
set(CMAKE_ASM_COMPILER ${PICO_COMPILER_ASM} CACHE FILEPATH "ASM compiler")
set(CMAKE_ASM_COMPILE_OBJECT "<CMAKE_ASM_COMPILER> <DEFINES> <INCLUDES> <FLAGS> -o <OBJECT> -c <SOURCE>")
set(CMAKE_INCLUDE_FLAG_ASM "-I")
set(CMAKE_OBJCOPY ${PICO_OBJCOPY} CACHE FILEPATH "")
set(CMAKE_OBJDUMP ${PICO_OBJDUMP} CACHE FILEPATH "")
# Disable compiler checks.
set(CMAKE_C_COMPILER_FORCED TRUE)
set(CMAKE_CXX_COMPILER_FORCED TRUE)
# Add target system root to cmake find path.
get_filename_component(PICO_COMPILER_DIR "${PICO_COMPILER_CC}" DIRECTORY)
get_filename_component(CMAKE_FIND_ROOT_PATH "${PICO_COMPILER_DIR}" DIRECTORY)
# Look for includes and libraries only in the target system prefix.
set(CMAKE_FIND_ROOT_PATH_MODE_INCLUDE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_LIBRARY ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PACKAGE ONLY)
set(CMAKE_FIND_ROOT_PATH_MODE_PROGRAM NEVER)
option(PICO_DEOPTIMIZED_DEBUG "Build debug builds with -O0" 0)
# todo move to platform/Generix-xxx
set(ARM_GCC_COMMON_FLAGS " -march=armv6-m -mcpu=cortex-m0plus -mthumb")
#set(ARM_GCC_COMMON_FLAGS " -mcpu=cortex-m0plus -mthumb")
foreach(LANG IN ITEMS C CXX ASM)
set(CMAKE_${LANG}_FLAGS_INIT "${ARM_GCC_COMMON_FLAGS}")
if (PICO_DEOPTIMIZED_DEBUG)
set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-O0")
else()
set(CMAKE_${LANG}_FLAGS_DEBUG_INIT "-Og")
endif()
set(CMAKE_${LANG}_LINK_FLAGS "-Wl,--build-id=none")
endforeach()
find_package(Doxygen)
if (PICO_SDK_TOP_LEVEL_PROJECT AND ${DOXYGEN_FOUND})
set(PICO_BUILD_DOCS_DEFAULT 1)
endif()
option(PICO_BUILD_DOCS "Build HTML Doxygen docs" ${PICO_BUILD_DOCS_DEFAULT})
if (DEFINED ENV{PICO_EXAMPLES_PATH} AND NOT PICO_EXAMPLES_PATH)
set(PICO_EXAMPLES_PATH $ENV{PICO_EXAMPLES_PATH})
message("Using PICO_EXAMPLES_PATH from environment ('${PICO_EXAMPLES_PATH}')")
endif()
if(PICO_BUILD_DOCS)
if(NOT DOXYGEN_FOUND)
message(FATAL_ERROR "Doxygen is needed to build the documentation.")
endif()
include(ExternalProject)
if(PICO_EXAMPLES_PATH)
get_filename_component(PICO_EXAMPLES_PATH "${PICO_EXAMPLES_PATH}" REALPATH BASE_DIR "${CMAKE_BINARY_DIR}")
if (EXISTS ${PICO_EXAMPLES_PATH})
message("Documentation example code will come from ${PICO_EXAMPLES_PATH}")
else()
message(WARNING "Documentation example code configured to come from ${PICO_EXAMPLES_PATH}, but that path does not exist")
endif()
add_custom_target(doc-pico-examples)
else()
ExternalProject_Add(doc-pico-examples
GIT_REPOSITORY git@github.com:raspberrypi/pico-examples.git
GIT_TAG master
CONFIGURE_COMMAND ""
BUILD_COMMAND ""
INSTALL_COMMAND ""
)
ExternalProject_Get_property(doc-pico-examples SOURCE_DIR)
ExternalProject_Get_property(doc-pico-examples GIT_REPOSITORY)
ExternalProject_Get_property(doc-pico-examples GIT_TAG)
set(PICO_EXAMPLES_PATH ${SOURCE_DIR})
message("Documentation example code will come from git repo ${GIT_REPOSITORY}, branch ${GIT_TAG}")
endif()
set(DOXY_OUTPUT_DIR "${CMAKE_CURRENT_BINARY_DIR}/doxygen")
set(DOXY_INPUT_DIRS "${PICO_DOXYGEN_PATHS}")
set(DOXY_EXCLUDE_DIRS "${PICO_DOXYGEN_EXCLUDE_PATHS}")
set(DOXY_EXAMPLE_DIR "${PICO_EXAMPLES_PATH}")
set(doxyfile_in ${CMAKE_CURRENT_SOURCE_DIR}/Doxyfile.in)
set(doxyfile ${CMAKE_CURRENT_BINARY_DIR}/Doxyfile)
configure_file(${doxyfile_in} ${doxyfile} @ONLY)
add_custom_target(docs
COMMAND ${DOXYGEN_EXECUTABLE} ${doxyfile}
WORKING_DIRECTORY ${CMAKE_CURRENT_BINARY_DIR}
COMMENT "Generating API documentation with Doxygen"
VERBATIM)
add_dependencies(docs doc-pico-examples)
endif()
PROJECT_NAME = "Pico SDK"
PROJECT_NUMBER = @VERSION_MAJOR@.@VERSION_MINOR@.@VERSION_PATCH@
#STRIP_FROM_PATH = @PROJECT_SOURCE_DIR@
STRIP_FROM_PATH = @DOXY_INPUT_DIRS@
# @PROJECT_BINARY_DIR@
#INPUT = @doxy_main_page@ \
# @PROJECT_SOURCE_DIR@ \
# @PROJECT_BINARY_DIR@
FILE_PATTERNS = *.h \
*.cpp \
*.c \
*.S \
*.s \
*.md
USE_MDFILE_AS_MAINPAGE = @PROJECT_SOURCE_DIR@/docs/mainpage.md
LAYOUT_FILE = @PROJECT_SOURCE_DIR@/docs/DoxygenLayout.xml
HTML_FOOTER = @PROJECT_SOURCE_DIR@/docs/footer.html
HTML_HEADER = @PROJECT_SOURCE_DIR@/docs/header.html
PROJECT_BRIEF = "Pico SDK documentation"
PROJECT_NUMBER = 1.0
OPTIMIZE_OUTPUT_FOR_C = YES
# HTML_EXTRA_STYLESHEET = @PROJECT_SOURCE_DIR@/docs/customdoxygen.css
HTML_EXTRA_STYLESHEET = @PROJECT_SOURCE_DIR@/docs/normalise.css @PROJECT_SOURCE_DIR@/docs/main.css @PROJECT_SOURCE_DIR@/docs/styles.css
HTML_EXTRA_FILES = @PROJECT_SOURCE_DIR@/docs/logo-mobile.svg @PROJECT_SOURCE_DIR@/docs/logo.svg @PROJECT_SOURCE_DIR@/docs/search.svg \
@PROJECT_SOURCE_DIR@/docs/main.js @PROJECT_SOURCE_DIR@/docs/pico.jpg @PROJECT_SOURCE_DIR@/docs/rp2040.png
GENERATE_TREEVIEW = YES # This is needed as it wraps the content area in an HTML tag that we need to use
HTML_COLORSTYLE_HUE = 350
HTML_COLORSTYLE_SAT = 200
HTML_COLORSTYLE_GAMMA = 150
GENERATE_LATEX = NO
GENERATE_XML = YES
GROUP_GRAPHS = NO
ALIASES += tag=@internal
ALIASES += end=@internal
OUTPUT_DIRECTORY = @DOXY_OUTPUT_DIR@
INPUT = @PROJECT_SOURCE_DIR@/docs/index.h @DOXY_INPUT_DIRS@ @PROJECT_SOURCE_DIR@/docs/
#EXCLUDE = @DOXY_EXCLUDE_DIRS@ @PROJECT_SOURCE_DIR@/src/rp2040
EXCLUDE = @DOXY_EXCLUDE_DIRS@
RECURSIVE = YES
EXAMPLE_PATH = @PICO_EXAMPLES_PATH@
# This is needed as we have a number of static inline functions that need to be documented.
EXTRACT_STATIC = YES
EXTRACT_ALL = NO
ALWAYS_DETAILED_SEC = NO
#REPEAT_BRIEF = NO
# Need these next options to ensure that functions with modifiers do not confuse the Doxygen parser.
# And any further function modifiers here.
MACRO_EXPANSION = YES
PREDEFINED = __not_in_flash_func(x) \
__time_critical_func(x) \
__not_in_flash(x)= \
__no_inline_not_in_flash(x)= \
__attribute__(x)=
## Examples Index {#examples_page}
This page links to the various example code fragments in this documentation. For more complete examples, please see the pico_examples repository, which contains complete buildable projects.
- [RTC example](@ref rtc_example)
- [UART example](@ref uart_example)
- [ADC example](@ref adc_example)
- [I2C example](@ref i2c_example)
- [Clock example](@ref clock_example)
- [Timer example](@ref timer_example)
- [Flash programming example](@ref flash_example)
- [Watchdog example](@ref watchdog_example)
- [Divider example](@ref divider_example)
- [PWM example](@ref pwm_example)
- [Multicore example](@ref multicore_example)
- [Reset example](@ref reset_example)
All examples are "Copyright (c) 2020 Raspberry Pi (Trading) Ltd", and are released under a 3-Clause BSD licence. Briefly, this means you are free to use the example code
as long as you retain the copyright notice. Full details on the licence can be found [here](https://opensource.org/licenses/BSD-3-Clause).
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<?xml version="1.0" encoding="UTF-8"?><svg xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink" version="1.1" id="Layer_1" x="0px" y="0px" viewBox="0 0 29 29" xml:space="preserve"><style type="text/css">.st0{fill:none;stroke:#000000;stroke-width:2;stroke-miterlimit:10;} .st1{fill:none;stroke:#000000;stroke-width:2;stroke-linecap:round;stroke-linejoin:round;stroke-miterlimit:10;} .st2{fill:none;stroke:#000000;stroke-miterlimit:10;} .st3{fill:none;stroke:#000000;stroke-width:2;stroke-miterlimit:10;stroke-dasharray:1.7411,1.7411;} .st4{fill:none;stroke:#000000;stroke-width:2;stroke-linecap:round;stroke-linejoin:round;stroke-dasharray:2.0261,4.0522;}</style><circle class="st0" cx="11.854" cy="11.854" r="9" fill="none" stroke="#000" stroke-miterlimit="10" stroke-width="2"/><path class="st1" fill="none" stroke="#000" stroke-linecap="round" stroke-linejoin="round" stroke-miterlimit="10" stroke-width="2" d="M18.451 18.451l7.695 7.695"/><metadata><rdf:RDF xmlns:rdf="http://www.w3.org/1999/02/22-rdf-syntax-ns#" xmlns:rdfs="http://www.w3.org/2000/01/rdf-schema#" xmlns:dc="http://purl.org/dc/elements/1.1/"><rdf:Description about="https://iconscout.com/legal#licenses" dc:title="search,find,magnifier,glass,magnify" dc:description="search,find,magnifier,glass,magnify" dc:publisher="Iconscout" dc:date="2017-10-04" dc:format="image/svg+xml" dc:language="en"><dc:creator><rdf:Bag><rdf:li>Jemis Mali</rdf:li></rdf:Bag></dc:creator></rdf:Description></rdf:RDF></metadata></svg>
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