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体验新版 GitCode,发现更多精彩内容 >>
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3cf0f341
编写于
9月 12, 2019
作者:
z13955633063
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浏览文件
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电子邮件补丁
差异文件
[bsp][stm32][libraries]删除冲突的spi库文件,修正stm32f1系列的uuid读取函数
上级
900cc4b1
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
1 addition
and
235 deletion
+1
-235
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
+1
-3
bsp/stm32/libraries/STM32F1xx_HAL/SConscript
bsp/stm32/libraries/STM32F1xx_HAL/SConscript
+0
-1
bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c
...2F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c
+0
-231
未找到文件。
bsp/stm32/libraries/HAL_Drivers/drv_crypto.c
浏览文件 @
3cf0f341
...
...
@@ -300,11 +300,9 @@ int stm32_hw_crypto_device_init(void)
_crypto_dev
.
dev
.
ops
=
&
_ops
;
#if defined(BSP_USING_UDID)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F
4) || defined(SOC_SERIES_STM32F0
) || defined(SOC_SERIES_STM32F7)
#if defined(SOC_SERIES_STM32L4) || defined(SOC_SERIES_STM32F
0) || defined(SOC_SERIES_STM32F1) || defined(SOC_SERIES_STM32F4
) || defined(SOC_SERIES_STM32F7)
cpuid
[
0
]
=
HAL_GetUIDw0
();
cpuid
[
1
]
=
HAL_GetUIDw1
();
#elif defined(SOC_SERIES_STM32F1)
HAL_GetUID
(
cpuid
);
#elif defined(SOC_SERIES_STM32H7)
cpuid
[
0
]
=
HAL_GetREVID
();
cpuid
[
1
]
=
HAL_GetDEVID
();
...
...
bsp/stm32/libraries/STM32F1xx_HAL/SConscript
浏览文件 @
3cf0f341
...
...
@@ -32,7 +32,6 @@ if GetDepend(['RT_USING_I2C']):
if
GetDepend
([
'RT_USING_SPI'
]):
src
+=
[
'STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi.c'
]
src
+=
[
'STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c'
]
src
+=
[
'STM32F1xx_HAL_Driver/Src/stm32f1xx_ll_spi.c'
]
if
GetDepend
([
'RT_USING_USB_HOST'
])
or
GetDepend
([
'RT_USING_USB_DEVICE'
]):
...
...
bsp/stm32/libraries/STM32F1xx_HAL/STM32F1xx_HAL_Driver/Src/stm32f1xx_hal_spi_ex.c
已删除
100644 → 0
浏览文件 @
900cc4b1
/**
******************************************************************************
* @file stm32f1xx_hal_spi_ex.c
* @author MCD Application Team
* @brief Extended SPI HAL module driver.
*
* This file provides firmware functions to manage the following
* functionalities SPI extension peripheral:
* + Extended Peripheral Control functions
*
******************************************************************************
* @attention
*
* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
* 1. Redistributions of source code must retain the above copyright notice,
* this list of conditions and the following disclaimer.
* 2. Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
* 3. Neither the name of STMicroelectronics nor the names of its contributors
* may be used to endorse or promote products derived from this software
* without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
#include "stm32f1xx_hal.h"
/** @addtogroup STM32F1xx_HAL_Driver
* @{
*/
/** @addtogroup SPI
* @{
*/
#ifdef HAL_SPI_MODULE_ENABLED
/** @defgroup SPI_Private_Variables SPI Private Variables
* @{
*/
#if (USE_SPI_CRC != 0U)
/* Variable used to determine if device is impacted by implementation of workaround
related to wrong CRC errors detection on SPI2. Conditions in which this workaround has to be applied, are:
- STM32F101CDE/STM32F103CDE
- Revision ID : Z
- SPI2
- In receive only mode, with CRC calculation enabled, at the end of the CRC reception,
the software needs to check the CRCERR flag. If it is found set, read back the SPI_RXCRC:
+ If the value is 0, the complete data transfer is successful.
+ Otherwise, one or more errors have been detected during the data transfer by CPU or DMA.
If CRCERR is found reset, the complete data transfer is considered successful.
*/
uint8_t
uCRCErrorWorkaroundCheck
=
0U
;
#endif
/* USE_SPI_CRC */
/**
* @}
*/
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @addtogroup SPI_Exported_Functions
* @{
*/
/** @addtogroup SPI_Exported_Functions_Group1
*
* @{
*/
/**
* @brief Initializes the SPI according to the specified parameters
* in the SPI_InitTypeDef and create the associated handle.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
HAL_StatusTypeDef
HAL_SPI_Init
(
SPI_HandleTypeDef
*
hspi
)
{
/* Check the SPI handle allocation */
if
(
hspi
==
NULL
)
{
return
HAL_ERROR
;
}
/* Check the parameters */
assert_param
(
IS_SPI_ALL_INSTANCE
(
hspi
->
Instance
));
assert_param
(
IS_SPI_MODE
(
hspi
->
Init
.
Mode
));
assert_param
(
IS_SPI_DIRECTION
(
hspi
->
Init
.
Direction
));
assert_param
(
IS_SPI_DATASIZE
(
hspi
->
Init
.
DataSize
));
assert_param
(
IS_SPI_CPOL
(
hspi
->
Init
.
CLKPolarity
));
assert_param
(
IS_SPI_CPHA
(
hspi
->
Init
.
CLKPhase
));
assert_param
(
IS_SPI_NSS
(
hspi
->
Init
.
NSS
));
assert_param
(
IS_SPI_BAUDRATE_PRESCALER
(
hspi
->
Init
.
BaudRatePrescaler
));
assert_param
(
IS_SPI_FIRST_BIT
(
hspi
->
Init
.
FirstBit
));
#if (USE_SPI_CRC != 0U)
assert_param
(
IS_SPI_CRC_CALCULATION
(
hspi
->
Init
.
CRCCalculation
));
if
(
hspi
->
Init
.
CRCCalculation
==
SPI_CRCCALCULATION_ENABLE
)
{
assert_param
(
IS_SPI_CRC_POLYNOMIAL
(
hspi
->
Init
.
CRCPolynomial
));
}
#else
hspi
->
Init
.
CRCCalculation
=
SPI_CRCCALCULATION_DISABLE
;
#endif
/* USE_SPI_CRC */
if
(
hspi
->
State
==
HAL_SPI_STATE_RESET
)
{
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_SPI_MspInit
(
hspi
);
}
hspi
->
State
=
HAL_SPI_STATE_BUSY
;
/* Disble the selected SPI peripheral */
__HAL_SPI_DISABLE
(
hspi
);
/*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
/* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
Communication speed, First bit and CRC calculation state */
WRITE_REG
(
hspi
->
Instance
->
CR1
,
(
hspi
->
Init
.
Mode
|
hspi
->
Init
.
Direction
|
hspi
->
Init
.
DataSize
|
hspi
->
Init
.
CLKPolarity
|
hspi
->
Init
.
CLKPhase
|
(
hspi
->
Init
.
NSS
&
SPI_CR1_SSM
)
|
hspi
->
Init
.
BaudRatePrescaler
|
hspi
->
Init
.
FirstBit
|
hspi
->
Init
.
CRCCalculation
)
);
/* Configure : NSS management */
WRITE_REG
(
hspi
->
Instance
->
CR2
,
(((
hspi
->
Init
.
NSS
>>
16U
)
&
SPI_CR2_SSOE
)
|
hspi
->
Init
.
TIMode
));
/*---------------------------- SPIx CRCPOLY Configuration ------------------*/
/* Configure : CRC Polynomial */
WRITE_REG
(
hspi
->
Instance
->
CRCPR
,
hspi
->
Init
.
CRCPolynomial
);
#if defined(SPI_I2SCFGR_I2SMOD)
/* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
CLEAR_BIT
(
hspi
->
Instance
->
I2SCFGR
,
SPI_I2SCFGR_I2SMOD
);
#endif
/* SPI_I2SCFGR_I2SMOD */
#if (USE_SPI_CRC != 0U)
#if defined (STM32F101xE) || defined (STM32F103xE)
/* Check RevisionID value for identifying if Device is Rev Z (0x0001) in order to enable workaround for
CRC errors wrongly detected */
/* Pb is that ES_STM32F10xxCDE also identify an issue in Debug registers access while not in Debug mode.
Revision ID information is only available in Debug mode, so Workaround could not be implemented
to distinguish Rev Z devices (issue present) from more recent version (issue fixed).
So, in case of Revison Z F101 or F103 devices, below variable should be assigned to 1 */
uCRCErrorWorkaroundCheck
=
0U
;
#else
uCRCErrorWorkaroundCheck
=
0U
;
#endif
/* STM32F101xE || STM32F103xE */
#endif
/* USE_SPI_CRC */
hspi
->
ErrorCode
=
HAL_SPI_ERROR_NONE
;
hspi
->
State
=
HAL_SPI_STATE_READY
;
return
HAL_OK
;
}
/**
* @}
*/
/**
* @}
*/
/** @addtogroup SPI_Private_Functions
* @{
*/
#if (USE_SPI_CRC != 0U)
/**
* @brief Checks if encountered CRC error could be corresponding to wrongly detected errors
* according to SPI instance, Device type, and revision ID.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval CRC error validity (SPI_INVALID_CRC_ERROR or SPI_VALID_CRC_ERROR).
*/
uint8_t
SPI_ISCRCErrorValid
(
SPI_HandleTypeDef
*
hspi
)
{
#if defined(STM32F101xE) || defined(STM32F103xE)
/* Check how to handle this CRC error (workaround to be applied or not) */
/* If CRC errors could be wrongly detected (issue 2.15.2 in STM32F10xxC/D/E silicon limitations ES (DocID14732 Rev 13) */
if
((
uCRCErrorWorkaroundCheck
!=
0U
)
&&
(
hspi
->
Instance
==
SPI2
))
{
if
(
hspi
->
Instance
->
RXCRCR
==
0U
)
{
return
(
SPI_INVALID_CRC_ERROR
);
}
}
return
(
SPI_VALID_CRC_ERROR
);
#else
/* Prevent unused argument(s) compilation warning */
UNUSED
(
hspi
);
return
(
SPI_VALID_CRC_ERROR
);
#endif
}
#endif
/* USE_SPI_CRC */
/**
* @}
*/
#endif
/* HAL_SPI_MODULE_ENABLED */
/**
* @}
*/
/**
* @}
*/
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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