1. 18 8月, 2023 1 次提交
  2. 14 8月, 2023 5 次提交
  3. 11 8月, 2023 2 次提交
  4. 09 8月, 2023 1 次提交
    • S
      feat: `riscv-interrupt-{m,s}` calling conventions · 897c7bb2
      Seth Pellegrino 提交于
      Similar to prior support added for the mips430, avr, and x86 targets
      this change implements the rough equivalent of clang's
      [`__attribute__((interrupt))`][clang-attr] for riscv targets, enabling
      e.g.
      
      ```rust
      static mut CNT: usize = 0;
      
      pub extern "riscv-interrupt-m" fn isr_m() {
          unsafe {
              CNT += 1;
          }
      }
      ```
      
      to produce highly effective assembly like:
      
      ```asm
      pub extern "riscv-interrupt-m" fn isr_m() {
      420003a0:       1141                    addi    sp,sp,-16
          unsafe {
              CNT += 1;
      420003a2:       c62a                    sw      a0,12(sp)
      420003a4:       c42e                    sw      a1,8(sp)
      420003a6:       3fc80537                lui     a0,0x3fc80
      420003aa:       63c52583                lw      a1,1596(a0) # 3fc8063c <_ZN12esp_riscv_rt3CNT17hcec3e3a214887d53E.0>
      420003ae:       0585                    addi    a1,a1,1
      420003b0:       62b52e23                sw      a1,1596(a0)
          }
      }
      420003b4:       4532                    lw      a0,12(sp)
      420003b6:       45a2                    lw      a1,8(sp)
      420003b8:       0141                    addi    sp,sp,16
      420003ba:       30200073                mret
      ```
      
      (disassembly via `riscv64-unknown-elf-objdump -C -S --disassemble ./esp32c3-hal/target/riscv32imc-unknown-none-elf/release/examples/gpio_interrupt`)
      
      This outcome is superior to hand-coded interrupt routines which, lacking
      visibility into any non-assembly body of the interrupt handler, have to
      be very conservative and save the [entire CPU state to the stack
      frame][full-frame-save]. By instead asking LLVM to only save the
      registers that it uses, we defer the decision to the tool with the best
      context: it can more accurately account for the cost of spills if it
      knows that every additional register used is already at the cost of an
      implicit spill.
      
      At the LLVM level, this is apparently [implemented by] marking every
      register as "[callee-save]," matching the semantics of an interrupt
      handler nicely (it has to leave the CPU state just as it found it after
      its `{m|s}ret`).
      
      This approach is not suitable for every interrupt handler, as it makes
      no attempt to e.g. save the state in a user-accessible stack frame. For
      a full discussion of those challenges and tradeoffs, please refer to
      [the interrupt calling conventions RFC][rfc].
      
      Inside rustc, this implementation differs from prior art because LLVM
      does not expose the "all-saved" function flavor as a calling convention
      directly, instead preferring to use an attribute that allows for
      differentiating between "machine-mode" and "superivsor-mode" interrupts.
      
      Finally, some effort has been made to guide those who may not yet be
      aware of the differences between machine-mode and supervisor-mode
      interrupts as to why no `riscv-interrupt` calling convention is exposed
      through rustc, and similarly for why `riscv-interrupt-u` makes no
      appearance (as it would complicate future LLVM upgrades).
      
      [clang-attr]: https://clang.llvm.org/docs/AttributeReference.html#interrupt-risc-v
      [full-frame-save]: https://github.com/esp-rs/esp-riscv-rt/blob/9281af2ecffe13e40992917316f36920c26acaf3/src/lib.rs#L440-L469
      [implemented by]: https://github.com/llvm/llvm-project/blob/b7fb2a3fec7c187d58a6d338ab512d9173bca987/llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp#L61-L67
      [callee-save]: https://github.com/llvm/llvm-project/blob/973f1fe7a8591c7af148e573491ab68cc15b6ecf/llvm/lib/Target/RISCV/RISCVCallingConv.td#L30-L37
      [rfc]: https://github.com/rust-lang/rfcs/pull/3246
      897c7bb2
  5. 08 8月, 2023 2 次提交
  6. 07 8月, 2023 1 次提交
  7. 05 8月, 2023 3 次提交
  8. 03 8月, 2023 1 次提交
    • N
      Add `internal_features` lint · 5830ca21
      Nilstrieb 提交于
      It lints against features that are inteded to be internal to the
      compiler and standard library. Implements MCP #596.
      
      We allow `internal_features` in the standard library and compiler as those
      use many features and this _is_ the standard library from the "internal to the compiler and
      standard library" after all.
      
      Marking some features as internal wasn't exactly the most scientific approach, I just marked some
      mostly obvious features. While there is a categorization in the macro,
      it's not very well upheld (should probably be fixed in another PR).
      
      We always pass `-Ainternal_features` in the testsuite
      About 400 UI tests and several other tests use internal features.
      Instead of throwing the attribute on each one, just always allow them.
      There's nothing wrong with testing internal features^^
      5830ca21
  9. 29 7月, 2023 1 次提交
  10. 27 7月, 2023 1 次提交
  11. 26 7月, 2023 1 次提交
  12. 25 7月, 2023 1 次提交
  13. 24 7月, 2023 7 次提交
  14. 22 7月, 2023 1 次提交
  15. 21 7月, 2023 2 次提交
  16. 18 7月, 2023 3 次提交
  17. 15 7月, 2023 1 次提交
  18. 11 7月, 2023 6 次提交