提交 185cc5f2 编写于 作者: B bors

Auto merge of #44885 - lu-zero:master, r=alexcrichton

More Altivec Intrinsics

Float-specific intrinsics
......@@ -219,6 +219,76 @@
"llvm": "vsumsws",
"ret": "s32",
"args": ["0", "0"]
},
{
"intrinsic": "madd",
"width": [128],
"llvm": "vmaddfp",
"ret": "f32",
"args": ["0", "0", "0"]
},
{
"intrinsic": "nmsub",
"width": [128],
"llvm": "vnmsubfp",
"ret": "f32",
"args": ["0", "0", "0"]
},
{
"intrinsic": "expte",
"width": [128],
"llvm": "vexptefp",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "floor",
"width": [128],
"llvm": "vrfim",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "ceil",
"width": [128],
"llvm": "vrfip",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "round",
"width": [128],
"llvm": "vrfin",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "trunc",
"width": [128],
"llvm": "vrfiz",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "loge",
"width": [128],
"llvm": "vlogefp",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "re",
"width": [128],
"llvm": "vrefp",
"ret": "f32",
"args": ["0"]
},
{
"intrinsic": "rsqrte",
"width": [128],
"llvm": "vrsqrtefp",
"ret": "f32",
"args": ["0"]
}
]
}
......@@ -397,6 +397,56 @@ pub fn find(name: &str) -> Option<Intrinsic> {
output: &::I32x4,
definition: Named("llvm.ppc.altivec.vsumsws")
},
"_vec_madd" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vmaddfp")
},
"_vec_nmsub" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 3] = [&::F32x4, &::F32x4, &::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vnmsubfp")
},
"_vec_expte" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vexptefp")
},
"_vec_floor" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrfim")
},
"_vec_ceil" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrfip")
},
"_vec_round" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrfin")
},
"_vec_trunc" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrfiz")
},
"_vec_loge" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vlogefp")
},
"_vec_re" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrefp")
},
"_vec_rsqrte" => Intrinsic {
inputs: { static INPUTS: [&'static Type; 1] = [&::F32x4]; &INPUTS },
output: &::F32x4,
definition: Named("llvm.ppc.altivec.vrsqrtefp")
},
_ => return None,
})
}
Markdown is supported
0% .
You are about to add 0 people to the discussion. Proceed with caution.
先完成此消息的编辑!
想要评论请 注册