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提交 cbd32a0c 编写于 作者: D dzzxzz@gmail.com
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upgrade MB9BF506 CMSIS to version 3.01 

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@2100 bbd45198-f89e-11dd-88c7-29a3b14d5316
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bsp/mb9bf506r/CMSIS/core_cm3.c 已删除 100644 → 0
浏览文件 @ 209da682
/**************************************************************************//**
* @file core_cm3.c
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Source File
* @version V1.40
* @date 18. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#include <stdint.h>
/* define compiler specific symbols */
#if defined ( __CC_ARM )
#define __ASM __asm /*!< asm keyword for ARM Compiler */
#define __INLINE __inline /*!< inline keyword for ARM Compiler */
#elif defined ( __ICCARM__ )
#define __ASM __asm /*!< asm keyword for IAR Compiler */
#define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
#elif defined ( __GNUC__ )
#define __ASM __asm /*!< asm keyword for GNU Compiler */
#define __INLINE inline /*!< inline keyword for GNU Compiler */
#elif defined ( __TASKING__ )
#define __ASM __asm /*!< asm keyword for TASKING Compiler */
#define __INLINE inline /*!< inline keyword for TASKING Compiler */
#endif
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
__ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
__ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __CLREX(void)
{
clrex
}
#endif /* __ARMCC_VERSION */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
/* ########################### Core Function Access ########################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/**
* @brief Return the Control Register value
*
* @return Control value
*
* Return the content of the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_CONTROL(void)
{
mrs r0, control
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Control Register value
*
* @param control Control value
*
* Set the control register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_CONTROL(uint32_t control)
{
msr control, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get IPSR Register value
*
* @return uint32_t IPSR value
*
* return the content of the IPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_IPSR(void)
{
mrs r0, ipsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get APSR Register value
*
* @return uint32_t APSR value
*
* return the content of the APSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_APSR(void)
{
mrs r0, apsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Get xPSR Register value
*
* @return uint32_t xPSR value
*
* return the content of the xPSR register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_xPSR(void)
{
mrs r0, xpsr
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Process Stack Pointer
*
* @return ProcessStackPointer
*
* Return the actual process stack pointer
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PSP(void)
{
mrs r0, psp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Process Stack Pointer
*
* @param topOfProcStack Process Stack Pointer
*
* Assign the value ProcessStackPointer to the MSP
* (process stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PSP(uint32_t topOfProcStack)
{
msr psp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Main Stack Pointer
*
* @return Main Stack Pointer
*
* Return the current value of the MSP (main stack pointer)
* Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_MSP(void)
{
mrs r0, msp
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Main Stack Pointer
*
* @param topOfMainStack Main Stack Pointer
*
* Assign the value mainStackPointer to the MSP
* (main stack pointer) Cortex processor register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_MSP(uint32_t mainStackPointer)
{
msr msp, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Base Priority value
*
* @return BasePriority
*
* Return the content of the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_BASEPRI(void)
{
mrs r0, basepri
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Base Priority value
*
* @param basePri BasePriority
*
* Set the base priority register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_BASEPRI(uint32_t basePri)
{
msr basepri, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Priority Mask value
*
* @return PriMask
*
* Return state of the priority mask bit from the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_PRIMASK(void)
{
mrs r0, primask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Priority Mask value
*
* @param priMask PriMask
*
* Set the priority mask bit in the priority mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_PRIMASK(uint32_t priMask)
{
msr primask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the Fault Mask value
*
* @return FaultMask
*
* Return the content of the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM uint32_t __get_FAULTMASK(void)
{
mrs r0, faultmask
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Set the Fault Mask value
*
* @param faultMask faultMask value
*
* Set the fault mask register
*/
#if (__ARMCC_VERSION < 400000)
__ASM void __set_FAULTMASK(uint32_t faultMask)
{
msr faultmask, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Return the FPSCR value
*
* @return FloatingPointStatusControlRegister
*
* Return the content of the FPSCR register
*/
/**
* @brief Set the FPSCR value
*
* @param fpscr FloatingPointStatusControlRegister
*
* Set the FPSCR register
*/
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* obsolete */
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* obsolete */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* obsolete */
#endif
bsp/mb9bf506r/CMSIS/core_cmFunc.h 已删除 100644 → 0
浏览文件 @ 209da682
此差异已折叠。
bsp/mb9bf506r/CMSIS/core_cmInstr.h 已删除 100644 → 0
浏览文件 @ 209da682
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V1.40
* @date 16. February 2010
*
* @note
* Copyright (C) 2009-2010 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H__
#define __CORE_CMINSTR_H__
/* ########################## Core Instruction Access ######################### */
#if defined ( __CC_ARM ) /*------------------ RealView Compiler ----------------*/
/* ARM armcc specific functions */
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
#define __NOP __nop
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
#define __WFI __wfi
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
#define __SEV __sev
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
#define __ISB() __isb(0xF)
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
#define __DSB() __dsb(0xF)
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
#define __REV __rev
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
#if (__ARMCC_VERSION < 400677)
extern uint32_t __REV16(uint16_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM uint32_t __REV16(uint16_t value)
{
rev16 r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
#if (__ARMCC_VERSION < 400677)
extern int32_t __REVSH(int16_t value);
#else /* (__ARMCC_VERSION >= 400677) */
static __INLINE __ASM int32_t __REVSH(int16_t value)
{
revsh r0, r0
bx lr
}
#endif /* __ARMCC_VERSION */
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
#define __RBIT __rbit
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
#define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
#define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
#define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
#if (__ARMCC_VERSION < 400000)
extern void __CLREX(void);
#else /* (__ARMCC_VERSION >= 400000) */
#define __CLREX __clrex
#endif /* __ARMCC_VERSION */
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__ICCARM__)) /*---------------- ICC Compiler ---------------------*/
/* IAR iccarm specific functions */
#if defined (__ICCARM__)
#include <intrinsics.h> /* IAR Intrinsics */
#endif
#pragma diag_suppress=Pe940
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
#define __NOP __no_operation
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
static __INLINE void __WFI() { __ASM ("wfi"); }
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE() { __ASM ("wfe"); }
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
static __INLINE void __SEV() { __ASM ("sev"); }
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
/* intrinsic void __ISB(void) (see intrinsics.h */
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
/* intrinsic void __DSB(void) (see intrinsics.h */
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
/* intrinsic void __DMB(void) (see intrinsics.h */
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
/* intrinsic uint32_t __REV(uint32_t value) (see intrinsics.h */
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
static uint32_t __REV16(uint16_t value)
{
__ASM("rev16 r0, r0");
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
/* intrinsic uint32_t __REVSH(uint32_t value) (see intrinsics.h */
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
static uint8_t __LDREXB(uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
static uint16_t __LDREXH(uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
/* intrinsic unsigned long __LDREX(unsigned long *) (see intrinsics.h */
static uint32_t __LDREXW(uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
static uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
static uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
/* intrinsic unsigned long __STREX(unsigned long, unsigned long) (see intrinsics.h */
static uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
static __INLINE void __CLREX() { __ASM ("clrex"); }
#endif /* (__CORTEX_M >= 0x03) */
#pragma diag_default=Pe940
#elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/**
* @brief No Operation
*
* No Operation does nothing. This instruction can be used for code alignment
* purposes.
*/
static __INLINE void __NOP() { __ASM volatile ("nop"); }
/**
* @brief Wait For Interrupt
*
* Wait For Interrupt is a hint instruction that suspends execution until
* one of a number of events occurs.
*/
static __INLINE void __WFI() { __ASM volatile ("wfi"); }
/**
* @brief Wait For Event
*
* Wait For Event is a hint instruction that permits the processor to enter
* a low-power state until one of a number of events occurs.
*/
static __INLINE void __WFE() { __ASM volatile ("wfe"); }
/**
* @brief Send Event
*
* Send Event is a hint instruction. It causes an event to be signaled
* to the CPU.
*/
static __INLINE void __SEV() { __ASM volatile ("sev"); }
/**
* @brief Instruction Synchronization Barrier
*
* Instruction Synchronization Barrier flushes the pipeline in the processor,
* so that all instructions following the ISB are fetched from cache or
* memory, after the instruction has been completed
*/
static __INLINE void __ISB() { __ASM volatile ("isb"); }
/**
* @brief Data Synchronization Barrier
*
* The DSB instruction operation acts as a special kind of Data Memory Barrier.
* The DSB operation completes when all explicit memory accesses before this
* instruction complete.
*/
static __INLINE void __DSB() { __ASM volatile ("dsb"); }
/**
* @brief Data Memory Barrier
*
* DMB ensures the apparent order of the explicit memory operations before
* and after the instruction, without ensuring their completion.
*/
static __INLINE void __DMB() { __ASM volatile ("dmb"); }
/**
* @brief Reverse byte order (32 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in integer value
*/
static __INLINE uint32_t __REV(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order (16 bit)
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in unsigned short value
*/
static __INLINE uint32_t __REV16(uint16_t value)
{
uint32_t result=0;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief Reverse byte order in signed short value with sign extension to integer
*
* @param value value to reverse
* @return reversed value
*
* Reverse byte order in signed short value with sign extension to integer
*/
static __INLINE int32_t __REVSH(int16_t value)
{
uint32_t result=0;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#if (__CORTEX_M >= 0x03)
/**
* @brief Reverse bit order of value
*
* @param value value to reverse
* @return reversed value
*
* Reverse bit order of value
*/
static __INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result=0;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/**
* @brief LDR Exclusive (8 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 8 bit value
*/
static __INLINE uint8_t __LDREXB(uint8_t *addr)
{
uint8_t result=0;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (16 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 16 bit values
*/
static __INLINE uint16_t __LDREXH(uint16_t *addr)
{
uint16_t result=0;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief LDR Exclusive (32 bit)
*
* @param *addr address pointer
* @return value of (*address)
*
* Exclusive LDR command for 32 bit values
*/
static __INLINE uint32_t __LDREXW(uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/**
* @brief STR Exclusive (8 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 8 bit values
*/
static __INLINE uint32_t __STREXB(uint8_t value, uint8_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (16 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 16 bit values
*/
static __INLINE uint32_t __STREXH(uint16_t value, uint16_t *addr)
{
uint32_t result=0;
__ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief STR Exclusive (32 bit)
*
* @param value value to store
* @param *addr address pointer
* @return successful / failed
*
* Exclusive STR command for 32 bit values
*/
static __INLINE uint32_t __STREXW(uint32_t value, uint32_t *addr)
{
uint32_t result=0;
__ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
return(result);
}
/**
* @brief Remove the exclusive lock created by ldrex
*
* Removes the exclusive lock which is created by ldrex.
*/
static __INLINE void __CLREX() { __ASM volatile ("clrex"); }
#endif /* (__CORTEX_M >= 0x03) */
#elif (defined (__TASKING__)) /*--------------- TASKING Compiler -----------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
#endif // __CORE_CMINSTR_H__
bsp/mb9bf506r/CMSIS/start_gcc.S 已删除 100644 → 0
浏览文件 @ 209da682
/*
* File : start_gcc.S
* This file is part of RT-Thread RTOS
* COPYRIGHT (C) 2011, RT-Thread Development Team
*
* The license and distribution terms for this file may be
* found in the file LICENSE in this distribution or at
* http://www.rt-thread.org/license/LICENSE
*
* Change Logs:
* Date Author Notes
* 2011-07-01 lgnq first version
*/
.section .bss.init
.equ Stack_Size, 0x00000200
.space Stack_Size
Initial_spTop:
.syntax unified
.cpu cortex-m3
.fpu softvfp
.thumb
.global g_pfnVectors
.global Default_Handler
/* start address for the initialization values of the .data section.
defined in linker script */
.word _sidata
/* start address for the .data section. defined in linker script */
.word _sdata
/* end address for the .data section. defined in linker script */
.word _edata
/* start address for the .bss section. defined in linker script */
.word _sbss
/* end address for the .bss section. defined in linker script */
.word _ebss
// .equ Initial_spTop, 0x20000200
.equ BootRAM, 0xF1E0F85F
/**
* @brief This is the code that gets called when the processor first
* starts execution following a reset event. Only the absolutely
* necessary set is performed, after which the application
* supplied main() routine is called.
* @param None
* @retval : None
*/
.section .text.Reset_Handler
.weak Reset_Handler
.type Reset_Handler, %function
Reset_Handler:
/* restore original stack pointer */
LDR r0, =Initial_spTop
MSR msp, r0
/* Copy the data segment initializers from flash to SRAM */
movs r1, #0
b LoopCopyDataInit
CopyDataInit:
ldr r3, =_sidata
ldr r3, [r3, r1]
str r3, [r0, r1]
adds r1, r1, #4
LoopCopyDataInit:
ldr r0, =_sdata
ldr r3, =_edata
adds r2, r0, r1
cmp r2, r3
bcc CopyDataInit
ldr r2, =_sbss
b LoopFillZerobss
/* Zero fill the bss segment. */
FillZerobss:
movs r3, #0
str r3, [r2], #4
LoopFillZerobss:
ldr r3, = _ebss
cmp r2, r3
bcc FillZerobss
/* Call the application's entry point.*/
bl main
bx lr
.size Reset_Handler, .-Reset_Handler
/**
* @brief This is the code that gets called when the processor receives an
* unexpected interrupt. This simply enters an infinite loop, preserving
* the system state for examination by a debugger.
*
* @param None
* @retval : None
*/
.section .text.Default_Handler,"ax",%progbits
Default_Handler:
Infinite_Loop:
b Infinite_Loop
.size Default_Handler, .-Default_Handler
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,"a",%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word Initial_spTop
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word CSV_IRQHandler
.word SWDT_IRQHandler
.word LVD_IRQHandler
.word WFG_IRQHandler
.word EXINT0_7_IRQHandler
.word EXINT8_15_IRQHandler
.word DTIM_QDU_IRQHandler
.word MFS0RX_IRQHandler
.word MFS0TX_IRQHandler
.word MFS1RX_IRQHandler
.word MFS1TX_IRQHandler
.word MFS2RX_IRQHandler
.word MFS2TX_IRQHandler
.word MFS3RX_IRQHandler
.word MFS3TX_IRQHandler
.word MFS4RX_IRQHandler
.word MFS4TX_IRQHandler
.word MFS5RX_IRQHandler
.word MFS5TX_IRQHandler
.word MFS6RX_IRQHandler
.word MFS6TX_IRQHandler
.word MFS7RX_IRQHandler
.word MFS7TX_IRQHandler
.word PPG_IRQHandler
.word OSC_PLL_WC_IRQHandler
.word ADC0_IRQHandler
.word ADC1_IRQHandler
.word ADC2_IRQHandler
.word FRTIM_IRQHandler
.word INCAP_IRQHandler
.word OUTCOMP_IRQHandler
.word BTIM_IRQHandler
.word CAN0_IRQHandler
.word CAN1_IRQHandler
.word USBF_IRQHandler
.word USBF_USBH_IRQHandler
.word RESERVED_1_IRQHandler
.word RESERVED_2_IRQHandler
.word DMAC0_IRQHandler
.word DMAC1_IRQHandler
.word DMAC2_IRQHandler
.word DMAC3_IRQHandler
.word DMAC4_IRQHandler
.word DMAC5_IRQHandler
.word DMAC6_IRQHandler
.word DMAC7_IRQHandler
.word RESERVED_3_IRQHandler
.word RESERVED_4_IRQHandler
/*******************************************************************************
*
* Provide weak aliases for each Exception handler to the Default_Handler.
* As they are weak aliases, any function with the same name will override
* this definition.
*
*******************************************************************************/
.weak NMI_Handler
.thumb_set NMI_Handler,Default_Handler
.weak HardFault_Handler
.thumb_set HardFault_Handler,Default_Handler
.weak MemManage_Handler
.thumb_set MemManage_Handler,Default_Handler
.weak BusFault_Handler
.thumb_set BusFault_Handler,Default_Handler
.weak UsageFault_Handler
.thumb_set UsageFault_Handler,Default_Handler
.weak SVC_Handler
.thumb_set SVC_Handler,Default_Handler
.weak DebugMon_Handler
.thumb_set DebugMon_Handler,Default_Handler
.weak PendSV_Handler
.thumb_set PendSV_Handler,Default_Handler
.weak SysTick_Handler
.thumb_set SysTick_Handler,Default_Handler
.weak CSV_IRQHandler
.thumb_set CSV_IRQHandler,Default_Handler
.weak SWDT_IRQHandler
.thumb_set SWDT_IRQHandler,Default_Handler
.weak LVD_IRQHandler
.thumb_set LVD_IRQHandler,Default_Handler
.weak WFG_IRQHandler
.thumb_set WFG_IRQHandler,Default_Handler
.weak EXINT0_7_IRQHandler
.thumb_set EXINT0_7_IRQHandler,Default_Handler
.weak EXINT8_15_IRQHandler
.thumb_set EXINT8_15_IRQHandler,Default_Handler
.weak DTIM_QDU_IRQHandler
.thumb_set DTIM_QDU_IRQHandler,Default_Handler
.weak MFS0RX_IRQHandler
.thumb_set MFS0RX_IRQHandler,Default_Handler
.weak MFS0TX_IRQHandler
.thumb_set MFS0TX_IRQHandler,Default_Handler
.weak MFS1RX_IRQHandler
.thumb_set MFS1RX_IRQHandler,Default_Handler
.weak MFS1TX_IRQHandler
.thumb_set MFS1TX_IRQHandler,Default_Handler
.weak MFS2RX_IRQHandler
.thumb_set MFS2RX_IRQHandler,Default_Handler
.weak MFS2TX_IRQHandler
.thumb_set MFS2TX_IRQHandler,Default_Handler
.weak MFS3RX_IRQHandler
.thumb_set MFS3RX_IRQHandler,Default_Handler
.weak MFS3TX_IRQHandler
.thumb_set MFS3TX_IRQHandler,Default_Handler
.weak MFS4RX_IRQHandler
.thumb_set MFS4RX_IRQHandler,Default_Handler
.weak MFS4TX_IRQHandler
.thumb_set MFS4TX_IRQHandler,Default_Handler
.weak MFS5RX_IRQHandler
.thumb_set MFS5RX_IRQHandler,Default_Handler
.weak MFS5TX_IRQHandler
.thumb_set MFS5TX_IRQHandler,Default_Handler
.weak MFS6RX_IRQHandler
.thumb_set MFS6RX_IRQHandler,Default_Handler
.weak MFS6TX_IRQHandler
.thumb_set MFS6TX_IRQHandler,Default_Handler
.weak MFS7RX_IRQHandler
.thumb_set MFS7RX_IRQHandler,Default_Handler
.weak MFS7TX_IRQHandler
.thumb_set MFS7TX_IRQHandler,Default_Handler
.weak PPG_IRQHandler
.thumb_set PPG_IRQHandler,Default_Handler
.weak OSC_PLL_WC_IRQHandler
.thumb_set OSC_PLL_WC_IRQHandler,Default_Handler
.weak ADC0_IRQHandler
.thumb_set ADC0_IRQHandler,Default_Handler
.weak ADC1_IRQHandler
.thumb_set ADC1_IRQHandler,Default_Handler
.weak ADC2_IRQHandler
.thumb_set ADC2_IRQHandler,Default_Handler
.weak FRTIM_IRQHandler
.thumb_set FRTIM_IRQHandler,Default_Handler
.weak INCAP_IRQHandler
.thumb_set INCAP_IRQHandler,Default_Handler
.weak OUTCOMP_IRQHandler
.thumb_set OUTCOMP_IRQHandler,Default_Handler
.weak BTIM_IRQHandler
.thumb_set BTIM_IRQHandler,Default_Handler
.weak CAN0_IRQHandler
.thumb_set CAN0_IRQHandler,Default_Handler
.weak CAN1_IRQHandler
.thumb_set CAN1_IRQHandler,Default_Handler
.weak USBF_IRQHandler
.thumb_set USBF_IRQHandler,Default_Handler
.weak USBF_USBH_IRQHandler
.thumb_set USBF_USBH_IRQHandler,Default_Handler
.weak RESERVED_1_IRQHandler
.thumb_set RESERVED_1_IRQHandler,Default_Handler
.weak RESERVED_2_IRQHandler
.thumb_set RESERVED_2_IRQHandler,Default_Handler
.weak DMAC0_IRQHandler
.thumb_set DMAC0_IRQHandler,Default_Handler
.weak DMAC1_IRQHandler
.thumb_set DMAC1_IRQHandler,Default_Handler
.weak DMAC2_IRQHandler
.thumb_set DMAC2_IRQHandler,Default_Handler
.weak DMAC3_IRQHandler
.thumb_set DMAC3_IRQHandler,Default_Handler
.weak DMAC4_IRQHandler
.thumb_set DMAC4_IRQHandler,Default_Handler
.weak DMAC5_IRQHandler
.thumb_set DMAC5_IRQHandler,Default_Handler
.weak DMAC6_IRQHandler
.thumb_set DMAC6_IRQHandler,Default_Handler
.weak DMAC7_IRQHandler
.thumb_set DMAC7_IRQHandler,Default_Handler
.weak RESERVED_3_IRQHandler
.thumb_set RESERVED_3_IRQHandler,Default_Handler
.weak RESERVED_4_IRQHandler
.thumb_set RESERVED_4_IRQHandler,Default_Handler
bsp/mb9bf506r/CMSIS/start_iar.S 已删除 100644 → 0
浏览文件 @ 209da682
;/*
; * File : context_iar.S
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2009-01-17 Bernard first version
; * 2009-09-27 Bernard add protect when contex switch occurs
; */
#include "rtconfig.h"
MODULE ?cstartup
;; ICODE is the same segment as cstartup. By placing __low_level_init
;; in the same segment, we make sure it can be reached with BL. */
SECTION CSTACK:DATA:NOROOT(3)
SECTION .icode:CODE:NOROOT(2)
#ifdef RT_USING_UART2
IMPORT MFS2RX_IRQHandler
#endif
PUBLIC __low_level_init
PUBWEAK SystemInit_ExtMemCtl
SECTION .text:CODE:REORDER(2)
THUMB
SystemInit_ExtMemCtl
BX LR
__low_level_init:
;; Initialize hardware.
LDR R0, = SystemInit_ExtMemCtl ; initialize external memory controller
MOV R11, LR
BLX R0
LDR R1, =sfe(CSTACK) ; restore original stack pointer
MSR MSP, R1
MOV R0,#1
;; Return with BX to be independent of mode of caller
BX R11
;; Forward declaration of sections.
SECTION .intvec:CODE:NOROOT(2)
EXTERN __iar_program_start
PUBLIC __vector_table
DATA
__vector_table
DCD sfe(CSTACK)
DCD __iar_program_start
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD CSV_IRQHandler ; Clock Super Visor
DCD SWDT_IRQHandler ; Software Watchdog Timer
DCD LVD_IRQHandler ; Low Voltage Detector
DCD WFG_IRQHandler ; Wave Form Generator
DCD EXINT0_7_IRQHandler ; External Interrupt Request ch.0 to ch.7
DCD EXINT8_15_IRQHandler ; External Interrupt Request ch.8 to ch.15
DCD DTIM_QDU_IRQHandler ; Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; MultiFunction Serial ch.1
#ifdef RT_USING_UART2
DCD MFS2RX_IRQHandler ; MultiFunction Serial ch.2
#else
DCD NULL_IRQHandler ; MultiFunction Serial ch.2
#endif
DCD MFS2TX_IRQHandler ; MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; MultiFunction Serial ch.7
DCD PPG_IRQHandler ; PPG
DCD OSC_PLL_WC_IRQHandler ; OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; ADC0
DCD ADC1_IRQHandler ; ADC1
DCD ADC2_IRQHandler ; ADC2
DCD FRTIM_IRQHandler ; Free-run Timer
DCD INCAP_IRQHandler ; Input Capture
DCD OUTCOMP_IRQHandler ; Output Compare
DCD BTIM_IRQHandler ; Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; CAN ch.0
DCD CAN1_IRQHandler ; CAN ch.1
DCD USBF_IRQHandler ; USB Function
DCD USBF_USBH_IRQHandler ; USB Function / USB HOST
DCD RESERVED_1_IRQHandler ; Reserved_1
DCD RESERVED_2_IRQHandler ; Reserved_2
DCD DMAC0_IRQHandler ; DMAC ch.0
DCD DMAC1_IRQHandler ; DMAC ch.1
DCD DMAC2_IRQHandler ; DMAC ch.2
DCD DMAC3_IRQHandler ; DMAC ch.3
DCD DMAC4_IRQHandler ; DMAC ch.4
DCD DMAC5_IRQHandler ; DMAC ch.5
DCD DMAC6_IRQHandler ; DMAC ch.6
DCD DMAC7_IRQHandler ; DMAC ch.7
DCD RESERVED_3_IRQHandler ; Reserved_3
DCD RESERVED_4_IRQHandler ; Reserved_4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Default interrupt handlers.
;;
THUMB
PUBWEAK NMI_Handler
SECTION .text:CODE:REORDER(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
SECTION .text:CODE:REORDER(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
SECTION .text:CODE:REORDER(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
SECTION .text:CODE:REORDER(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
SECTION .text:CODE:REORDER(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
SECTION .text:CODE:REORDER(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
SECTION .text:CODE:REORDER(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
SECTION .text:CODE:REORDER(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
SECTION .text:CODE:REORDER(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK CSV_IRQHandler
SECTION .text:CODE:REORDER(1)
CSV_IRQHandler
B CSV_IRQHandler
PUBWEAK SWDT_IRQHandler
SECTION .text:CODE:REORDER(1)
SWDT_IRQHandler
B SWDT_IRQHandler
PUBWEAK LVD_IRQHandler
SECTION .text:CODE:REORDER(1)
LVD_IRQHandler
B LVD_IRQHandler
PUBWEAK WFG_IRQHandler
SECTION .text:CODE:REORDER(1)
WFG_IRQHandler
B WFG_IRQHandler
PUBWEAK EXINT0_7_IRQHandler
SECTION .text:CODE:REORDER(1)
EXINT0_7_IRQHandler
B EXINT0_7_IRQHandler
PUBWEAK EXINT8_15_IRQHandler
SECTION .text:CODE:REORDER(1)
EXINT8_15_IRQHandler
B EXINT8_15_IRQHandler
PUBWEAK DTIM_QDU_IRQHandler
SECTION .text:CODE:REORDER(1)
DTIM_QDU_IRQHandler
B DTIM_QDU_IRQHandler
PUBWEAK MFS0RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0RX_IRQHandler
B MFS0RX_IRQHandler
PUBWEAK MFS0TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS0TX_IRQHandler
B MFS0TX_IRQHandler
PUBWEAK MFS1RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1RX_IRQHandler
B MFS1RX_IRQHandler
PUBWEAK MFS1TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS1TX_IRQHandler
B MFS1TX_IRQHandler
PUBWEAK NULL_IRQHandler
SECTION .text:CODE:REORDER(1)
NULL_IRQHandler
B NULL_IRQHandler
PUBWEAK MFS2TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS2TX_IRQHandler
B MFS2TX_IRQHandler
PUBWEAK MFS3RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3RX_IRQHandler
B MFS3RX_IRQHandler
PUBWEAK MFS3TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS3TX_IRQHandler
B MFS3TX_IRQHandler
PUBWEAK MFS4RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4RX_IRQHandler
B MFS4RX_IRQHandler
PUBWEAK MFS4TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS4TX_IRQHandler
B MFS4TX_IRQHandler
PUBWEAK MFS5RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5RX_IRQHandler
B MFS5RX_IRQHandler
PUBWEAK MFS5TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS5TX_IRQHandler
B MFS5TX_IRQHandler
PUBWEAK MFS6RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6RX_IRQHandler
B MFS6RX_IRQHandler
PUBWEAK MFS6TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS6TX_IRQHandler
B MFS6TX_IRQHandler
PUBWEAK MFS7RX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7RX_IRQHandler
B MFS7RX_IRQHandler
PUBWEAK MFS7TX_IRQHandler
SECTION .text:CODE:REORDER(1)
MFS7TX_IRQHandler
B MFS7TX_IRQHandler
PUBWEAK PPG_IRQHandler
SECTION .text:CODE:REORDER(1)
PPG_IRQHandler
B PPG_IRQHandler
PUBWEAK OSC_PLL_WC_IRQHandler
SECTION .text:CODE:REORDER(1)
OSC_PLL_WC_IRQHandler
B OSC_PLL_WC_IRQHandler
PUBWEAK ADC0_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC0_IRQHandler
B ADC0_IRQHandler
PUBWEAK ADC1_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC1_IRQHandler
B ADC1_IRQHandler
PUBWEAK ADC2_IRQHandler
SECTION .text:CODE:REORDER(1)
ADC2_IRQHandler
B ADC2_IRQHandler
PUBWEAK FRTIM_IRQHandler
SECTION .text:CODE:REORDER(1)
FRTIM_IRQHandler
B FRTIM_IRQHandler
PUBWEAK INCAP_IRQHandler
SECTION .text:CODE:REORDER(1)
INCAP_IRQHandler
B INCAP_IRQHandler
PUBWEAK OUTCOMP_IRQHandler
SECTION .text:CODE:REORDER(1)
OUTCOMP_IRQHandler
B OUTCOMP_IRQHandler
PUBWEAK BTIM_IRQHandler
SECTION .text:CODE:REORDER(1)
BTIM_IRQHandler
B BTIM_IRQHandler
PUBWEAK CAN0_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN0_IRQHandler
B CAN0_IRQHandler
PUBWEAK CAN1_IRQHandler
SECTION .text:CODE:REORDER(1)
CAN1_IRQHandler
B CAN1_IRQHandler
PUBWEAK USBF_IRQHandler
SECTION .text:CODE:REORDER(1)
USBF_IRQHandler
B USBF_IRQHandler
PUBWEAK USBF_USBH_IRQHandler
SECTION .text:CODE:REORDER(1)
USBF_USBH_IRQHandler
B USBF_USBH_IRQHandler
PUBWEAK RESERVED_1_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_1_IRQHandler
B RESERVED_1_IRQHandler
PUBWEAK RESERVED_2_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_2_IRQHandler
B RESERVED_2_IRQHandler
PUBWEAK DMAC0_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC0_IRQHandler
B DMAC0_IRQHandler
PUBWEAK DMAC1_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC1_IRQHandler
B DMAC1_IRQHandler
PUBWEAK DMAC2_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC2_IRQHandler
B DMAC2_IRQHandler
PUBWEAK DMAC3_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC3_IRQHandler
B DMAC3_IRQHandler
PUBWEAK DMAC4_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC4_IRQHandler
B DMAC4_IRQHandler
PUBWEAK DMAC5_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC5_IRQHandler
B DMAC5_IRQHandler
PUBWEAK DMAC6_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC6_IRQHandler
B DMAC6_IRQHandler
PUBWEAK DMAC7_IRQHandler
SECTION .text:CODE:REORDER(1)
DMAC7_IRQHandler
B DMAC7_IRQHandler
PUBWEAK RESERVED_3_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_3_IRQHandler
B RESERVED_3_IRQHandler
PUBWEAK RESERVED_4_IRQHandler
SECTION .text:CODE:REORDER(1)
RESERVED_4_IRQHandler
B RESERVED_4_IRQHandler
END
bsp/mb9bf506r/CMSIS/system_mb9bf50x.c 已删除 100644 → 0
浏览文件 @ 209da682
/************************************************************************/
/* (C) Fujitsu Semiconductor Europe GmbH */
/* */
/* The following software deliverable is intended for and must only be */
/* used for reference and in an evaluation laboratory environment. */
/* It is provided on an as-is basis without charge and is subject to */
/* alterations. */
/* It is the users obligation to fully test the software in its */
/* environment and to ensure proper functionality, qualification and */
/* compliance with component specifications. */
/* */
/* In the event the software deliverable includes the use of open */
/* source components, the provisions of the governing open source */
/* license agreement shall apply with respect to such software */
/* deliverable. */
/* FSEU does not warrant that the deliverables do not infringe any */
/* third party intellectual property right (IPR). In the event that */
/* the deliverables infringe a third party IPR it is the sole */
/* responsibility of the customer to obtain necessary licenses to */
/* continue the usage of the deliverable. */
/* */
/* To the maximum extent permitted by applicable law FSEU disclaims all */
/* warranties, whether express or implied, in particular, but not */
/* limited to, warranties of merchantability and fitness for a */
/* particular purpose for which the deliverable is not designated. */
/* */
/* To the maximum extent permitted by applicable law, FSEU's liability */
/* is restricted to intention and gross negligence. */
/* FSEU is not liable for consequential damages. */
/* */
/* (V1.4) */
/************************************************************************/
#include "mb9bf506r.h"
/*
* 80MHz : Master Clock
*/
const uint32_t SystemFrequency = 80000000UL;
uint32_t SysFreHCLK = 80000000UL; /* HCLK = MasterClock / 1 */
uint32_t SysFrePCLK0 = 40000000UL; /* PCLK0 = HCLK / 2 */
uint32_t SysFrePCLK1 = 40000000UL; /* PCLK1 = HCLK / 2 */
uint32_t SysFrePCLK2 = 40000000UL; /* PCLK2 = HCLK / 2 */
uint32_t SysFreTPIU = 0UL; /* TPIUCLK : Disable */
/*
* Prototype of internal function
*/
static void ClockInit(void);
static void HwwdtDisable(void);
/*
* Setup the microcontroller system
*/
void SystemInit (void)
{
HwwdtDisable(); /* Disable Hardware Watchdog */
ClockInit(); /* Initialize Clock */
}
/*
* Initialize Clock
*/
static void ClockInit(void)
{
/*set Main clock stabilization
wait time to 2ms*/
FM3_CRG->CSW_TMR = 0x79;
/*Enable Main Oscilator*/
FM3_CRG->SCM_CTL |= 1<<1;
/*Wait stabilization end*/
while(!(FM3_CRG->SCM_STR & 0x02));
/* sub CLK enable */
//FM3_CRG->SCM_CTL |= 0x08;
//while(!(FM3_CRG->SCM_STR & 0x08));
/*Set PLL stabilization
wait time to 512uS*/
FM3_CRG->PSW_TMR |= 2;
/*Set PLL to 80MHz*/
FM3_CRG->PLL_CTL1 = 0; /*K = 1, M=1*/
FM3_CRG->PLL_CTL2 = 19; /*N = 20*/
/*Enable PLL*/
FM3_CRG->SCM_CTL |= 0x10;
/*Set bus prescalers*/
FM3_CRG->BSC_PSR = 0; /*Base clock Prescaler 1:1*/
FM3_CRG->APBC0_PSR |= 1; /*APB0 clock Prescaler 1:2*/
FM3_CRG->APBC1_PSR |= 1; /*APB1 clock Prescaler 1:2*/
FM3_CRG->APBC2_PSR |= 1; /*APB2 clock Prescaler 1:2*/
/*Wait PLL stabilizatoin end*/
while(!(FM3_CRG->SCM_STR & 0x10));
/*Select PLL for main clock*/
FM3_CRG->SCM_CTL |= 2<<5;
/*Wait PLL to be connected*/
while((FM3_CRG->SCM_STR & 0xe0) != 0x40);
}
/*
* Stop HW Watchdog Timer
*/
static void HwwdtDisable(void)
{
/* UnLock (except WDG_CTL) */
FM3_HWWDT->WDG_LCK = 0x1ACCE551;
/* UnLock (WDG_CTL) */
FM3_HWWDT->WDG_LCK = 0xE5331AAE;
/* Disable WDG */
FM3_HWWDT->WDG_CTL = 0x00;
}
bsp/mb9bf506r/applications/startup.c
浏览文件 @ cbd32a0c
......@@ -16,7 +16,7 @@
#include <rtthread.h>
#include "board.h"
#include "mb9bf506r.h"
#ifdef RT_USING_FINSH
#include <finsh.h>
#endif
......@@ -109,9 +109,6 @@ int main(void)
{
/* disable interrupt first */
rt_hw_interrupt_disable();
/* init system setting */
SystemInit();
/* startup RT-Thread RTOS */
rtthread_startup();
......
bsp/mb9bf506r/drivers/board.c
浏览文件 @ cbd32a0c
......@@ -16,13 +16,11 @@
#include <rtthread.h>
#include "board.h"
#include "mb9bf506r.h"
#include "mcu.h"
#include "serial.h"
#include "nand.h"
extern const uint32_t SystemFrequency;
/**
* @addtogroup FM3
*/
......@@ -48,8 +46,8 @@ void SysTick_Handler(void)
*/
void rt_hw_board_init(void)
{
/* init systick */
SysTick_Config(SystemFrequency/RT_TICK_PER_SECOND);
/* init systick */
SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
/* initialize UART device */
rt_hw_serial_init();
......
bsp/mb9bf506r/libraries/CMSIS/Include/cmsis_iar.h 0 → 100644
浏览文件 @ cbd32a0c
/**************************************************
*
* This file shall be included in appropriate CMSIS header
* files, to provide required functions and intrinsics when
* building with the IAR C/C++ Compiler for ARM (iccarm).
*
* Copyright 2011 IAR Systems. All rights reserved.
*
* $Revision: 50409 $
*
**************************************************/
#ifndef __CMSIS_IAR_H__
#define __CMSIS_IAR_H__
#ifndef __ICCARM__
#error This file should only be compiled by ICCARM
#endif
#pragma system_include
#include <intrinsics.h>
#if (__CORE__ == __ARM6M__)
/* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */
#define __CLZ __cmsis_iar_clz
#define __SSAT __cmsis_iar_ssat
#endif
#pragma diag_suppress=Pe940
#pragma diag_suppress=Pe177
#define __enable_irq __enable_interrupt
#define __disable_irq __disable_interrupt
#define __NOP __no_operation
#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
#if (__VER__ < 6010002) /* If iccarm version is older than 6.10.2 ---------- */
static uint32_t __get_APSR(void)
{
__ASM("mrs r0, apsr");
}
static uint32_t __get_xPSR(void)
{
__ASM("mrs r0, psr"); /* assembler does not know "xpsr" */
}
#endif /* __VER__ < 6010002 */
static uint32_t __get_IPSR(void)
{
__ASM("mrs r0, ipsr");
}
static uint32_t __get_PSR(void)
{
__ASM("mrs r0, psr");
}
static uint32_t __get_PSP(void)
{
__ASM("mrs r0, psp");
}
static void __set_PSP(uint32_t topOfProcStack)
{
__ASM("msr psp, r0");
}
static uint32_t __get_MSP(void)
{
__ASM("mrs r0, msp");
}
static void __set_MSP(uint32_t topOfMainStack)
{
__ASM("msr msp, r0");
}
static __INLINE void __WFI(void)
{
__ASM ("wfi");
}
static __INLINE void __WFE(void)
{
__ASM ("wfe");
}
static __INLINE void __SEV(void)
{
__ASM ("sev");
}
static uint32_t __REV16(uint32_t value)
{
__ASM("rev16 r0, r0");
}
#else /* __VER__ < 6020000 */
static uint32_t __get_xPSR(void)
{
return __get_PSR(); /* __get_PSR() intrinsic introduced in iccarm 6.20 */
}
#endif /* __VER__ < 6020000 */
#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
static __INLINE void __enable_fault_irq(void)
{
__ASM ("cpsie f");
}
static __INLINE void __disable_fault_irq(void)
{
__ASM ("cpsid f");
}
static uint32_t __RBIT(uint32_t value)
{
__ASM("rbit r0, r0");
}
static uint8_t __LDREXB(volatile uint8_t *addr)
{
__ASM("ldrexb r0, [r0]");
}
static uint16_t __LDREXH(volatile uint16_t *addr)
{
__ASM("ldrexh r0, [r0]");
}
static uint32_t __LDREXW(volatile uint32_t *addr)
{
__ASM("ldrex r0, [r0]");
}
static uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
__ASM("strexb r0, r0, [r1]");
}
static uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
__ASM("strexh r0, r0, [r1]");
}
static uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
__ASM("strex r0, r0, [r1]");
}
static __INLINE void __CLREX(void)
{
__ASM ("clrex");
}
#else /* __VER__ >= 6020000 --------------------- */
#define __LDREXW __LDREX
#define __STREXW __STREX
#define __enable_fault_irq __enable_fiq
#define __disable_fault_irq __disable_fiq
#endif /* __VER__ < 6020000 */
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */
#if (__VER__ < 6020000) /* If iccarm version is older than 6.20.0 ---------- */
static uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
__ASM("vmrs r0, fpscr");
#else
return(0);
#endif
}
static void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) /* __FPU_PRESENT is defined in the device header file, if present in current device. */
__ASM("vmsr fpscr, r0");
#endif
}
#endif /* __VER__ < 6020000 */
#endif /* (__CORTEX_M == 0x04) */
static __INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2));
}
#pragma diag_default=Pe940
#pragma diag_default=Pe177
#endif /* __CMSIS_IAR_H__ */
bsp/mb9bf506r/libraries/CMSIS/Include/core_cmFunc.h 0 → 100644
浏览文件 @ cbd32a0c
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
/* ########################### Core Function Access ########################### */
/** \ingroup CMSIS_Core_FunctionInterface
\defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/* intrinsic void __enable_irq(); */
/* intrinsic void __disable_irq(); */
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__STATIC_INLINE uint32_t __get_CONTROL(void)
{
register uint32_t __regControl __ASM("control");
return(__regControl);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__STATIC_INLINE void __set_CONTROL(uint32_t control)
{
register uint32_t __regControl __ASM("control");
__regControl = control;
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__STATIC_INLINE uint32_t __get_IPSR(void)
{
register uint32_t __regIPSR __ASM("ipsr");
return(__regIPSR);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__STATIC_INLINE uint32_t __get_APSR(void)
{
register uint32_t __regAPSR __ASM("apsr");
return(__regAPSR);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__STATIC_INLINE uint32_t __get_xPSR(void)
{
register uint32_t __regXPSR __ASM("xpsr");
return(__regXPSR);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t __regProcessStackPointer __ASM("psp");
return(__regProcessStackPointer);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
register uint32_t __regProcessStackPointer __ASM("psp");
__regProcessStackPointer = topOfProcStack;
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t __regMainStackPointer __ASM("msp");
return(__regMainStackPointer);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
register uint32_t __regMainStackPointer __ASM("msp");
__regMainStackPointer = topOfMainStack;
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__STATIC_INLINE uint32_t __get_PRIMASK(void)
{
register uint32_t __regPriMask __ASM("primask");
return(__regPriMask);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
register uint32_t __regPriMask __ASM("primask");
__regPriMask = (priMask);
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __enable_fault_irq __enable_fiq
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
#define __disable_fault_irq __disable_fiq
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__STATIC_INLINE uint32_t __get_BASEPRI(void)
{
register uint32_t __regBasePri __ASM("basepri");
return(__regBasePri);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
{
register uint32_t __regBasePri __ASM("basepri");
__regBasePri = (basePri & 0xff);
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
register uint32_t __regFaultMask __ASM("faultmask");
return(__regFaultMask);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
register uint32_t __regFaultMask __ASM("faultmask");
__regFaultMask = (faultMask & (uint32_t)1);
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
return(__regfpscr);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
register uint32_t __regfpscr __ASM("fpscr");
__regfpscr = (fpscr);
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief Enable IRQ Interrupts
This function enables IRQ interrupts by clearing the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
{
__ASM volatile ("cpsie i");
}
/** \brief Disable IRQ Interrupts
This function disables IRQ interrupts by setting the I-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
{
__ASM volatile ("cpsid i");
}
/** \brief Get Control Register
This function returns the content of the Control Register.
\return Control Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
{
uint32_t result;
__ASM volatile ("MRS %0, control" : "=r" (result) );
return(result);
}
/** \brief Set Control Register
This function writes the given value to the Control Register.
\param [in] control Control Register value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
{
__ASM volatile ("MSR control, %0" : : "r" (control) );
}
/** \brief Get IPSR Register
This function returns the content of the IPSR Register.
\return IPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, ipsr" : "=r" (result) );
return(result);
}
/** \brief Get APSR Register
This function returns the content of the APSR Register.
\return APSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, apsr" : "=r" (result) );
return(result);
}
/** \brief Get xPSR Register
This function returns the content of the xPSR Register.
\return xPSR Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
{
uint32_t result;
__ASM volatile ("MRS %0, xpsr" : "=r" (result) );
return(result);
}
/** \brief Get Process Stack Pointer
This function returns the current value of the Process Stack Pointer (PSP).
\return PSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, psp\n" : "=r" (result) );
return(result);
}
/** \brief Set Process Stack Pointer
This function assigns the given value to the Process Stack Pointer (PSP).
\param [in] topOfProcStack Process Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
{
__ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
}
/** \brief Get Main Stack Pointer
This function returns the current value of the Main Stack Pointer (MSP).
\return MSP Register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
{
register uint32_t result;
__ASM volatile ("MRS %0, msp\n" : "=r" (result) );
return(result);
}
/** \brief Set Main Stack Pointer
This function assigns the given value to the Main Stack Pointer (MSP).
\param [in] topOfMainStack Main Stack Pointer value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
{
__ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
}
/** \brief Get Priority Mask
This function returns the current state of the priority mask bit from the Priority Mask Register.
\return Priority Mask value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, primask" : "=r" (result) );
return(result);
}
/** \brief Set Priority Mask
This function assigns the given value to the Priority Mask Register.
\param [in] priMask Priority Mask
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
{
__ASM volatile ("MSR primask, %0" : : "r" (priMask) );
}
#if (__CORTEX_M >= 0x03)
/** \brief Enable FIQ
This function enables FIQ interrupts by clearing the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
{
__ASM volatile ("cpsie f");
}
/** \brief Disable FIQ
This function disables FIQ interrupts by setting the F-bit in the CPSR.
Can only be executed in Privileged modes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
{
__ASM volatile ("cpsid f");
}
/** \brief Get Base Priority
This function returns the current value of the Base Priority register.
\return Base Priority register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
{
uint32_t result;
__ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
return(result);
}
/** \brief Set Base Priority
This function assigns the given value to the Base Priority register.
\param [in] basePri Base Priority value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
{
__ASM volatile ("MSR basepri, %0" : : "r" (value) );
}
/** \brief Get Fault Mask
This function returns the current value of the Fault Mask register.
\return Fault Mask register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
{
uint32_t result;
__ASM volatile ("MRS %0, faultmask" : "=r" (result) );
return(result);
}
/** \brief Set Fault Mask
This function assigns the given value to the Fault Mask register.
\param [in] faultMask Fault Mask value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
{
__ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
}
#endif /* (__CORTEX_M >= 0x03) */
#if (__CORTEX_M == 0x04)
/** \brief Get FPSCR
This function returns the current value of the Floating Point Status/Control register.
\return Floating Point Status/Control register value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t result;
__ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
return(result);
#else
return(0);
#endif
}
/** \brief Set FPSCR
This function assigns the given value to the Floating Point Status/Control register.
\param [in] fpscr Floating Point Status/Control value to set
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
#endif
}
#endif /* (__CORTEX_M == 0x04) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all instrinsics,
* Including the CMSIS ones.
*/
#endif
/*@} end of CMSIS_Core_RegAccFunctions */
#endif /* __CORE_CMFUNC_H */
bsp/mb9bf506r/libraries/CMSIS/Include/core_cmInstr.h 0 → 100644
浏览文件 @ cbd32a0c
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.01
* @date 06. March 2012
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
/* ########################## Core Instruction Access ######################### */
/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
Access to dedicated instructions
@{
*/
#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
/* ARM armcc specific functions */
#if (__ARMCC_VERSION < 400677)
#error "Please use ARM Compiler Toolchain V4.0.677 or later!"
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
#define __NOP __nop
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
#define __WFI __wfi
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
#define __WFE __wfe
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
#define __SEV __sev
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
#define __ISB() __isb(0xF)
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
#define __DSB() __dsb(0xF)
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
#define __DMB() __dmb(0xF)
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __REV __rev
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
{
rev16 r0, r0
bx lr
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
{
revsh r0, r0
bx lr
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
#define __ROR __ror
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
#define __RBIT __rbit
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXB(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXH(value, ptr) __strex(value, ptr)
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
#define __STREXW(value, ptr) __strex(value, ptr)
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
#define __CLREX __clrex
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT __ssat
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT __usat
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
#define __CLZ __clz
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
/* IAR iccarm specific functions */
#include <cmsis_iar.h>
#elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
/* TI CCS specific functions */
#include <cmsis_ccs.h>
#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
{
__ASM volatile ("nop");
}
/** \brief Wait For Interrupt
Wait For Interrupt is a hint instruction that suspends execution
until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
{
__ASM volatile ("wfi");
}
/** \brief Wait For Event
Wait For Event is a hint instruction that permits the processor to enter
a low-power state until one of a number of events occurs.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
{
__ASM volatile ("wfe");
}
/** \brief Send Event
Send Event is a hint instruction. It causes an event to be signaled to the CPU.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
{
__ASM volatile ("sev");
}
/** \brief Instruction Synchronization Barrier
Instruction Synchronization Barrier flushes the pipeline in the processor,
so that all instructions following the ISB are fetched from cache or
memory, after the instruction has been completed.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
{
__ASM volatile ("isb");
}
/** \brief Data Synchronization Barrier
This function acts as a special kind of Data Memory Barrier.
It completes when all explicit memory accesses before this instruction complete.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
{
__ASM volatile ("dsb");
}
/** \brief Data Memory Barrier
This function ensures the apparent order of the explicit memory operations before
and after the instruction, without ensuring their completion.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
{
__ASM volatile ("dmb");
}
/** \brief Reverse byte order (32 bit)
This function reverses the byte order in integer value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order (16 bit)
This function reverses the byte order in two unsigned short values.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
{
uint32_t result;
__ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Reverse byte order in signed short value
This function reverses the byte order in a signed short value with sign extension to integer.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
{
uint32_t result;
__ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief Rotate Right in unsigned value (32 bit)
This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
\param [in] value Value to rotate
\param [in] value Number of Bits to rotate
\return Rotated value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
{
__ASM volatile ("ror %0, %0, %1" : "+r" (op1) : "r" (op2) );
return(op1);
}
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
This function reverses the bit order of the given value.
\param [in] value Value to reverse
\return Reversed value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
{
uint32_t result;
__ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
/** \brief LDR Exclusive (8 bit)
This function performs a exclusive LDR command for 8 bit value.
\param [in] ptr Pointer to data
\return value of type uint8_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
{
uint8_t result;
__ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (16 bit)
This function performs a exclusive LDR command for 16 bit values.
\param [in] ptr Pointer to data
\return value of type uint16_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
{
uint16_t result;
__ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief LDR Exclusive (32 bit)
This function performs a exclusive LDR command for 32 bit values.
\param [in] ptr Pointer to data
\return value of type uint32_t at (*ptr)
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
return(result);
}
/** \brief STR Exclusive (8 bit)
This function performs a exclusive STR command for 8 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
{
uint32_t result;
__ASM volatile ("strexb %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (16 bit)
This function performs a exclusive STR command for 16 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
{
uint32_t result;
__ASM volatile ("strexh %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief STR Exclusive (32 bit)
This function performs a exclusive STR command for 32 bit values.
\param [in] value Value to store
\param [in] ptr Pointer to location
\return 0 Function succeeded
\return 1 Function failed
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
{
uint32_t result;
__ASM volatile ("strex %0, %2, [%1]" : "=&r" (result) : "r" (addr), "r" (value) );
return(result);
}
/** \brief Remove the exclusive lock
This function removes the exclusive lock which is created by LDREX.
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
{
__ASM volatile ("clrex");
}
/** \brief Signed Saturate
This function saturates a signed value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (1..32)
\return Saturated value
*/
#define __SSAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Unsigned Saturate
This function saturates an unsigned value.
\param [in] value Value to be saturated
\param [in] sat Bit position to saturate to (0..31)
\return Saturated value
*/
#define __USAT(ARG1,ARG2) \
({ \
uint32_t __RES, __ARG1 = (ARG1); \
__ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
__RES; \
})
/** \brief Count leading zeros
This function counts the number of leading zeros of a data value.
\param [in] value Value to count the leading zeros
\return number of leading zeros in value
*/
__attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
{
uint8_t result;
__ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
return(result);
}
#endif /* (__CORTEX_M >= 0x03) */
#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
/* TASKING carm specific functions */
/*
* The CMSIS functions have been implemented as intrinsics in the compiler.
* Please use "carm -?i" to get an up to date list of all intrinsics,
* Including the CMSIS ones.
*/
#endif
/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
#endif /* __CORE_CMINSTR_H */
bsp/mb9bf506r/libraries/CMSIS/RTOS/cmsis_os.h 0 → 100644
浏览文件 @ cbd32a0c
此差异已折叠。
bsp/mb9bf506r/CMSIS/system_mb9bf50x.h → bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Include/mcu.h
浏览文件 @ cbd32a0c
......@@ -30,42 +30,33 @@
/* */
/* (V1.5) */
/************************************************************************/
#ifndef _SYSTEM_MB9BF50X_H_
#define _SYSTEM_MB9BF50X_H_
#ifdef __cplusplus
extern "C" {
#endif
#include <stdint.h>
extern uint32_t SystemCoreClock; /*!< System Clock Frequency (Core Clock) */
/**
* Initialize the system
*
* @param none
* @return none
*
* @brief Setup the microcontroller system.
* Initialize the System and update the SystemCoreClock variable.
*/
extern void SystemInit (void);
******************************************************************************
** \file mcu.h
**
** Header File for device dependent includes
**
** History:
** 2011-05-19 V1.00 MWi first version
**
******************************************************************************/
/**
* Update SystemCoreClock variable
*
* @param none
* @return none
*
* @brief Updates the SystemCoreClock with current core Clock
* retrieved from cpu registers.
*/
extern void SystemCoreClockUpdate (void);
******************************************************************************
** \brief MCU header file include
**
******************************************************************************/
#ifndef _MB9BF506R_H_
#include "mb9bf506r.h"
#endif
#ifdef __cplusplus
}
/**
******************************************************************************
** \brief MCU system start-up header file include
**
******************************************************************************/
#ifndef _SYSTEM_MB9BF50X_H_
#include "system_mb9bf50x.h"
#endif
#endif /* __SYSTEM_MB9BF50X_H */
bsp/mb9bf506r/CMSIS/start_rvds.S → bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/ARM/startup_mb9bf50x.S
浏览文件 @ cbd32a0c
; /*
; * File : start_rvds.s
; * This file is part of RT-Thread RTOS
; * COPYRIGHT (C) 2009 - 2011, RT-Thread Development Team
; *
; * The license and distribution terms for this file may be
; * found in the file LICENSE in this distribution or at
; * http://www.rt-thread.org/license/LICENSE
; *
; * Change Logs:
; * Date Author Notes
; * 2011-02-23 Bernard first implementation
; */
;* <<< Use Configuration Wizard in Context Menu >>>
; Amount of memory (in bytes) allocated for Stack
; Tailor this value to your application needs
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
;/************************************************************************/
;/* (C) Fujitsu Semiconductor Europe GmbH (FSEU) */
;/* */
;/* The following software deliverable is intended for and must only be */
;/* used for reference and in an evaluation laboratory environment. */
;/* It is provided on an as-is basis without charge and is subject to */
;/* alterations. */
;/* It is the user's obligation to fully test the software in its */
;/* environment and to ensure proper functionality, qualification and */
;/* compliance with component specifications. */
;/* */
;/* In the event the software deliverable includes the use of open */
;/* source components, the provisions of the governing open source */
;/* license agreement shall apply with respect to such software */
;/* deliverable. */
;/* FSEU does not warrant that the deliverables do not infringe any */
;/* third party intellectual property right (IPR). In the event that */
;/* the deliverables infringe a third party IPR it is the sole */
;/* responsibility of the customer to obtain necessary licenses to */
;/* continue the usage of the deliverable. */
;/* */
;/* To the maximum extent permitted by applicable law FSEU disclaims all */
;/* warranties, whether express or implied, in particular, but not */
;/* limited to, warranties of merchantability and fitness for a */
;/* particular purpose for which the deliverable is not designated. */
;/* */
;/* To the maximum extent permitted by applicable law, FSEU's liability */
;/* is restricted to intentional misconduct and gross negligence. */
;/* FSEU is not liable for consequential damages. */
;/* */
;/* (V1.5) */
;/************************************************************************/
;/* Startup for ARM */
;/* Version V1.02 */
;/* Date 2011-01-12 */
;/* Target-mcu MB9B5xx */
;/************************************************************************/
; Stack Configuration
; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
Stack_Size EQU 0x00000200
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; Note: RT-Thread not use malloc/free in Keil MDK, therefore the heap size is 0.
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
; Heap Configuration
; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
Heap_Size EQU 0x00000000
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD MemManage_Handler ; MPU Fault Handler
DCD BusFault_Handler ; Bus Fault Handler
DCD UsageFault_Handler ; Usage Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD DebugMon_Handler ; Debug Monitor Handler
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
DCD CSV_Handler ; 0: Clock Super Visor
DCD SWDT_Handler ; 1: Software Watchdog Timer
DCD LVD_Handler ; 2: Low Voltage Detector
DCD MFT_WG_IRQHandler ; 3: Wave Form Generator / DTIF
DCD INT0_7_Handler ; 4: External Interrupt Request ch.0 to ch.7
DCD INT8_15_Handler ; 5: External Interrupt Request ch.8 to ch.15
DCD DT_Handler ; 6: Dual Timer / Quad Decoder
DCD MFS0RX_IRQHandler ; 7: MultiFunction Serial ch.0
DCD MFS0TX_IRQHandler ; 8: MultiFunction Serial ch.0
DCD MFS1RX_IRQHandler ; 9: MultiFunction Serial ch.1
DCD MFS1TX_IRQHandler ; 10: MultiFunction Serial ch.1
DCD MFS2RX_IRQHandler ; 11: MultiFunction Serial ch.2
DCD MFS2TX_IRQHandler ; 12: MultiFunction Serial ch.2
DCD MFS3RX_IRQHandler ; 13: MultiFunction Serial ch.3
DCD MFS3TX_IRQHandler ; 14: MultiFunction Serial ch.3
DCD MFS4RX_IRQHandler ; 15: MultiFunction Serial ch.4
DCD MFS4TX_IRQHandler ; 16: MultiFunction Serial ch.4
DCD MFS5RX_IRQHandler ; 17: MultiFunction Serial ch.5
DCD MFS5TX_IRQHandler ; 18: MultiFunction Serial ch.5
DCD MFS6RX_IRQHandler ; 19: MultiFunction Serial ch.6
DCD MFS6TX_IRQHandler ; 20: MultiFunction Serial ch.6
DCD MFS7RX_IRQHandler ; 21: MultiFunction Serial ch.7
DCD MFS7TX_IRQHandler ; 22: MultiFunction Serial ch.7
DCD PPG_Handler ; 23: PPG
DCD TIM_IRQHandler ; 24: OSC / PLL / Watch Counter
DCD ADC0_IRQHandler ; 25: ADC0
DCD ADC1_IRQHandler ; 26: ADC1
DCD ADC2_IRQHandler ; 27: ADC2
DCD MFT_FRT_IRQHandler ; 28: Free-run Timer
DCD MFT_IPC_IRQHandler ; 29: Input Capture
DCD MFT_OPC_IRQHandler ; 30: Output Compare
DCD BT_IRQHandler ; 31: Base Timer ch.0 to ch.7
DCD CAN0_IRQHandler ; 32: CAN ch.0
DCD CAN1_IRQHandler ; 33: CAN ch.1
DCD USBF_Handler ; 34: USB Function
DCD USB_Handler ; 35: USB Function / USB HOST
DCD DummyHandler ; 36: Reserved
DCD DummyHandler ; 37: Reserved
DCD DMAC0_Handler ; 38: DMAC ch.0
DCD DMAC1_Handler ; 39: DMAC ch.1
DCD DMAC2_Handler ; 40: DMAC ch.2
DCD DMAC3_Handler ; 41: DMAC ch.3
DCD DMAC4_Handler ; 42: DMAC ch.4
DCD DMAC5_Handler ; 43: DMAC ch.5
DCD DMAC6_Handler ; 44: DMAC ch.6
DCD DMAC7_Handler ; 45: DMAC ch.7
DCD DummyHandler ; 46: Reserved
DCD DummyHandler ; 47: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
__Vectors_Size EQU __Vectors_End - __Vectors
AREA |.text|, CODE, READONLY
AREA |.text|, CODE, READONLY
; Reset handler routine
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
LDR R1, = __initial_sp ; restore original stack pointer
MSR MSP, R1
IMPORT __main
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
EXPORT HardFault_Handler [WEAK]
B .
ENDP
MemManage_Handler\
PROC
EXPORT MemManage_Handler [WEAK]
EXPORT MemManage_Handler [WEAK]
B .
ENDP
BusFault_Handler\
PROC
EXPORT BusFault_Handler [WEAK]
EXPORT BusFault_Handler [WEAK]
B .
ENDP
UsageFault_Handler\
PROC
EXPORT UsageFault_Handler [WEAK]
EXPORT UsageFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
EXPORT SVC_Handler [WEAK]
B .
ENDP
DebugMon_Handler\
PROC
EXPORT DebugMon_Handler [WEAK]
EXPORT DebugMon_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT CSV_Handler [WEAK]
EXPORT CSV_Handler [WEAK]
EXPORT SWDT_Handler [WEAK]
EXPORT LVD_Handler [WEAK]
EXPORT MFT_WG_IRQHandler [WEAK]
......@@ -264,17 +290,25 @@ DMAC5_Handler
DMAC6_Handler
DMAC7_Handler
DummyHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
......@@ -286,6 +320,8 @@ __user_initial_stackheap
BX LR
ALIGN
ENDIF
END
bsp/mb9bf506r/libraries/Device/FUJISTU/MB9BF50x/Source/G++/startup_mb9bf50x.S 0 → 100644
浏览文件 @ cbd32a0c
/**************************************************************************//**
* @file startup_<Device>.s
* @brief CMSIS Cortex-M# Core Device Startup File for
* Device <Device>
* @version V3.01
* @date 06. March 2012
*
* @note Version CodeSourcery Sourcery G++ Lite (with CS3)
* Copyright (C) 2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/*
//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------
*/
/*
// <h> Stack Configuration
// <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Stack_Size, 0x00000400
.section ".stack", "w"
.align 3
.globl __cs3_stack_mem
.globl __cs3_stack_size
__cs3_stack_mem:
.if Stack_Size
.space Stack_Size
.endif
.size __cs3_stack_mem, . - __cs3_stack_mem
.set __cs3_stack_size, . - __cs3_stack_mem
/*
// <h> Heap Configuration
// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
// </h>
*/
.equ Heap_Size, 0x00000100
.section ".heap", "w"
.align 3
.globl __cs3_heap_start
.globl __cs3_heap_end
__cs3_heap_start:
.if Heap_Size
.space Heap_Size
.endif
__cs3_heap_end:
/* Vector Table */
.section ".cs3.interrupt_vector"
.globl __cs3_interrupt_vector_cortex_m
.type __cs3_interrupt_vector_cortex_m, %object
__cs3_interrupt_vector_cortex_m:
.long __cs3_stack /* Top of Stack */
.long __cs3_reset /* Reset Handler */
.long NMI_Handler /* NMI Handler */
.long HardFault_Handler /* Hard Fault Handler */
.long MemManage_Handler /* MPU Fault Handler */
.long BusFault_Handler /* Bus Fault Handler */
.long UsageFault_Handler /* Usage Fault Handler */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long 0 /* Reserved */
.long SVC_Handler /* SVCall Handler */
.long DebugMon_Handler /* Debug Monitor Handler */
.long 0 /* Reserved */
.long PendSV_Handler /* PendSV Handler */
.long SysTick_Handler /* SysTick Handler */
/* External Interrupts */
/* ToDo: Add here the vectors for the device specific external interrupts handler */
.long CSV_Handler /* 0: Clock Super Visor */
.long SWDT_Handler /* 1: Software Watchdog Timer */
.long LVD_Handler /* 2: Low Voltage Detector */
.long MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
.long INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
.long INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
.long DT_Handler /* 6: Dual Timer / Quad Decoder */
.long MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
.long MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
.long MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
.long MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
.long MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
.long MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
.long MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
.long MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
.long MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
.long MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
.long MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
.long MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
.long MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
.long MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
.long MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
.long MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
.long PPG_Handler /* 23: PPG */
.long TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
.long ADC0_IRQHandler /* 25: ADC0 */
.long ADC1_IRQHandler /* 26: ADC1 */
.long ADC2_IRQHandler /* 27: ADC2 */
.long MFT_FRT_IRQHandler /* 28: Free-run Timer */
.long MFT_IPC_IRQHandler /* 29: Input Capture */
.long MFT_OPC_IRQHandler /* 30: Output Compare */
.long BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
.long CAN0_IRQHandler /* 32: CAN ch.0 */
.long CAN1_IRQHandler /* 33: CAN ch.1 */
.long USBF_Handler /* 34: USB Function */
.long USB_Handler /* 35: USB Function / USB HOST */
.long RESERVED_1_IRQHandler /* 36: Reserved */
.long RESERVED_2_IRQHandler /* 37: Reserved */
.long DMAC0_Handler /* 38: DMAC ch.0 */
.long DMAC1_Handler /* 39: DMAC ch.1 */
.long DMAC2_Handler /* 40: DMAC ch.2 */
.long DMAC3_Handler /* 41: DMAC ch.3 */
.long DMAC4_Handler /* 42: DMAC ch.4 */
.long DMAC5_Handler /* 43: DMAC ch.5 */
.long DMAC6_Handler /* 44: DMAC ch.6 */
.long DMAC7_Handler /* 45: DMAC ch.7 */
.long RESERVED_3_IRQHandler /* 46: Reserved */
.long RESERVED_4_IRQHandler /* 47: Reserved */
.size __cs3_interrupt_vector_cortex_m, . - __cs3_interrupt_vector_cortex_m
.thumb
/* Reset Handler */
.section .cs3.reset,"x",%progbits
.thumb_func
.globl __cs3_reset_cortex_m
.type __cs3_reset_cortex_m, %function
__cs3_reset_cortex_m:
.fnstart
LDR R0, =SystemInit
BLX R0
LDR R0,=_start
BX R0
.pool
.cantunwind
.fnend
.size __cs3_reset_cortex_m,.-__cs3_reset_cortex_m
.section ".text"
/* Exception Handlers */
.weak NMI_Handler
.type NMI_Handler, %function
NMI_Handler:
B .
.size NMI_Handler, . - NMI_Handler
.weak HardFault_Handler
.type HardFault_Handler, %function
HardFault_Handler:
B .
.size HardFault_Handler, . - HardFault_Handler
.weak MemManage_Handler
.type MemManage_Handler, %function
MemManage_Handler:
B .
.size MemManage_Handler, . - MemManage_Handler
.weak BusFault_Handler
.type BusFault_Handler, %function
BusFault_Handler:
B .
.size BusFault_Handler, . - BusFault_Handler
.weak UsageFault_Handler
.type UsageFault_Handler, %function
UsageFault_Handler:
B .
.size UsageFault_Handler, . - UsageFault_Handler
.weak SVC_Handler
.type SVC_Handler, %function
SVC_Handler:
B .
.size SVC_Handler, . - SVC_Handler
.weak DebugMon_Handler
.type DebugMon_Handler, %function
DebugMon_Handler:
B .
.size DebugMon_Handler, . - DebugMon_Handler
.weak PendSV_Handler
.type PendSV_Handler, %function
PendSV_Handler:
B .
.size PendSV_Handler, . - PendSV_Handler
.weak SysTick_Handler
.type SysTick_Handler, %function
SysTick_Handler:
B .
.size SysTick_Handler, . - SysTick_Handler
/* IRQ Handlers */
/* ToDo: Add here the export definition for the device specific external interrupts handler */
/* ToDo: Add here the names for the device specific external interrupts handler */
.globl Default_Handler
.type Default_Handler, %function
Default_Handler:
B .
.size Default_Handler, . - Default_Handler
.macro IRQ handler
.weak \handler
.set \handler, Default_Handler
.endm
IRQ CSV_Handler /* 0: Clock Super Visor */
IRQ SWDT_Handler /* 1: Software Watchdog Timer */
IRQ LVD_Handler /* 2: Low Voltage Detector */
IRQ MFT_WG_IRQHandler /* 3: Wave Form Generator / DTIF */
IRQ INT0_7_Handler /* 4: External Interrupt Request ch.0 to ch.7 */
IRQ INT8_15_Handler /* 5: External Interrupt Request ch.8 to ch.15 */
IRQ DT_Handler /* 6: Dual Timer / Quad Decoder */
IRQ MFS0RX_IRQHandler /* 7: MultiFunction Serial ch.0 */
IRQ MFS0TX_IRQHandler /* 8: MultiFunction Serial ch.0 */
IRQ MFS1RX_IRQHandler /* 9: MultiFunction Serial ch.1 */
IRQ MFS1TX_IRQHandler /* 10: MultiFunction Serial ch.1 */
IRQ MFS2RX_IRQHandler /* 11: MultiFunction Serial ch.2 */
IRQ MFS2TX_IRQHandler /* 12: MultiFunction Serial ch.2 */
IRQ MFS3RX_IRQHandler /* 13: MultiFunction Serial ch.3 */
IRQ MFS3TX_IRQHandler /* 14: MultiFunction Serial ch.3 */
IRQ MFS4RX_IRQHandler /* 15: MultiFunction Serial ch.4 */
IRQ MFS4TX_IRQHandler /* 16: MultiFunction Serial ch.4 */
IRQ MFS5RX_IRQHandler /* 17: MultiFunction Serial ch.5 */
IRQ MFS5TX_IRQHandler /* 18: MultiFunction Serial ch.5 */
IRQ MFS6RX_IRQHandler /* 19: MultiFunction Serial ch.6 */
IRQ MFS6TX_IRQHandler /* 20: MultiFunction Serial ch.6 */
IRQ MFS7RX_IRQHandler /* 21: MultiFunction Serial ch.7 */
IRQ MFS7TX_IRQHandler /* 22: MultiFunction Serial ch.7 */
IRQ PPG_Handler /* 23: PPG */
IRQ TIM_IRQHandler /* 24: OSC / PLL / Watch Counter */
IRQ ADC0_IRQHandler /* 25: ADC0 */
IRQ ADC1_IRQHandler /* 26: ADC1 */
IRQ ADC2_IRQHandler /* 27: ADC2 */
IRQ MFT_FRT_IRQHandler /* 28: Free-run Timer */
IRQ MFT_IPC_IRQHandler /* 29: Input Capture */
IRQ MFT_OPC_IRQHandler /* 30: Output Compare */
IRQ BT_IRQHandler /* 31: Base Timer ch.0 to ch.7 */
IRQ CAN0_IRQHandler /* 32: CAN ch.0 */
IRQ CAN1_IRQHandler /* 33: CAN ch.1 */
IRQ USBF_Handler /* 34: USB Function */
IRQ USB_Handler /* 35: USB Function / USB HOST */
IRQ RESERVED_1_IRQHandler /* 36: Reserved */
IRQ RESERVED_2_IRQHandler /* 37: Reserved */
IRQ DMAC0_Handler /* 38: DMAC ch.0 */
IRQ DMAC1_Handler /* 39: DMAC ch.1 */
IRQ DMAC2_Handler /* 40: DMAC ch.2 */
IRQ DMAC3_Handler /* 41: DMAC ch.3 */
IRQ DMAC4_Handler /* 42: DMAC ch.4 */
IRQ DMAC5_Handler /* 43: DMAC ch.5 */
IRQ DMAC6_Handler /* 44: DMAC ch.6 */
IRQ DMAC7_Handler /* 45: DMAC ch.7 */
IRQ RESERVED_3_IRQHandler /* 46: Reserved */
IRQ RESERVED_4_IRQHandler /* 47: Reserved */
.end
bsp/mb9bf506r/project.ewp
浏览文件 @ cbd32a0c
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bsp/mb9bf506r/project.uvopt
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bsp/mb9bf506r/project.uvproj
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bsp/mb9bf506r/rtthread-mb9bf506.ld
浏览文件 @ cbd32a0c
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