add display controller driver for LS1B demo board

git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1672 bbd45198-f89e-11dd-88c7-29a3b14d5316

bsp/ls1bdev/SConscript

@@ -5,6 +5,9 @@ src_bsp = ['application.c', 'startup.c', 'board.c']
 
 src_drv = ['uart.c']
     
+if GetDepend('RT_USING_RTGUI'):
+    src_drv += ['display_controller.c']
+        
 src	= File(src_bsp + src_drv)
 CPPPATH = [GetCurrentDir()]
 group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)

bsp/ls1bdev/SConstruct

@@ -21,6 +21,9 @@ Export('rtconfig')
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT)
     
+if GetDepend('RT_USING_RTGUI'):
+    objs = objs + SConscript(RTT_ROOT + '/examples/gui/SConscript', variant_dir='build/examples/gui', duplicate=0)
+    
 # build program 
 env.Program(TARGET, objs)
 

bsp/ls1bdev/application.c

@@ -16,8 +16,33 @@
 #include <rtthread.h>
 #include <ls1b.h>
 
+#ifdef RT_USING_RTGUI
+#include <rtgui/rtgui.h>
+extern void rt_hw_dc_init(void);
+#endif
+
 void rt_init_thread_entry(void* parameter)
 {
+#ifdef RT_USING_RTGUI
+	{
+		rt_device_t dc;
+
+		/* init Display Controller */
+		rt_hw_dc_init();
+			
+		/* re-init device driver */
+		rt_device_init_all();
+	
+		/* find Display Controller device */
+		dc = rt_device_find("dc");
+	
+		/* set Display Controller device as rtgui graphic driver */		
+		rtgui_graphic_set_device(dc);
+	
+		/* startup rtgui */
+		rtgui_startup();
+	}
+#endif
 }
 
 int rt_application_init()

bsp/ls1bdev/display_controller.c

+/*
+ * File      : display_controller.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-09     lgnq         first version for LS1B DC
+ */
+
+#include <rtthread.h>
+#include "display_controller.h"
+
+struct vga_struct vga_mode[] =
+{
+	{/*"640x480_70.00"*/    28560,  640,    664,    728,    816,    480,    481,    484,    500,    },
+	{/*"640x640_60.00"*/	33100,	640,	672,	736,	832,	640,	641,	644,	663,	},
+	{/*"640x768_60.00"*/	39690,	640,	672,	736,	832,	768,	769,	772,	795,	},
+	{/*"640x800_60.00"*/	42130,	640,	680,	744,	848,	800,	801,	804,	828,	},
+	{/*"800x480_70.00"*/    35840,  800,    832,    912,    1024,   480,    481,    484,    500,    },
+	{/*"800x600_60.00"*/	38220,	800,	832,	912,	1024,	600,	601,	604,	622,	},
+	{/*"800x640_60.00"*/	40730,	800,	832,	912,	1024,	640,	641,	644,	663,	},
+	{/*"832x600_60.00"*/	40010,	832,	864,	952,	1072,	600,	601,	604,	622,	},
+	{/*"832x608_60.00"*/	40520,	832,	864,	952,	1072,	608,	609,	612,	630,	},
+	{/*"1024x480_60.00"*/	38170,	1024,	1048,	1152,	1280,	480,	481,	484,	497,	},
+	{/*"1024x600_60.00"*/	48960,	1024,	1064,	1168,	1312,	600,	601,	604,	622,	},
+	{/*"1024x640_60.00"*/	52830,	1024,	1072,	1176,	1328,	640,	641,	644,	663,	},
+	{/*"1024x768_60.00"*/	64110,	1024,	1080,	1184,	1344,	768,	769,	772,	795,	},
+	{/*"1152x764_60.00"*/   71380,  1152,   1208,   1328,   1504,   764,    765,    768,    791,    },
+	{/*"1280x800_60.00"*/   83460,  1280,   1344,   1480,   1680,   800,    801,    804,    828,    },
+	{/*"1280x1024_55.00"*/  98600,  1280,   1352,   1488,   1696,   1024,   1025,   1028,   1057,   },
+	{/*"1440x800_60.00"*/   93800,  1440,   1512,   1664,   1888,   800,    801,    804,    828,    },
+	{/*"1440x900_67.00"*/   120280, 1440,   1528,   1680,   1920,   900,    901,    904,    935,    },
+};
+
+ALIGN(16)
+volatile rt_uint16_t _rt_framebuffer[FB_YSIZE][FB_XSIZE];
+static struct rt_device_graphic_info _dc_info;
+
+#define abs(x) ((x<0)?(-x):x)
+#define min(a,b) ((a<b)?a:b)
+
+int caclulate_freq(long long XIN, long long PCLK)
+{
+	int i;
+	long long clk, clk1;
+	int start, end;
+	int mi;
+	int pll,ctrl,div,div1,frac;
+
+	pll = PLL_FREQ;
+	ctrl = PLL_DIV_PARAM;
+	rt_kprintf("pll=0x%x, ctrl=0x%x\n", pll, ctrl);
+//	rt_kprintf("cpu freq is %d\n", tgt_pipefreq());
+	start = -1;
+	end = 1;
+
+	for (i=start; i<=end; i++)
+	{
+		clk = (12+i+(pll&0x3f))*33333333/2;
+		div = clk/(long)PCLK/1000;
+		clk1 = (12+i+1+(pll&0x3f))*33333333/2;
+		div1 = clk1/(long)PCLK/1000;
+		if (div!=div1)
+			break;
+	}
+
+	if (div!=div1)
+	{
+		frac = ((PCLK*1000*div1)*2*1024/33333333 - (12+i+(pll&0x3f))*1024)&0x3ff;
+		pll = (pll & ~0x3ff3f)|(frac<<8)|((pll&0x3f)+i);
+		ctrl = ctrl&~(0x1f<<26)|(div1<<26)|(1<<31);
+	}
+	else
+	{
+		clk = (12+start+(pll&0x3f))*33333333/2;
+		clk1 = (12+end+(pll&0x3f))*33333333/2;
+		if (abs((long)clk/div/1000-PCLK)<abs((long)clk1/(div+1)/1000-PCLK))
+		{
+			pll = (pll & ~0x3ff3f)|((pll&0x3f)+start);
+			ctrl = ctrl&~(0x1f<<26)|(div<<26)|(1<<31);
+		}
+		else
+		{
+			pll = (pll & ~0x3ff3f)|((pll&0x3f)+end);
+			ctrl = ctrl&~(0x1f<<26)|((div+1)<<26)|(1<<31);
+		}
+	}
+
+	rt_kprintf("new pll=0x%x, ctrl=0x%x\n", pll, ctrl);
+	ctrl |= 0x2a00;
+	PLL_DIV_PARAM = ctrl; 
+	PLL_FREQ = pll;
+	rt_thread_delay(10);
+//	initserial(0);
+//	_probe_frequencies();
+//	rt_kprintf("cpu freq is %d\n",tgt_pipefreq());
+	return 0;
+}
+
+static rt_err_t rt_dc_init(rt_device_t dev)
+{
+	int i, out, mode=-1;
+	int val;
+
+	for (i=0; i<sizeof(vga_mode)/sizeof(struct vga_struct); i++)
+	{
+		if (vga_mode[i].hr == FB_XSIZE && vga_mode[i].vr == FB_YSIZE)
+		{
+			mode=i;
+#ifdef LS1FSOC
+//			out = caclulatefreq(APB_CLK/1000,vga_mode[i].pclk);
+//			rt_kprintf("out=%x\n",out);
+			/*inner gpu dc logic fifo pll ctrl,must large then outclk*/
+//			*(volatile int *)0xbfd00414 = out+1;
+			/*output pix1 clock  pll ctrl*/
+//			*(volatile int *)0xbfd00410 = out;
+			/*output pix2 clock pll ctrl */
+//			*(volatile int *)0xbfd00424 = out;
+#else
+			caclulate_freq(APB_CLK/1000, vga_mode[i].pclk);
+#endif
+			break;
+		}
+	}
+
+	if (mode<0)
+	{
+		rt_kprintf("\n\n\nunsupported framebuffer resolution\n\n\n");
+		return;
+	}
+
+	DC_FB_CONFIG = 0x0;
+	DC_FB_CONFIG = 0x3; //	// framebuffer configuration RGB565
+ 	DC_FB_BUFFER_ADDR0 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
+	DC_FB_BUFFER_ADDR1 = (rt_uint32_t)_rt_framebuffer - 0x80000000;
+	DC_DITHER_CONFIG = 0x0;
+	DC_DITHER_TABLE_LOW = 0x0;
+	DC_DITHER_TABLE_HIGH = 0x0;
+	DC_PANEL_CONFIG = 0x80001311;
+	DC_PANEL_TIMING = 0x0;
+
+	DC_HDISPLAY = (vga_mode[mode].hfl<<16) | vga_mode[mode].hr;
+	DC_HSYNC = 0x40000000 | (vga_mode[mode].hse<<16) | vga_mode[mode].hss;
+	DC_VDISPLAY = (vga_mode[mode].vfl<<16) | vga_mode[mode].vr;
+	DC_VSYNC = 0x40000000 | (vga_mode[mode].vse<<16) | vga_mode[mode].vss;
+
+#if defined(CONFIG_VIDEO_32BPP)
+	DC_FB_CONFIG = 0x00100104;
+	DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
+#elif defined(CONFIG_VIDEO_16BPP)
+	DC_FB_CONFIG = 0x00100103;
+	DC_FB_BUFFER_STRIDE = (FB_XSIZE*2+255)&(~255);
+#elif defined(CONFIG_VIDEO_15BPP)
+	DC_FB_CONFIG = 0x00100102;
+	DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
+#elif defined(CONFIG_VIDEO_12BPP)
+	DC_FB_CONFIG = 0x00100101;
+	DC_FB_BUFFER_STRIDE = FB_XSIZE*2;
+#else  //640x480-32Bits
+	DC_FB_CONFIG = 0x00100104;
+	DC_FB_BUFFER_STRIDE = FB_XSIZE*4;
+#endif //32Bits
+
+#ifdef LS1GSOC
+	/*fix ls1g dc
+	 *first switch to tile mode
+	 *change origin register to 0
+	 *goback nomal mode
+	 */
+	{
+		val = DC_FB_CONFIG;
+		DC_FB_CONFIG = val | 0x10;
+		DC_FB_BUFFER_ORIGIN = 0;
+		DC_FB_BUFFER_ORIGIN;
+		rt_thread_delay(10);
+		DC_FB_CONFIG;
+		DC_FB_CONFIG = val;
+	}
+#endif
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_dc_control(rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	switch (cmd)
+	{
+	case RTGRAPHIC_CTRL_RECT_UPDATE:
+		break;
+	case RTGRAPHIC_CTRL_POWERON:
+		break;
+	case RTGRAPHIC_CTRL_POWEROFF:
+		break;
+	case RTGRAPHIC_CTRL_GET_INFO:		
+		rt_memcpy(args, &_dc_info, sizeof(_dc_info));
+		break;
+	case RTGRAPHIC_CTRL_SET_MODE:
+		break;
+	}
+
+	return RT_EOK;
+}
+
+void rt_hw_dc_init(void)
+{
+	rt_device_t dc = rt_malloc(sizeof(struct rt_device));
+	if (dc == RT_NULL) 
+	{
+		rt_kprintf("dc == RT_NULL\n");
+		return; /* no memory yet */
+	}
+
+	_dc_info.bits_per_pixel = 16;
+	_dc_info.pixel_format = RTGRAPHIC_PIXEL_FORMAT_RGB565P;
+	_dc_info.framebuffer = (rt_uint8_t*)HW_FB_ADDR;
+	_dc_info.width = FB_XSIZE;
+	_dc_info.height = FB_YSIZE;
+
+	/* init device structure */
+	dc->type = RT_Device_Class_Graphic;
+	dc->init = rt_dc_init;
+	dc->open = RT_NULL;
+	dc->close = RT_NULL;
+	dc->control = rt_dc_control;
+	dc->user_data = (void*)&_dc_info;
+	
+	/* register Display Controller device to RT-Thread */
+	rt_device_register(dc, "dc", RT_DEVICE_FLAG_RDWR);
+}

bsp/ls1bdev/display_controller.h

+/*
+ * File      : display_controller.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2011-08-08     lgnq         first version for LS1B
+ */
+ 
+#ifndef __DISPLAY_CONTROLLER_H__
+#define __DISPLAY_CONTROLLER_H__
+
+#include <rtthread.h>
+#include "ls1b.h"
+
+#define DC_BASE					0xBC301240  //Display Controller
+
+/* Frame Buffer registers */
+#define DC_FB_CONFIG			__REG32(DC_BASE + 0x000)
+#define DC_FB_BUFFER_ADDR0		__REG32(DC_BASE + 0x020)
+#define DC_FB_BUFFER_STRIDE		__REG32(DC_BASE + 0x040)
+#define DC_FB_BUFFER_ORIGIN		__REG32(DC_BASE + 0x060)
+#define DC_DITHER_CONFIG		__REG32(DC_BASE + 0x120)
+#define DC_DITHER_TABLE_LOW		__REG32(DC_BASE + 0x140)
+#define DC_DITHER_TABLE_HIGH	__REG32(DC_BASE + 0x160)
+#define DC_PANEL_CONFIG			__REG32(DC_BASE + 0x180)
+#define DC_PANEL_TIMING			__REG32(DC_BASE + 0x1A0)
+#define DC_HDISPLAY				__REG32(DC_BASE + 0x1C0)
+#define DC_HSYNC				__REG32(DC_BASE + 0x1E0)
+#define DC_VDISPLAY				__REG32(DC_BASE + 0x240)
+#define DC_VSYNC				__REG32(DC_BASE + 0x260)
+#define DC_FB_BUFFER_ADDR1		__REG32(DC_BASE + 0x340)
+
+/* Display Controller driver for 1024x768 16bit */
+#define FB_XSIZE		1024
+#define FB_YSIZE		768
+#define CONFIG_VIDEO_16BPP
+
+#define APB_CLK 33333333
+
+#define K1BASE				0xA0000000
+#define KSEG1(addr)			((void *)(K1BASE | (rt_uint32_t)(addr)))
+#define HW_FB_ADDR			KSEG1(_rt_framebuffer)
+#define HW_FB_PIXEL(x, y)	*(volatile rt_uint16_t*)((rt_uint8_t*)HW_FB_ADDR + (y * FB_XSIZE * 2) + x * 2)
+
+struct vga_struct
+{
+	long pclk;
+	int hr,hss,hse,hfl;
+	int vr,vss,vse,vfl;
+};
+
+#endif

bsp/ls1bdev/rtconfig.h

@@ -140,7 +140,7 @@
 #define RT_LWIP_ETHTHREAD_STACKSIZE		512
 
 /* SECTION: RT-Thread/GUI */
-/* #define RT_USING_RTGUI */
+#define RT_USING_RTGUI
 
 /* name length of RTGUI object */
 #define RTGUI_NAME_MAX		12

bsp/ls1bdev/uart.c

@@ -15,7 +15,7 @@
 #include <rthw.h>
 #include <rtthread.h>
 
-#include "ls1b.h"
+#include "uart.h"
 
 /**
  * @addtogroup Loongson LS1B
@@ -24,30 +24,6 @@
 /*@{*/
 #if defined(RT_USING_UART) && defined(RT_USING_DEVICE)
 
-/* UART interrupt enable register value */
-#define UARTIER_IME		(1 << 3)
-#define UARTIER_ILE		(1 << 2) 
-#define UARTIER_ITXE	(1 << 1)
-#define UARTIER_IRXE	(1 << 0)
-
-/* UART line control register value */
-#define UARTLCR_DLAB	(1 << 7)
-#define UARTLCR_BCB		(1 << 6)
-#define UARTLCR_SPB		(1 << 5)
-#define UARTLCR_EPS		(1 << 4)
-#define UARTLCR_PE		(1 << 3)
-#define UARTLCR_SB		(1 << 2)
-
-/* UART line status register value */
-#define UARTLSR_ERROR	(1 << 7)
-#define UARTLSR_TE		(1 << 6)
-#define UARTLSR_TFE		(1 << 5)
-#define UARTLSR_BI		(1 << 4)
-#define UARTLSR_FE		(1 << 3)
-#define UARTLSR_PE		(1 << 2)
-#define UARTLSR_OE		(1 << 1)
-#define UARTLSR_DR		(1 << 0)
-
 struct rt_uart_ls1b
 {
 	struct rt_device parent;

bsp/ls1bdev/uart.h

 /*
- * File      : board.c
+ * File      : uart.h
  * This file is part of RT-Thread RTOS
  * COPYRIGHT (C) 2006-2011, RT-Thread Develop Team
  *
@@ -9,12 +9,89 @@
  *
  * Change Logs:
  * Date           Author       Notes
- * 2011-08-08     lgnq         first version
+ * 2011-08-08     lgnq         first version for LS1B
  */
-
 #ifndef __UART_H__
 #define __UART_H__
 
+#include "ls1b.h"
+
+#define UART0_BASE			0xBFE40000
+#define UART0_1_BASE		0xBFE41000
+#define UART0_2_BASE		0xBFE42000
+#define UART0_3_BASE		0xBFE43000
+#define UART1_BASE			0xBFE44000
+#define UART1_1_BASE		0xBFE45000
+#define UART1_2_BASE		0xBFE46000
+#define UART1_3_BASE		0xBFE47000
+#define UART2_BASE			0xBFE48000
+#define UART3_BASE			0xBFE4C000
+#define UART4_BASE			0xBFE6C000
+#define UART5_BASE			0xBFE7C000
+
+/* UART registers */
+#define UART_DAT(base)		__REG8(base + 0x00)
+#define UART_IER(base)		__REG8(base + 0x01)
+#define UART_IIR(base)		__REG8(base + 0x02)
+#define UART_FCR(base)		__REG8(base + 0x02)
+#define UART_LCR(base)		__REG8(base + 0x03)
+#define UART_MCR(base)		__REG8(base + 0x04)
+#define UART_LSR(base)		__REG8(base + 0x05)
+#define UART_MSR(base)		__REG8(base + 0x06)
+
+#define UART_LSB(base)		__REG8(base + 0x00)
+#define UART_MSB(base)		__REG8(base + 0x01)
+
+/* UART0 registers */
+#define UART0_DAT			__REG8(UART0_BASE + 0x00)
+#define UART0_IER			__REG8(UART0_BASE + 0x01)
+#define UART0_IIR			__REG8(UART0_BASE + 0x02)
+#define UART0_FCR			__REG8(UART0_BASE + 0x02)
+#define UART0_LCR			__REG8(UART0_BASE + 0x03)
+#define UART0_MCR			__REG8(UART0_BASE + 0x04)
+#define UART0_LSR			__REG8(UART0_BASE + 0x05)
+#define UART0_MSR			__REG8(UART0_BASE + 0x06)
+
+#define UART0_LSB			__REG8(UART0_BASE + 0x00)
+#define UART0_MSB			__REG8(UART0_BASE + 0x01)
+
+/* UART1 registers */
+#define UART1_DAT			__REG8(UART1_BASE + 0x00)
+#define UART1_IER			__REG8(UART1_BASE + 0x01)
+#define UART1_IIR			__REG8(UART1_BASE + 0x02)
+#define UART1_FCR			__REG8(UART1_BASE + 0x02)
+#define UART1_LCR			__REG8(UART1_BASE + 0x03)
+#define UART1_MCR			__REG8(UART1_BASE + 0x04)
+#define UART1_LSR			__REG8(UART1_BASE + 0x05)
+#define UART1_MSR			__REG8(UART1_BASE + 0x06)
+
+#define UART1_LSB			__REG8(UART1_BASE + 0x00)
+#define UART1_MSB			__REG8(UART1_BASE + 0x01)
+
+/* UART interrupt enable register value */
+#define UARTIER_IME		(1 << 3)
+#define UARTIER_ILE		(1 << 2) 
+#define UARTIER_ITXE	(1 << 1)
+#define UARTIER_IRXE	(1 << 0)
+
+/* UART line control register value */
+#define UARTLCR_DLAB	(1 << 7)
+#define UARTLCR_BCB		(1 << 6)
+#define UARTLCR_SPB		(1 << 5)
+#define UARTLCR_EPS		(1 << 4)
+#define UARTLCR_PE		(1 << 3)
+#define UARTLCR_SB		(1 << 2)
+
+/* UART line status register value */
+#define UARTLSR_ERROR	(1 << 7)
+#define UARTLSR_TE		(1 << 6)
+#define UARTLSR_TFE		(1 << 5)
+#define UARTLSR_BI		(1 << 4)
+#define UARTLSR_FE		(1 << 3)
+#define UARTLSR_PE		(1 << 2)
+#define UARTLSR_OE		(1 << 1)
+#define UARTLSR_DR		(1 << 0)
+
 void rt_hw_uart_init(void);
 
 #endif

libcpu/mips/loongson_1b/ls1b.h

@@ -11,6 +11,7 @@
  * Date           Author       Notes
  * 2011-08-08     lgnq         first version
  */
+
 #ifndef __LS1B_H__
 #define __LS1B_H__
 
@@ -113,16 +114,6 @@ struct ls1b_cop_regs
 #define GMAC0_DMA_BASE		0xBFE11000
 #define GMAC1_BASE			0xBFE20000
 #define GMAC1_DMA_BASE		0xBFE21000
-#define UART0_BASE			0xBFE40000
-#define UART0_1_BASE		0xBFE41000
-#define UART0_2_BASE		0xBFE42000
-#define UART0_3_BASE		0xBFE43000
-#define UART1_BASE			0xBFE44000
-#define UART1_1_BASE		0xBFE45000
-#define UART1_2_BASE		0xBFE46000
-#define UART1_3_BASE		0xBFE47000
-#define UART2_BASE			0xBFE48000
-#define UART3_BASE			0xBFE4C000
 #define I2C0_BASE			0xBFE58000
 #define PWM0_BASE			0xBFE5C000
 #define PWM1_BASE			0xBFE5C010
@@ -131,77 +122,18 @@ struct ls1b_cop_regs
 #define WDT_BASE			0xBFE5C060
 #define RTC_BASE			0xBFE64000
 #define I2C1_BASE			0xBFE68000
-#define UART4_BASE			0xBFE6C000
 #define I2C2_BASE			0xBFE70000
 #define AC97_BASE			0xBFE74000
 #define NAND_BASE			0xBFE78000
-#define UART5_BASE			0xBFE7C000
 #define SPI_BASE			0xBFE80000
 #define CAN1_BASE			0xBF004300
 #define CAN0_BASE			0xBF004400
 
-#define DC_BASE				0xBC301240  //Display Control
-
-/* UART registers */
-#define UART_DAT(base)		__REG8(base + 0x00)
-#define UART_IER(base)		__REG8(base + 0x01)
-#define UART_IIR(base)		__REG8(base + 0x02)
-#define UART_FCR(base)		__REG8(base + 0x02)
-#define UART_LCR(base)		__REG8(base + 0x03)
-#define UART_MCR(base)		__REG8(base + 0x04)
-#define UART_LSR(base)		__REG8(base + 0x05)
-#define UART_MSR(base)		__REG8(base + 0x06)
-
-#define UART_LSB(base)		__REG8(base + 0x00)
-#define UART_MSB(base)		__REG8(base + 0x01)
-
-/* UART0 registers */
-#define UART0_DAT			__REG8(UART0_BASE + 0x00)
-#define UART0_IER			__REG8(UART0_BASE + 0x01)
-#define UART0_IIR			__REG8(UART0_BASE + 0x02)
-#define UART0_FCR			__REG8(UART0_BASE + 0x02)
-#define UART0_LCR			__REG8(UART0_BASE + 0x03)
-#define UART0_MCR			__REG8(UART0_BASE + 0x04)
-#define UART0_LSR			__REG8(UART0_BASE + 0x05)
-#define UART0_MSR			__REG8(UART0_BASE + 0x06)
-
-#define UART0_LSB			__REG8(UART0_BASE + 0x00)
-#define UART0_MSB			__REG8(UART0_BASE + 0x01)
-
-/* UART1 registers */
-#define UART1_DAT			__REG8(UART1_BASE + 0x00)
-#define UART1_IER			__REG8(UART1_BASE + 0x01)
-#define UART1_IIR			__REG8(UART1_BASE + 0x02)
-#define UART1_FCR			__REG8(UART1_BASE + 0x02)
-#define UART1_LCR			__REG8(UART1_BASE + 0x03)
-#define UART1_MCR			__REG8(UART1_BASE + 0x04)
-#define UART1_LSR			__REG8(UART1_BASE + 0x05)
-#define UART1_MSR			__REG8(UART1_BASE + 0x06)
-
-#define UART1_LSB			__REG8(UART1_BASE + 0x00)
-#define UART1_MSB			__REG8(UART1_BASE + 0x01)
-
 /* Watch Dog registers */
 #define WDT_EN				__REG32(WDT_BASE + 0x00)
 #define WDT_SET				__REG32(WDT_BASE + 0x04)
 #define WDT_TIMER			__REG32(WDT_BASE + 0x08)
 
-/* Frame Buffer registers */
-#define DC_FB_CONFIG			__REG32(DC_BASE + 0x000)
-#define DC_FB_BUFFER_ADDR0		__REG32(DC_BASE + 0x020)
-#define DC_FB_BUFFER_STRIDE		__REG32(DC_BASE + 0x040)
-#define DC_FB_BUFFER_ORIGIN		__REG32(DC_BASE + 0x060)
-#define DC_DITHER_CONFIG		__REG32(DC_BASE + 0x120)
-#define DC_DITHER_TABLE_LOW		__REG32(DC_BASE + 0x140)
-#define DC_DITHER_TABLE_HIGH	__REG32(DC_BASE + 0x160)
-#define DC_PANEL_CONFIG			__REG32(DC_BASE + 0x180)
-#define DC_PANEL_TIMING			__REG32(DC_BASE + 0x1A0)
-#define DC_HDISPLAY				__REG32(DC_BASE + 0x1C0)
-#define DC_HSYNC				__REG32(DC_BASE + 0x1E0)
-#define DC_VDISPLAY				__REG32(DC_BASE + 0x240)
-#define DC_VSYNC				__REG32(DC_BASE + 0x260)
-#define DC_FB_BUFFER_ADDR1		__REG32(DC_BASE + 0x340)
-
 #define PLL_FREQ 				__REG32(0xbfe78030)
 #define PLL_DIV_PARAM 			__REG32(0xbfe78034)