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体验新版 GitCode,发现更多精彩内容 >>
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bd855186
编写于
3月 18, 2020
作者:
S
supperthomas
浏览文件
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差异文件
Merge branch 'master' of github.com:supperthomas/rt-thread into back
上级
56a2e831
ff302f44
变更
3
隐藏空白更改
内联
并排
Showing
3 changed file
with
2 addition
and
166 deletion
+2
-166
bsp/stm32/stm32l496-st-nucleo/board/board.c
bsp/stm32/stm32l496-st-nucleo/board/board.c
+0
-164
bsp/stm32/stm32l496-st-nucleo/figures/board.png
bsp/stm32/stm32l496-st-nucleo/figures/board.png
+0
-0
bsp/stm32/stm32l496-st-nucleo/project.uvoptx
bsp/stm32/stm32l496-st-nucleo/project.uvoptx
+2
-2
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bsp/stm32/stm32l496-st-nucleo/board/board.c
浏览文件 @
bd855186
...
...
@@ -82,167 +82,3 @@ void SystemClock_Config(void)
HAL_RCCEx_EnableMSIPLLMode
();
}
#ifdef RT_USING_PM
void
SystemClock_MSI_ON
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
/* Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
MSIState
=
RCC_MSI_ON
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
RT_ASSERT
(
0
);
}
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_SYSCLK
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_MSI
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_1
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_MSI_OFF
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
HSIState
=
RCC_MSI_OFF
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_NONE
;
/* No update on PLL */
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_80M
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
;
RCC_ClkInitTypeDef
RCC_ClkInitStruct
;
/**Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
20
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV2
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/**Initializes the CPU, AHB and APB busses clocks
*/
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_4
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_24M
(
void
)
{
RCC_OscInitTypeDef
RCC_OscInitStruct
;
RCC_ClkInitTypeDef
RCC_ClkInitStruct
;
/** Initializes the CPU, AHB and APB busses clocks */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_HSE
;
RCC_OscInitStruct
.
HSEState
=
RCC_HSE_ON
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_ON
;
RCC_OscInitStruct
.
PLL
.
PLLSource
=
RCC_PLLSOURCE_HSE
;
RCC_OscInitStruct
.
PLL
.
PLLM
=
1
;
RCC_OscInitStruct
.
PLL
.
PLLN
=
12
;
RCC_OscInitStruct
.
PLL
.
PLLP
=
RCC_PLLP_DIV7
;
RCC_OscInitStruct
.
PLL
.
PLLQ
=
RCC_PLLQ_DIV2
;
RCC_OscInitStruct
.
PLL
.
PLLR
=
RCC_PLLR_DIV4
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
Error_Handler
();
}
/** Initializes the CPU, AHB and APB busses clocks */
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_HCLK
|
RCC_CLOCKTYPE_SYSCLK
|
RCC_CLOCKTYPE_PCLK1
|
RCC_CLOCKTYPE_PCLK2
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_PLLCLK
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_1
)
!=
HAL_OK
)
{
Error_Handler
();
}
}
void
SystemClock_2M
(
void
)
{
RCC_ClkInitTypeDef
RCC_ClkInitStruct
=
{
0
};
RCC_OscInitTypeDef
RCC_OscInitStruct
=
{
0
};
/* MSI is enabled after System reset, update MSI to 2Mhz (RCC_MSIRANGE_5) */
RCC_OscInitStruct
.
OscillatorType
=
RCC_OSCILLATORTYPE_MSI
;
RCC_OscInitStruct
.
MSIState
=
RCC_MSI_ON
;
RCC_OscInitStruct
.
MSIClockRange
=
RCC_MSIRANGE_5
;
RCC_OscInitStruct
.
MSICalibrationValue
=
RCC_MSICALIBRATION_DEFAULT
;
RCC_OscInitStruct
.
PLL
.
PLLState
=
RCC_PLL_NONE
;
if
(
HAL_RCC_OscConfig
(
&
RCC_OscInitStruct
)
!=
HAL_OK
)
{
/* Initialization Error */
Error_Handler
();
}
/* Select MSI as system clock source and configure the HCLK, PCLK1 and PCLK2
clocks dividers */
RCC_ClkInitStruct
.
ClockType
=
RCC_CLOCKTYPE_SYSCLK
;
RCC_ClkInitStruct
.
SYSCLKSource
=
RCC_SYSCLKSOURCE_MSI
;
RCC_ClkInitStruct
.
AHBCLKDivider
=
RCC_SYSCLK_DIV1
;
RCC_ClkInitStruct
.
APB1CLKDivider
=
RCC_HCLK_DIV1
;
RCC_ClkInitStruct
.
APB2CLKDivider
=
RCC_HCLK_DIV1
;
if
(
HAL_RCC_ClockConfig
(
&
RCC_ClkInitStruct
,
FLASH_LATENCY_0
)
!=
HAL_OK
)
{
/* Initialization Error */
Error_Handler
();
}
}
/**
* @brief Configures system clock after wake-up from STOP: enable HSI, PLL
* and select PLL as system clock source.
* @param None
* @retval None
*/
void
SystemClock_ReConfig
(
uint8_t
mode
)
{
SystemClock_MSI_ON
();
switch
(
mode
)
{
case
PM_RUN_MODE_HIGH_SPEED
:
case
PM_RUN_MODE_NORMAL_SPEED
:
SystemClock_80M
();
break
;
case
PM_RUN_MODE_MEDIUM_SPEED
:
SystemClock_24M
();
break
;
case
PM_RUN_MODE_LOW_SPEED
:
SystemClock_2M
();
break
;
default:
break
;
}
// SystemClock_MSI_OFF();
}
#endif
bsp/stm32/stm32l496-st-nucleo/figures/board.png
查看替换文件 @
56a2e831
浏览文件 @
bd855186
466.4 KB
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|
H:
100.9 KB
|
W:
|
H:
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Onion skin
bsp/stm32/stm32l496-st-nucleo/project.uvoptx
浏览文件 @
bd855186
...
...
@@ -183,7 +183,7 @@
<Group>
<GroupName>
Kernel
</GroupName>
<tvExp>
0
</tvExp>
<tvExp>
1
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<cbSel>
0
</cbSel>
<RteFlg>
0
</RteFlg>
...
...
@@ -379,7 +379,7 @@
<Group>
<GroupName>
Drivers
</GroupName>
<tvExp>
0
</tvExp>
<tvExp>
1
</tvExp>
<tvExpOptDlg>
0
</tvExpOptDlg>
<cbSel>
0
</cbSel>
<RteFlg>
0
</RteFlg>
...
...
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