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9367bba6
编写于
1月 22, 2014
作者:
wuyangyong
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电子邮件补丁
差异文件
update CMSIS version to 3.20
上级
8fdbb7c9
变更
11
展开全部
隐藏空白更改
内联
并排
Showing
11 changed file
with
1063 addition
and
1055 deletion
+1063
-1055
components/CMSIS/Include/arm_common_tables.h
components/CMSIS/Include/arm_common_tables.h
+76
-21
components/CMSIS/Include/arm_math.h
components/CMSIS/Include/arm_math.h
+585
-836
components/CMSIS/Include/core_cm0.h
components/CMSIS/Include/core_cm0.h
+35
-20
components/CMSIS/Include/core_cm0plus.h
components/CMSIS/Include/core_cm0plus.h
+37
-22
components/CMSIS/Include/core_cm3.h
components/CMSIS/Include/core_cm3.h
+36
-21
components/CMSIS/Include/core_cm4.h
components/CMSIS/Include/core_cm4.h
+36
-21
components/CMSIS/Include/core_cm4_simd.h
components/CMSIS/Include/core_cm4_simd.h
+39
-15
components/CMSIS/Include/core_cmFunc.h
components/CMSIS/Include/core_cmFunc.h
+46
-26
components/CMSIS/Include/core_cmInstr.h
components/CMSIS/Include/core_cmInstr.h
+102
-32
components/CMSIS/Include/core_sc000.h
components/CMSIS/Include/core_sc000.h
+35
-20
components/CMSIS/Include/core_sc300.h
components/CMSIS/Include/core_sc300.h
+36
-21
未找到文件。
components/CMSIS/Include/arm_common_tables.h
浏览文件 @
9367bba6
/* ----------------------------------------------------------------------
* Copyright (C) 2010
ARM Limited. All rights reserved.
*
* $Date: 1
1. November 2010
* $Revision:
V1.0.2
*
* Project:
CMSIS DSP Library
* Title:
arm_common_tables.h
*
* Description:
This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
/* ----------------------------------------------------------------------
* Copyright (C) 2010
-2013 ARM Limited. All rights reserved.
*
* $Date: 1
7. January 2013
* $Revision:
V1.4.1
*
* Project:
CMSIS DSP Library
* Title:
arm_common_tables.h
*
* Description:
This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions
*
* Target Processor: Cortex-M4/Cortex-M3
*
* Version 1.0.2 2010/11/11
* Documentation updated.
*
* Version 1.0.1 2010/10/05
* Production release and review comments incorporated.
*
* Version 1.0.0 2010/09/20
* Production release and review comments incorporated.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions
* are met:
* - Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* - Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in
* the documentation and/or other materials provided with the
* distribution.
* - Neither the name of ARM LIMITED nor the names of its contributors
* may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
* -------------------------------------------------------------------- */
#ifndef _ARM_COMMON_TABLES_H
...
...
@@ -31,8 +48,46 @@ extern const q15_t armRecipTableQ15[64];
extern
const
q31_t
armRecipTableQ31
[
64
];
extern
const
q31_t
realCoefAQ31
[
1024
];
extern
const
q31_t
realCoefBQ31
[
1024
];
extern
const
float32_t
twiddleCoef
[
6144
];
extern
const
float32_t
twiddleCoef_16
[
32
];
extern
const
float32_t
twiddleCoef_32
[
64
];
extern
const
float32_t
twiddleCoef_64
[
128
];
extern
const
float32_t
twiddleCoef_128
[
256
];
extern
const
float32_t
twiddleCoef_256
[
512
];
extern
const
float32_t
twiddleCoef_512
[
1024
];
extern
const
float32_t
twiddleCoef_1024
[
2048
];
extern
const
float32_t
twiddleCoef_2048
[
4096
];
extern
const
float32_t
twiddleCoef_4096
[
8192
];
#define twiddleCoef twiddleCoef_4096
extern
const
q31_t
twiddleCoefQ31
[
6144
];
extern
const
q15_t
twiddleCoefQ15
[
6144
];
extern
const
float32_t
twiddleCoef_rfft_32
[
32
];
extern
const
float32_t
twiddleCoef_rfft_64
[
64
];
extern
const
float32_t
twiddleCoef_rfft_128
[
128
];
extern
const
float32_t
twiddleCoef_rfft_256
[
256
];
extern
const
float32_t
twiddleCoef_rfft_512
[
512
];
extern
const
float32_t
twiddleCoef_rfft_1024
[
1024
];
extern
const
float32_t
twiddleCoef_rfft_2048
[
2048
];
extern
const
float32_t
twiddleCoef_rfft_4096
[
4096
];
#define ARMBITREVINDEXTABLE__16_TABLE_LENGTH ((uint16_t)20 )
#define ARMBITREVINDEXTABLE__32_TABLE_LENGTH ((uint16_t)48 )
#define ARMBITREVINDEXTABLE__64_TABLE_LENGTH ((uint16_t)56 )
#define ARMBITREVINDEXTABLE_128_TABLE_LENGTH ((uint16_t)208 )
#define ARMBITREVINDEXTABLE_256_TABLE_LENGTH ((uint16_t)440 )
#define ARMBITREVINDEXTABLE_512_TABLE_LENGTH ((uint16_t)448 )
#define ARMBITREVINDEXTABLE1024_TABLE_LENGTH ((uint16_t)1800)
#define ARMBITREVINDEXTABLE2048_TABLE_LENGTH ((uint16_t)3808)
#define ARMBITREVINDEXTABLE4096_TABLE_LENGTH ((uint16_t)4032)
extern
const
uint16_t
armBitRevIndexTable16
[
ARMBITREVINDEXTABLE__16_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable32
[
ARMBITREVINDEXTABLE__32_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable64
[
ARMBITREVINDEXTABLE__64_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable128
[
ARMBITREVINDEXTABLE_128_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable256
[
ARMBITREVINDEXTABLE_256_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable512
[
ARMBITREVINDEXTABLE_512_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable1024
[
ARMBITREVINDEXTABLE1024_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable2048
[
ARMBITREVINDEXTABLE2048_TABLE_LENGTH
];
extern
const
uint16_t
armBitRevIndexTable4096
[
ARMBITREVINDEXTABLE4096_TABLE_LENGTH
];
#endif
/* ARM_COMMON_TABLES_H */
components/CMSIS/Include/arm_math.h
浏览文件 @
9367bba6
此差异已折叠。
点击以展开。
components/CMSIS/Include/core_cm0.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cm0.h
* @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File
* @version V3.
01
* @date
13. March 2012
* @version V3.
20
* @date
25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS CM0 definitions */
#define __CM0_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __CM0_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16) | \
__CM0_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
...
...
@@ -590,9 +605,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if
(
IRQn
<
0
)
{
return
((
uint32_t
)((
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for Cortex-M0 system interrupts */
return
((
uint32_t
)((
(
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for Cortex-M0 system interrupts */
else
{
return
((
uint32_t
)((
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts */
return
((
uint32_t
)((
(
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts */
}
...
...
@@ -640,9 +655,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
components/CMSIS/Include/core_cm0plus.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cm0plus.h
* @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File
* @version V3.
01
* @date 2
2. March 2012
* @version V3.
20
* @date 2
5. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS CM0P definitions */
#define __CM0PLUS_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16) | \
__CM0PLUS_CMSIS_VERSION_SUB)
/*!< CMSIS HAL version number */
...
...
@@ -361,8 +376,8 @@ typedef struct
#if (__VTOR_PRESENT == 1)
/* SCB Interrupt Control State Register Definitions */
#define SCB_VTOR_TBLOFF_Pos
7
/*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x
1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
/*!< SCB VTOR: TBLOFF Mask */
#define SCB_VTOR_TBLOFF_Pos
8
/*!< SCB VTOR: TBLOFF Position */
#define SCB_VTOR_TBLOFF_Msk (0x
FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
/*!< SCB VTOR: TBLOFF Mask */
#endif
/* SCB Application Interrupt and Reset Control Register Definitions */
...
...
@@ -701,9 +716,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if
(
IRQn
<
0
)
{
return
((
uint32_t
)((
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for Cortex-M0+
system interrupts */
return
((
uint32_t
)((
(
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for Cortex-M0
system interrupts */
else
{
return
((
uint32_t
)((
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts
*/
return
((
uint32_t
)((
(
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts
*/
}
...
...
@@ -751,9 +766,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
components/CMSIS/Include/core_cm3.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cm3.h
* @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File
* @version V3.
01
* @date 2
2. March 2012
* @version V3.
20
* @date 2
5. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS CM3 definitions */
#define __CM3_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __CM3_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | \
__CM3_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
...
...
@@ -636,14 +651,14 @@ typedef struct
__IO
uint32_t
TPR
;
/*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t
RESERVED2
[
15
];
__IO
uint32_t
TCR
;
/*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t
RESERVED3
[
29
];
uint32_t
RESERVED3
[
29
];
__O
uint32_t
IWR
;
/*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I
uint32_t
IRR
;
/*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO
uint32_t
IMCR
;
/*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t
RESERVED4
[
43
];
uint32_t
RESERVED4
[
43
];
__O
uint32_t
LAR
;
/*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I
uint32_t
LSR
;
/*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t
RESERVED5
[
6
];
uint32_t
RESERVED5
[
6
];
__I
uint32_t
PID4
;
/*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I
uint32_t
PID5
;
/*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I
uint32_t
PID6
;
/*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
...
...
@@ -1516,9 +1531,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
components/CMSIS/Include/core_cm4.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cm4.h
* @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
* @version V3.
01
* @date 2
2. March 2012
* @version V3.
20
* @date 2
5. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS CM4 definitions */
#define __CM4_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __CM4_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
__CM4_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
...
...
@@ -669,14 +684,14 @@ typedef struct
__IO
uint32_t
TPR
;
/*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t
RESERVED2
[
15
];
__IO
uint32_t
TCR
;
/*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t
RESERVED3
[
29
];
uint32_t
RESERVED3
[
29
];
__O
uint32_t
IWR
;
/*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I
uint32_t
IRR
;
/*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO
uint32_t
IMCR
;
/*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t
RESERVED4
[
43
];
uint32_t
RESERVED4
[
43
];
__O
uint32_t
LAR
;
/*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I
uint32_t
LSR
;
/*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t
RESERVED5
[
6
];
uint32_t
RESERVED5
[
6
];
__I
uint32_t
PID4
;
/*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I
uint32_t
PID5
;
/*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I
uint32_t
PID6
;
/*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
...
...
@@ -1661,9 +1676,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
components/CMSIS/Include/core_cm4_simd.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cm4_simd.h
* @brief CMSIS Cortex-M4 SIMD Header File
* @version V3.
01
* @date
06. March 2012
* @version V3.
20
* @date
25. February 2013
*
* @note
* Copyright (C) 2010-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifdef __cplusplus
extern
"C"
{
...
...
@@ -110,6 +124,8 @@
#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \
((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) )
#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \
((int64_t)(ARG3) << 32) ) >> 32))
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
...
...
@@ -624,6 +640,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __QSUB(uint32_t op1,
__RES; \
})
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint32_t
__SMMLA
(
int32_t
op1
,
int32_t
op2
,
int32_t
op3
)
{
int32_t
result
;
__ASM
volatile
(
"smmla %0, %1, %2, %3"
:
"=r"
(
result
)
:
"r"
(
op1
),
"r"
(
op2
),
"r"
(
op3
)
);
return
(
result
);
}
/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
...
...
components/CMSIS/Include/core_cmFunc.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cmFunc.h
* @brief CMSIS Cortex-M Core Function Access Header File
* @version V3.
01
* @date
06. March 2012
* @version V3.
20
* @date
25. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMFUNC_H
#define __CORE_CMFUNC_H
...
...
@@ -314,7 +328,7 @@ __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__enable_irq
(
void
)
{
__ASM
volatile
(
"cpsie i"
);
__ASM
volatile
(
"cpsie i"
:
:
:
"memory"
);
}
...
...
@@ -325,7 +339,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__disable_irq
(
void
)
{
__ASM
volatile
(
"cpsid i"
);
__ASM
volatile
(
"cpsid i"
:
:
:
"memory"
);
}
...
...
@@ -352,7 +366,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_CONTROL
(
uint32_t
control
)
{
__ASM
volatile
(
"MSR control, %0"
:
:
"r"
(
control
)
);
__ASM
volatile
(
"MSR control, %0"
:
:
"r"
(
control
)
:
"memory"
);
}
...
...
@@ -424,7 +438,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_PSP
(
uint32_t
topOfProcStack
)
{
__ASM
volatile
(
"MSR psp, %0
\n
"
:
:
"r"
(
topOfProcStack
)
);
__ASM
volatile
(
"MSR psp, %0
\n
"
:
:
"r"
(
topOfProcStack
)
:
"sp"
);
}
...
...
@@ -451,7 +465,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_MSP
(
uint32_t
topOfMainStack
)
{
__ASM
volatile
(
"MSR msp, %0
\n
"
:
:
"r"
(
topOfMainStack
)
);
__ASM
volatile
(
"MSR msp, %0
\n
"
:
:
"r"
(
topOfMainStack
)
:
"sp"
);
}
...
...
@@ -478,7 +492,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_PRIMASK
(
uint32_t
priMask
)
{
__ASM
volatile
(
"MSR primask, %0"
:
:
"r"
(
priMask
)
);
__ASM
volatile
(
"MSR primask, %0"
:
:
"r"
(
priMask
)
:
"memory"
);
}
...
...
@@ -491,7 +505,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t p
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__enable_fault_irq
(
void
)
{
__ASM
volatile
(
"cpsie f"
);
__ASM
volatile
(
"cpsie f"
:
:
:
"memory"
);
}
...
...
@@ -502,7 +516,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__disable_fault_irq
(
void
)
{
__ASM
volatile
(
"cpsid f"
);
__ASM
volatile
(
"cpsid f"
:
:
:
"memory"
);
}
...
...
@@ -529,7 +543,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_BASEPRI
(
uint32_t
value
)
{
__ASM
volatile
(
"MSR basepri, %0"
:
:
"r"
(
value
)
);
__ASM
volatile
(
"MSR basepri, %0"
:
:
"r"
(
value
)
:
"memory"
);
}
...
...
@@ -556,7 +570,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_FAULTMASK
(
uint32_t
faultMask
)
{
__ASM
volatile
(
"MSR faultmask, %0"
:
:
"r"
(
faultMask
)
);
__ASM
volatile
(
"MSR faultmask, %0"
:
:
"r"
(
faultMask
)
:
"memory"
);
}
#endif
/* (__CORTEX_M >= 0x03) */
...
...
@@ -575,7 +589,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
uint32_t
result
;
/* Empty asm statement works as a scheduling barrier */
__ASM
volatile
(
""
);
__ASM
volatile
(
"VMRS %0, fpscr"
:
"=r"
(
result
)
);
__ASM
volatile
(
""
);
return
(
result
);
#else
return
(
0
);
...
...
@@ -592,7 +609,10 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__set_FPSCR
(
uint32_t
fpscr
)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
__ASM
volatile
(
"VMSR fpscr, %0"
:
:
"r"
(
fpscr
)
);
/* Empty asm statement works as a scheduling barrier */
__ASM
volatile
(
""
);
__ASM
volatile
(
"VMSR fpscr, %0"
:
:
"r"
(
fpscr
)
:
"vfpcc"
);
__ASM
volatile
(
""
);
#endif
}
...
...
components/CMSIS/Include/core_cmInstr.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_cmInstr.h
* @brief CMSIS Cortex-M Core Instruction Access Header File
* @version V3.
01
* @date 0
6. March 2012
* @version V3.
20
* @date 0
5. March 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#ifndef __CORE_CMINSTR_H
#define __CORE_CMINSTR_H
...
...
@@ -111,12 +125,13 @@
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__
((
section
(
".rev16_text"
)))
__STATIC_INLINE
__ASM
uint32_t
__REV16
(
uint32_t
value
)
{
rev16
r0
,
r0
bx
lr
}
#endif
/** \brief Reverse byte order in signed short value
...
...
@@ -125,11 +140,13 @@ __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(u
\param [in] value Value to reverse
\return Reversed value
*/
#ifndef __NO_EMBEDDED_ASM
__attribute__
((
section
(
".revsh_text"
)))
__STATIC_INLINE
__ASM
int32_t
__REVSH
(
int32_t
value
)
{
revsh
r0
,
r0
bx
lr
}
#endif
/** \brief Rotate Right in unsigned value (32 bit)
...
...
@@ -143,6 +160,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#define __ROR __ror
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __breakpoint(value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
...
...
@@ -279,6 +307,17 @@ __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(in
#elif defined ( __GNUC__ )
/*------------------ GNU Compiler ---------------------*/
/* GNU gcc specific functions */
/* Define macros for porting to both thumb1 and thumb2.
* For thumb1, use low register (r0-r7), specified by constrant "l"
* Otherwise, use general registers, specified by constrant "r" */
#if defined (__thumb__) && !defined (__thumb2__)
#define __CMSIS_GCC_OUT_REG(r) "=l" (r)
#define __CMSIS_GCC_USE_REG(r) "l" (r)
#else
#define __CMSIS_GCC_OUT_REG(r) "=r" (r)
#define __CMSIS_GCC_USE_REG(r) "r" (r)
#endif
/** \brief No Operation
No Operation does nothing. This instruction can be used for code alignment purposes.
...
...
@@ -364,10 +403,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint32_t
__REV
(
uint32_t
value
)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
return
__builtin_bswap32
(
value
);
#else
uint32_t
result
;
__ASM
volatile
(
"rev %0, %1"
:
"=r"
(
result
)
:
"r"
(
value
)
);
__ASM
volatile
(
"rev %0, %1"
:
__CMSIS_GCC_OUT_REG
(
result
)
:
__CMSIS_GCC_USE_REG
(
value
)
);
return
(
result
);
#endif
}
...
...
@@ -382,7 +425,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
{
uint32_t
result
;
__ASM
volatile
(
"rev16 %0, %1"
:
"=r"
(
result
)
:
"r"
(
value
)
);
__ASM
volatile
(
"rev16 %0, %1"
:
__CMSIS_GCC_OUT_REG
(
result
)
:
__CMSIS_GCC_USE_REG
(
value
)
);
return
(
result
);
}
...
...
@@ -396,10 +439,14 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t val
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
int32_t
__REVSH
(
int32_t
value
)
{
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
return
(
short
)
__builtin_bswap16
(
value
);
#else
uint32_t
result
;
__ASM
volatile
(
"revsh %0, %1"
:
"=r"
(
result
)
:
"r"
(
value
)
);
__ASM
volatile
(
"revsh %0, %1"
:
__CMSIS_GCC_OUT_REG
(
result
)
:
__CMSIS_GCC_USE_REG
(
value
)
);
return
(
result
);
#endif
}
...
...
@@ -413,12 +460,21 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint32_t
__ROR
(
uint32_t
op1
,
uint32_t
op2
)
{
__ASM
volatile
(
"ror %0, %0, %1"
:
"+r"
(
op1
)
:
"r"
(
op2
)
);
return
(
op1
);
return
(
op1
>>
op2
)
|
(
op1
<<
(
32
-
op2
));
}
/** \brief Breakpoint
This function causes the processor to enter Debug state.
Debug tools can use this to investigate system state when the instruction at a particular address is reached.
\param [in] value is ignored by the processor.
If required, a debugger can use it to store additional information about the breakpoint.
*/
#define __BKPT(value) __ASM volatile ("bkpt "#value)
#if (__CORTEX_M >= 0x03)
/** \brief Reverse bit order of value
...
...
@@ -446,9 +502,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t valu
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint8_t
__LDREXB
(
volatile
uint8_t
*
addr
)
{
uint
8
_t
result
;
uint
32
_t
result
;
__ASM
volatile
(
"ldrexb %0, [%1]"
:
"=r"
(
result
)
:
"r"
(
addr
)
);
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM
volatile
(
"ldrexb %0, %1"
:
"=r"
(
result
)
:
"Q"
(
*
addr
)
);
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM
volatile
(
"ldrexb %0, [%1]"
:
"=r"
(
result
)
:
"r"
(
addr
)
:
"memory"
);
#endif
return
(
result
);
}
...
...
@@ -462,9 +525,16 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uin
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint16_t
__LDREXH
(
volatile
uint16_t
*
addr
)
{
uint
16
_t
result
;
uint
32
_t
result
;
__ASM
volatile
(
"ldrexh %0, [%1]"
:
"=r"
(
result
)
:
"r"
(
addr
)
);
#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
__ASM
volatile
(
"ldrexh %0, %1"
:
"=r"
(
result
)
:
"Q"
(
*
addr
)
);
#else
/* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
accepted by assembler. So has to use following less efficient pattern.
*/
__ASM
volatile
(
"ldrexh %0, [%1]"
:
"=r"
(
result
)
:
"r"
(
addr
)
:
"memory"
);
#endif
return
(
result
);
}
...
...
@@ -480,7 +550,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile ui
{
uint32_t
result
;
__ASM
volatile
(
"ldrex %0,
[%1]"
:
"=r"
(
result
)
:
"r"
(
addr
)
);
__ASM
volatile
(
"ldrex %0,
%1"
:
"=r"
(
result
)
:
"Q"
(
*
addr
)
);
return
(
result
);
}
...
...
@@ -498,7 +568,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t val
{
uint32_t
result
;
__ASM
volatile
(
"strexb %0, %2,
[%1]"
:
"=&r"
(
result
)
:
"r"
(
addr
),
"r"
(
value
)
);
__ASM
volatile
(
"strexb %0, %2,
%1"
:
"=&r"
(
result
),
"=Q"
(
*
addr
)
:
"r"
(
value
)
);
return
(
result
);
}
...
...
@@ -516,7 +586,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t va
{
uint32_t
result
;
__ASM
volatile
(
"strexh %0, %2,
[%1]"
:
"=&r"
(
result
)
:
"r"
(
addr
),
"r"
(
value
)
);
__ASM
volatile
(
"strexh %0, %2,
%1"
:
"=&r"
(
result
),
"=Q"
(
*
addr
)
:
"r"
(
value
)
);
return
(
result
);
}
...
...
@@ -534,7 +604,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
{
uint32_t
result
;
__ASM
volatile
(
"strex %0, %2,
[%1]"
:
"=&r"
(
result
)
:
"r"
(
addr
),
"r"
(
value
)
);
__ASM
volatile
(
"strex %0, %2,
%1"
:
"=&r"
(
result
),
"=Q"
(
*
addr
)
:
"r"
(
value
)
);
return
(
result
);
}
...
...
@@ -546,7 +616,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t va
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
void
__CLREX
(
void
)
{
__ASM
volatile
(
"clrex"
);
__ASM
volatile
(
"clrex"
:::
"memory"
);
}
...
...
@@ -591,7 +661,7 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
*/
__attribute__
(
(
always_inline
)
)
__STATIC_INLINE
uint8_t
__CLZ
(
uint32_t
value
)
{
uint8
_t
result
;
uint32
_t
result
;
__ASM
volatile
(
"clz %0, %1"
:
"=r"
(
result
)
:
"r"
(
value
)
);
return
(
result
);
...
...
components/CMSIS/Include/core_sc000.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_sc000.h
* @brief CMSIS SC000 Core Peripheral Access Layer Header File
* @version V3.
01
* @date 2
2. March 2012
* @version V3.
20
* @date 2
5. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS SC000 definitions */
#define __SC000_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __SC000_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16) | \
__SC000_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
...
...
@@ -721,9 +736,9 @@ __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
{
if
(
IRQn
<
0
)
{
return
((
uint32_t
)((
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for SC00
0 system interrupts */
return
((
uint32_t
)((
(
SCB
->
SHP
[
_SHP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for Cortex-M
0 system interrupts */
else
{
return
((
uint32_t
)((
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts */
return
((
uint32_t
)((
(
NVIC
->
IP
[
_IP_IDX
(
IRQn
)]
>>
_BIT_SHIFT
(
IRQn
)
)
&
0xFF
)
>>
(
8
-
__NVIC_PRIO_BITS
)));
}
/* get priority for device specific interrupts */
}
...
...
@@ -771,9 +786,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
components/CMSIS/Include/core_sc300.h
浏览文件 @
9367bba6
/**************************************************************************//**
* @file core_sc300.h
* @brief CMSIS SC300 Core Peripheral Access Layer Header File
* @version V3.
01
* @date 2
2. March 2012
* @version V3.
20
* @date 2
5. February 2013
*
* @note
* Copyright (C) 2009-2012 ARM Limited. All rights reserved.
*
* @par
* ARM Limited (ARM) is supplying this software for use with Cortex-M
* processor based microcontrollers. This file can be freely distributed
* within development tools that are supporting such ARM based processors.
*
* @par
* THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
* OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
* ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
* CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
*
******************************************************************************/
/* Copyright (c) 2009 - 2013 ARM LIMITED
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are met:
- Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
- Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in the
documentation and/or other materials provided with the distribution.
- Neither the name of ARM nor the names of its contributors may be used
to endorse or promote products derived from this software without
specific prior written permission.
*
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
POSSIBILITY OF SUCH DAMAGE.
---------------------------------------------------------------------------*/
#if defined ( __ICCARM__ )
#pragma system_include
/* treat file as system include file for MISRA check */
#endif
...
...
@@ -54,7 +69,7 @@
/* CMSIS SC300 definitions */
#define __SC300_CMSIS_VERSION_MAIN (0x03)
/*!< [31:16] CMSIS HAL main version */
#define __SC300_CMSIS_VERSION_SUB (0x
01
)
/*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION_SUB (0x
20
)
/*!< [15:0] CMSIS HAL sub version */
#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16) | \
__SC300_CMSIS_VERSION_SUB )
/*!< CMSIS HAL version number */
...
...
@@ -607,14 +622,14 @@ typedef struct
__IO
uint32_t
TPR
;
/*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
uint32_t
RESERVED2
[
15
];
__IO
uint32_t
TCR
;
/*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
uint32_t
RESERVED3
[
29
];
uint32_t
RESERVED3
[
29
];
__O
uint32_t
IWR
;
/*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
__I
uint32_t
IRR
;
/*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
__IO
uint32_t
IMCR
;
/*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
uint32_t
RESERVED4
[
43
];
uint32_t
RESERVED4
[
43
];
__O
uint32_t
LAR
;
/*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
__I
uint32_t
LSR
;
/*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
uint32_t
RESERVED5
[
6
];
uint32_t
RESERVED5
[
6
];
__I
uint32_t
PID4
;
/*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
__I
uint32_t
PID5
;
/*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
__I
uint32_t
PID6
;
/*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
...
...
@@ -1487,9 +1502,9 @@ __STATIC_INLINE void NVIC_SystemReset(void)
*/
__STATIC_INLINE
uint32_t
SysTick_Config
(
uint32_t
ticks
)
{
if
(
ticks
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
if
(
(
ticks
-
1
)
>
SysTick_LOAD_RELOAD_Msk
)
return
(
1
);
/* Reload value impossible */
SysTick
->
LOAD
=
(
ticks
&
SysTick_LOAD_RELOAD_Msk
)
-
1
;
/* set reload register */
SysTick
->
LOAD
=
ticks
-
1
;
/* set reload register */
NVIC_SetPriority
(
SysTick_IRQn
,
(
1
<<
__NVIC_PRIO_BITS
)
-
1
);
/* set Priority for Systick Interrupt */
SysTick
->
VAL
=
0
;
/* Load the SysTick Counter Value */
SysTick
->
CTRL
=
SysTick_CTRL_CLKSOURCE_Msk
|
...
...
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