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提交 1612d890 编写于 作者: F FuChao
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补充KEIL5编译支持文件，解决KEIL5编译问题

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bsp/Vango_V85xx/Libraries/CMSIS/Vango/V85xx/Source/keil5/startup_target.S 0 → 100644
浏览文件 @ 1612d890
;/**
;* @file startup_target.s
;* @author Application Team
;* @version V1.1.0
;* @date 2019-10-28
;* @brief Target Devices vector table.
;******************************************************************************/
; <h> Stack Configuration
; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
__CHIPINITIAL EQU 1
Stack_Size EQU 0x000001000
AREA STACK, NOINIT, READWRITE, ALIGN=3
Stack_Mem SPACE Stack_Size
__initial_sp
; <h> Heap Configuration
; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
; </h>
Heap_Size EQU 0x00000400
AREA HEAP, NOINIT, READWRITE, ALIGN=3
__heap_base
Heap_Mem SPACE Heap_Size
__heap_limit
PRESERVE8
THUMB
; Vector Table Mapped to Address 0 at Reset
AREA RESET, DATA, READONLY
EXPORT __Vectors
EXPORT __Vectors_End
EXPORT __Vectors_Size
__Vectors DCD __initial_sp ; Top of Stack
DCD Reset_Handler ; Reset Handler
DCD NMI_Handler ; NMI Handler
DCD HardFault_Handler ; Hard Fault Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD SVC_Handler ; SVCall Handler
DCD 0 ; Reserved
DCD 0 ; Reserved
DCD PendSV_Handler ; PendSV Handler
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
DCD PMU_IRQHandler ; 0: PMU
DCD RTC_IRQHandler ; 1: RTC
DCD U32K0_IRQHandler ; 2: U32K0
DCD U32K1_IRQHandler ; 3: U32K1
DCD I2C_IRQHandler ; 4: I2C
DCD SPI1_IRQHandler ; 5: SPI1
DCD UART0_IRQHandler ; 6: UART0
DCD UART1_IRQHandler ; 7: UART1
DCD UART2_IRQHandler ; 8: UART2
DCD UART3_IRQHandler ; 9: UART3
DCD UART4_IRQHandler ; 10: UART4
DCD UART5_IRQHandler ; 11: UART5
DCD ISO78160_IRQHandler ; 12: ISO78160
DCD ISO78161_IRQHandler ; 13: ISO78161
DCD TMR0_IRQHandler ; 14: TMR0
DCD TMR1_IRQHandler ; 15: TMR1
DCD TMR2_IRQHandler ; 16: TMR2
DCD TMR3_IRQHandler ; 17: TMR3
DCD PWM0_IRQHandler ; 18: PWM0
DCD PWM1_IRQHandler ; 19: PWM1
DCD PWM2_IRQHandler ; 20: PWM2
DCD PWM3_IRQHandler ; 21: PWM3
DCD DMA_IRQHandler ; 22: DMA
DCD FLASH_IRQHandler ; 23: FLASH
DCD ANA_IRQHandler ; 24: ANA
DCD 0 ; 25: Reserved
DCD 0 ; 26: Reserved
DCD SPI2_IRQHandler ; 27: SPI2
DCD SPI3_IRQHandler ; 28: SPI3
DCD 0 ; 29: Reserved
DCD 0 ; 30: Reserved
DCD 0 ; 31: Reserved
__Vectors_End
__Vectors_Size EQU __Vectors_End - __Vectors
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
ELSE
AREA |.text|, CODE, READONLY
ENDIF
; Reset Handler
Reset_Handler PROC
EXPORT Reset_Handler [WEAK]
IMPORT __main
IMPORT SystemInit
IF (__CHIPINITIAL != 0)
LDR R0, =__CHIP_INIT
BLX R0
ENDIF
LDR R0, =SystemInit
BLX R0
LDR R0, =__main
BX R0
ENDP
AREA |.text|, CODE, READONLY
; Dummy Exception Handlers (infinite loops which can be modified)
NMI_Handler PROC
EXPORT NMI_Handler [WEAK]
B .
ENDP
HardFault_Handler\
PROC
EXPORT HardFault_Handler [WEAK]
B .
ENDP
SVC_Handler PROC
EXPORT SVC_Handler [WEAK]
B .
ENDP
PendSV_Handler PROC
EXPORT PendSV_Handler [WEAK]
B .
ENDP
SysTick_Handler PROC
EXPORT SysTick_Handler [WEAK]
B .
ENDP
Default_Handler PROC
EXPORT PMU_IRQHandler [WEAK]
EXPORT RTC_IRQHandler [WEAK]
EXPORT U32K0_IRQHandler [WEAK]
EXPORT U32K1_IRQHandler [WEAK]
EXPORT I2C_IRQHandler [WEAK]
EXPORT SPI1_IRQHandler [WEAK]
EXPORT UART0_IRQHandler [WEAK]
EXPORT UART1_IRQHandler [WEAK]
EXPORT UART2_IRQHandler [WEAK]
EXPORT UART3_IRQHandler [WEAK]
EXPORT UART4_IRQHandler [WEAK]
EXPORT UART5_IRQHandler [WEAK]
EXPORT ISO78160_IRQHandler [WEAK]
EXPORT ISO78161_IRQHandler [WEAK]
EXPORT TMR0_IRQHandler [WEAK]
EXPORT TMR1_IRQHandler [WEAK]
EXPORT TMR2_IRQHandler [WEAK]
EXPORT TMR3_IRQHandler [WEAK]
EXPORT PWM0_IRQHandler [WEAK]
EXPORT PWM1_IRQHandler [WEAK]
EXPORT PWM2_IRQHandler [WEAK]
EXPORT PWM3_IRQHandler [WEAK]
EXPORT DMA_IRQHandler [WEAK]
EXPORT FLASH_IRQHandler [WEAK]
EXPORT ANA_IRQHandler [WEAK]
EXPORT SPI2_IRQHandler [WEAK]
EXPORT SPI3_IRQHandler [WEAK]
PMU_IRQHandler
RTC_IRQHandler
U32K0_IRQHandler
U32K1_IRQHandler
I2C_IRQHandler
SPI1_IRQHandler
UART0_IRQHandler
UART1_IRQHandler
UART2_IRQHandler
UART3_IRQHandler
UART4_IRQHandler
UART5_IRQHandler
ISO78160_IRQHandler
ISO78161_IRQHandler
TMR0_IRQHandler
TMR1_IRQHandler
TMR2_IRQHandler
TMR3_IRQHandler
PWM0_IRQHandler
PWM1_IRQHandler
PWM2_IRQHandler
PWM3_IRQHandler
DMA_IRQHandler
FLASH_IRQHandler
ANA_IRQHandler
SPI2_IRQHandler
SPI3_IRQHandler
B .
ENDP
ALIGN
; User Initial Stack & Heap
IF :DEF:__MICROLIB
EXPORT __initial_sp
EXPORT __heap_base
EXPORT __heap_limit
ELSE
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap PROC
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDP
ALIGN
ENDIF
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
;; Chip init.
;; 1. Load flash configuration
;; 2. Load ANA_REG(B/C/D/E) information
;; 3. Load ANA_REG10 information
IF (__CHIPINITIAL != 0)
AREA |.ARM.__AT_0xC0|, CODE, READONLY
__CHIP_INIT PROC
CONFIG1_START
;-------------------------------;
;; 1. Load flash configuration
; Unlock flash
LDR R0, =0x000FFFE0
LDR R1, =0x55AAAA55
STR R1, [R0]
; Load configure word 0 to 7
; Compare bit[7:0]
LDR R0, =0x00080E00
LDR R1, =0x20
LDR R2, =0x000FFFE8
LDR R3, =0x000FFFF0
LDR R4, =0x0
LDR R7, =0x0FF
FLASH_CONF_START_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_AGAIN_1
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_1
BNE FLASH_CONF_WHILELOOP_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_1
B FLASH_CONF_START_1
FLASH_CONF_END_1
; Load configure word 8 to 11
; Compare bit 31,24,23:16,8,7:0
LDR R1, =0x30
LDR R7, =0x81FF81FF
FLASH_CONF_START_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
BNE FLASH_CONF_AGAIN_1
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_AGAIN_2
LDR R5, [R0]
STR R4, [R2]
STR R5, [R3]
LDR R6, [R3]
ANDS R5, R7
ANDS R6, R7
CMP R5, R6
FLASH_CONF_WHILELOOP_2
BNE FLASH_CONF_WHILELOOP_2
ADDS R4, #4
ADDS R0, #4
CMP R1, R4
BEQ FLASH_CONF_END_2
B FLASH_CONF_START_2
FLASH_CONF_END_2
; Lock flash
LDR R0, =0x000FFFE0
LDR R1, =0x0
STR R1, [R0]
;-------------------------------;
;; 2. Load ANA_REG(B/C/D/E) information
CONFIG2_START
LDR R4, =0x4001422C
LDR R5, =0x40014230
LDR R6, =0x40014234
LDR R7, =0x40014238
LDR R0, =0x80DC0
LDR R0, [R0]
LDR R1, =0x80DC4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DCC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM1_OK
B ANADAT_CHECKSUM1_ERR
ANADAT_CHECKSUM1_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM1_ERR
LDR R0, =0x80DD0
LDR R0, [R0]
LDR R1, =0x80DD4
LDR R1, [R1]
ADDS R2, R0, R1
ADDS R2, #0x0FFFFFFFF
MVNS R2, R2
LDR R3, =0x80DDC
LDR R3, [R3]
CMP R3, R2
BEQ ANADAT_CHECKSUM2_OK
B ANADAT_CHECKSUM2_ERR
ANADAT_CHECKSUM2_OK
; ANA_REGB
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R4]
; ANA_REGC
LDR R1, =0x0FF00
ANDS R1, R0
LSRS R1, R1, #8
STR R1, [R5]
; ANA_REGD
LDR R1, =0x0FF0000
ANDS R1, R0
LSRS R1, R1, #16
STR R1, [R6]
; ANA_REGE
LDR R1, =0x0FF000000
ANDS R1, R0
LSRS R1, R1, #24
STR R1, [R7]
B CONFIG3_START
ANADAT_CHECKSUM2_ERR
B ANADAT_CHECKSUM2_ERR
;-------------------------------;
;; 2. Load ANA_REG10 information
CONFIG3_START
LDR R7, =0x40014240
LDR R0, =0x80DE0
LDR R0, [R0]
LDR R1, =0x80DE4
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM1_OK
B ANADAT10_CHECKSUM1_ERR
ANADAT10_CHECKSUM1_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM1_ERR
LDR R0, =0x80DE8
LDR R0, [R0]
LDR R1, =0x80DEC
LDR R1, [R1]
MVNS R1, R1
CMP R1, R0
BEQ ANADAT10_CHECKSUM2_OK
B ANADAT10_CHECKSUM2_ERR
ANADAT10_CHECKSUM2_OK
; ANA_REG10
LDR R1, =0x0FF
ANDS R1, R0
STR R1, [R7]
BX LR
ANADAT10_CHECKSUM2_ERR
B ANADAT10_CHECKSUM2_ERR
NOP
ENDP
ENDIF
END
/*********************************** END OF FILE ******************************/
bsp/Vango_V85xx/Libraries/SConscript
浏览文件 @ 1612d890
......@@ -8,10 +8,15 @@ cwd = GetCurrentDir()
src = Glob('VangoV85xx_standard_peripheral/Source/*.c')
src += [cwd + '/CMSIS/Vango/V85xx/Source/system_target.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_CodeRAM.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_cortex.c']
src += [cwd + '/CMSIS/Vango/V85xx/Source/lib_LoadNVR.c']
#add for startup script
if rtconfig.CROSS_TOOL == 'gcc':
src += [cwd + '/CMSIS/Vango/V85xx/Source/GCC/startup_target.S']
if rtconfig.CROSS_TOOL == 'mdk5':
src += [cwd + '/CMSIS/Vango/V85xx/Source/Keil5/startup_target.S']
path = [
cwd + '/CMSIS/Vango/V85xx/Include',
......
bsp/Vango_V85xx/template.uvprojx 0 → 100644
浏览文件 @ 1612d890
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<Project xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="project_projx.xsd">
<SchemaVersion>2.1</SchemaVersion>
<Header>### uVision Project, (C) Keil Software</Header>
<Targets>
<Target>
<TargetName>Target 1</TargetName>
<ToolsetNumber>0x4</ToolsetNumber>
<ToolsetName>ARM-ADS</ToolsetName>
<uAC6>0</uAC6>
<TargetOption>
<TargetCommonOption>
<Device>V85XX</Device>
<Vendor>Generic</Vendor>
<PackID>Vango.V85XX.4.0.2</PackID>
<Cpu>IRAM(0x20000000,0x8000) IROM(0x00000000,0x40000) CPUTYPE("Cortex-M0") CLOCK(12000000) ELITTLE</Cpu>
<FlashUtilSpec></FlashUtilSpec>
<StartupFile></StartupFile>
<FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0Vango_V85XX -FS00 -FL040000 -FP0($$Device:V85XX$FLASH\Vango_V85XX.FLM))</FlashDriverDll>
<DeviceId>0</DeviceId>
<RegisterFile>$$Device:V85XX$Device\Include\V85XX.h</RegisterFile>
<MemoryEnv></MemoryEnv>
<Cmp></Cmp>
<Asm></Asm>
<Linker></Linker>
<OHString></OHString>
<InfinionOptionDll></InfinionOptionDll>
<SLE66CMisc></SLE66CMisc>
<SLE66AMisc></SLE66AMisc>
<SLE66LinkerMisc></SLE66LinkerMisc>
<SFDFile>$$Device:V85XX$SVD\V85XX.svd</SFDFile>
<bCustSvd>0</bCustSvd>
<UseEnv>0</UseEnv>
<BinPath></BinPath>
<IncludePath></IncludePath>
<LibPath></LibPath>
<RegisterFilePath></RegisterFilePath>
<DBRegisterFilePath></DBRegisterFilePath>
<TargetStatus>
<Error>0</Error>
<ExitCodeStop>0</ExitCodeStop>
<ButtonStop>0</ButtonStop>
<NotGenerated>0</NotGenerated>
<InvalidFlash>1</InvalidFlash>
</TargetStatus>
<OutputDirectory>.\Objects\</OutputDirectory>
<OutputName>template</OutputName>
<CreateExecutable>1</CreateExecutable>
<CreateLib>0</CreateLib>
<CreateHexFile>0</CreateHexFile>
<DebugInformation>1</DebugInformation>
<BrowseInformation>1</BrowseInformation>
<ListingPath>.\Listings\</ListingPath>
<HexFormatSelection>1</HexFormatSelection>
<Merge32K>0</Merge32K>
<CreateBatchFile>0</CreateBatchFile>
<BeforeCompile>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopU1X>0</nStopU1X>
<nStopU2X>0</nStopU2X>
</BeforeCompile>
<BeforeMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopB1X>0</nStopB1X>
<nStopB2X>0</nStopB2X>
</BeforeMake>
<AfterMake>
<RunUserProg1>0</RunUserProg1>
<RunUserProg2>0</RunUserProg2>
<UserProg1Name></UserProg1Name>
<UserProg2Name></UserProg2Name>
<UserProg1Dos16Mode>0</UserProg1Dos16Mode>
<UserProg2Dos16Mode>0</UserProg2Dos16Mode>
<nStopA1X>0</nStopA1X>
<nStopA2X>0</nStopA2X>
</AfterMake>
<SelectedForBatchBuild>0</SelectedForBatchBuild>
<SVCSIdString></SVCSIdString>
</TargetCommonOption>
<CommonProperty>
<UseCPPCompiler>0</UseCPPCompiler>
<RVCTCodeConst>0</RVCTCodeConst>
<RVCTZI>0</RVCTZI>
<RVCTOtherData>0</RVCTOtherData>
<ModuleSelection>0</ModuleSelection>
<IncludeInBuild>1</IncludeInBuild>
<AlwaysBuild>0</AlwaysBuild>
<GenerateAssemblyFile>0</GenerateAssemblyFile>
<AssembleAssemblyFile>0</AssembleAssemblyFile>
<PublicsOnly>0</PublicsOnly>
<StopOnExitCode>3</StopOnExitCode>
<CustomArgument></CustomArgument>
<IncludeLibraryModules></IncludeLibraryModules>
<ComprImg>1</ComprImg>
</CommonProperty>
<DllOption>
<SimDllName>SARMCM3.DLL</SimDllName>
<SimDllArguments> </SimDllArguments>
<SimDlgDll>DARMCM1.DLL</SimDlgDll>
<SimDlgDllArguments>-pCM0</SimDlgDllArguments>
<TargetDllName>SARMCM3.DLL</TargetDllName>
<TargetDllArguments> </TargetDllArguments>
<TargetDlgDll>TARMCM1.DLL</TargetDlgDll>
<TargetDlgDllArguments>-pCM0</TargetDlgDllArguments>
</DllOption>
<DebugOption>
<OPTHX>
<HexSelection>1</HexSelection>
<HexRangeLowAddress>0</HexRangeLowAddress>
<HexRangeHighAddress>0</HexRangeHighAddress>
<HexOffset>0</HexOffset>
<Oh166RecLen>16</Oh166RecLen>
</OPTHX>
</DebugOption>
<Utilities>
<Flash1>
<UseTargetDll>1</UseTargetDll>
<UseExternalTool>0</UseExternalTool>
<RunIndependent>0</RunIndependent>
<UpdateFlashBeforeDebugging>1</UpdateFlashBeforeDebugging>
<Capability>1</Capability>
<DriverSelection>-1</DriverSelection>
</Flash1>
<bUseTDR>1</bUseTDR>
<Flash2>BIN\UL2CM3.DLL</Flash2>
<Flash3></Flash3>
<Flash4></Flash4>
<pFcarmOut></pFcarmOut>
<pFcarmGrp></pFcarmGrp>
<pFcArmRoot></pFcArmRoot>
<FcArmLst>0</FcArmLst>
</Utilities>
<TargetArmAds>
<ArmAdsMisc>
<GenerateListings>0</GenerateListings>
<asHll>1</asHll>
<asAsm>1</asAsm>
<asMacX>1</asMacX>
<asSyms>1</asSyms>
<asFals>1</asFals>
<asDbgD>1</asDbgD>
<asForm>1</asForm>
<ldLst>0</ldLst>
<ldmm>1</ldmm>
<ldXref>1</ldXref>
<BigEnd>0</BigEnd>
<AdsALst>1</AdsALst>
<AdsACrf>1</AdsACrf>
<AdsANop>0</AdsANop>
<AdsANot>0</AdsANot>
<AdsLLst>1</AdsLLst>
<AdsLmap>1</AdsLmap>
<AdsLcgr>1</AdsLcgr>
<AdsLsym>1</AdsLsym>
<AdsLszi>1</AdsLszi>
<AdsLtoi>1</AdsLtoi>
<AdsLsun>1</AdsLsun>
<AdsLven>1</AdsLven>
<AdsLsxf>1</AdsLsxf>
<RvctClst>0</RvctClst>
<GenPPlst>0</GenPPlst>
<AdsCpuType>"Cortex-M0"</AdsCpuType>
<RvctDeviceName></RvctDeviceName>
<mOS>0</mOS>
<uocRom>0</uocRom>
<uocRam>0</uocRam>
<hadIROM>1</hadIROM>
<hadIRAM>1</hadIRAM>
<hadXRAM>0</hadXRAM>
<uocXRam>0</uocXRam>
<RvdsVP>0</RvdsVP>
<RvdsMve>0</RvdsMve>
<hadIRAM2>0</hadIRAM2>
<hadIROM2>0</hadIROM2>
<StupSel>8</StupSel>
<useUlib>0</useUlib>
<EndSel>0</EndSel>
<uLtcg>0</uLtcg>
<nSecure>0</nSecure>
<RoSelD>3</RoSelD>
<RwSelD>3</RwSelD>
<CodeSel>0</CodeSel>
<OptFeed>0</OptFeed>
<NoZi1>0</NoZi1>
<NoZi2>0</NoZi2>
<NoZi3>0</NoZi3>
<NoZi4>0</NoZi4>
<NoZi5>0</NoZi5>
<Ro1Chk>0</Ro1Chk>
<Ro2Chk>0</Ro2Chk>
<Ro3Chk>0</Ro3Chk>
<Ir1Chk>1</Ir1Chk>
<Ir2Chk>0</Ir2Chk>
<Ra1Chk>0</Ra1Chk>
<Ra2Chk>0</Ra2Chk>
<Ra3Chk>0</Ra3Chk>
<Im1Chk>1</Im1Chk>
<Im2Chk>0</Im2Chk>
<OnChipMemories>
<Ocm1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm1>
<Ocm2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm2>
<Ocm3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm3>
<Ocm4>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm4>
<Ocm5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm5>
<Ocm6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</Ocm6>
<IRAM>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</IRAM>
<IROM>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</IROM>
<XRAM>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</XRAM>
<OCR_RVCT1>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT1>
<OCR_RVCT2>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT2>
<OCR_RVCT3>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT3>
<OCR_RVCT4>
<Type>1</Type>
<StartAddress>0x0</StartAddress>
<Size>0x40000</Size>
</OCR_RVCT4>
<OCR_RVCT5>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT5>
<OCR_RVCT6>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT6>
<OCR_RVCT7>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT7>
<OCR_RVCT8>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT8>
<OCR_RVCT9>
<Type>0</Type>
<StartAddress>0x20000000</StartAddress>
<Size>0x8000</Size>
</OCR_RVCT9>
<OCR_RVCT10>
<Type>0</Type>
<StartAddress>0x0</StartAddress>
<Size>0x0</Size>
</OCR_RVCT10>
</OnChipMemories>
<RvctStartVector></RvctStartVector>
</ArmAdsMisc>
<Cads>
<interw>1</interw>
<Optim>1</Optim>
<oTime>0</oTime>
<SplitLS>0</SplitLS>
<OneElfS>1</OneElfS>
<Strict>0</Strict>
<EnumInt>0</EnumInt>
<PlainCh>0</PlainCh>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<wLevel>2</wLevel>
<uThumb>0</uThumb>
<uSurpInc>0</uSurpInc>
<uC99>1</uC99>
<uGnu>1</uGnu>
<useXO>0</useXO>
<v6Lang>1</v6Lang>
<v6LangP>1</v6LangP>
<vShortEn>1</vShortEn>
<vShortWch>1</vShortWch>
<v6Lto>0</v6Lto>
<v6WtE>0</v6WtE>
<v6Rtti>0</v6Rtti>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Cads>
<Aads>
<interw>1</interw>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<thumb>0</thumb>
<SplitLS>0</SplitLS>
<SwStkChk>0</SwStkChk>
<NoWarn>0</NoWarn>
<uSurpInc>0</uSurpInc>
<useXO>0</useXO>
<uClangAs>0</uClangAs>
<VariousControls>
<MiscControls></MiscControls>
<Define></Define>
<Undefine></Undefine>
<IncludePath></IncludePath>
</VariousControls>
</Aads>
<LDads>
<umfTarg>1</umfTarg>
<Ropi>0</Ropi>
<Rwpi>0</Rwpi>
<noStLib>0</noStLib>
<RepFail>1</RepFail>
<useFile>0</useFile>
<TextAddressRange>0x00000000</TextAddressRange>
<DataAddressRange>0x20000000</DataAddressRange>
<pXoBase></pXoBase>
<ScatterFile></ScatterFile>
<IncludeLibs></IncludeLibs>
<IncludeLibsPath></IncludeLibsPath>
<Misc></Misc>
<LinkerInputFile></LinkerInputFile>
<DisabledWarnings></DisabledWarnings>
</LDads>
</TargetArmAds>
</TargetOption>
<Groups>
<Group>
<GroupName>Source Group 1</GroupName>
</Group>
</Groups>
</Target>
</Targets>
<RTE>
<apis/>
<components/>
<files/>
</RTE>
</Project>
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