- 07 11月, 2019 1 次提交
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由 Evan Quan 提交于
Otherwise, the feature enablement will be skipped due to wrong count. Fixes: beff74bc ("drm/amdgpu: fix a race in GPU reset with IB test (v2)") Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 8月, 2019 1 次提交
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由 Andrey Grodzovsky 提交于
This should be checked at all places job is accessed. Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: NChristian König <christian.koenig@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 30 8月, 2019 2 次提交
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由 Roman Li 提交于
Enable DC support for renoir. Acked-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NRoman Li <Roman.Li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Monk Liu 提交于
for SOC15/vega10 the BACO reset & mode1 would introduce vram lost in high end address range, current kmd's vram lost checking cannot catch it since it only check very ahead visible frame buffer v2: cover NV as well Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 16 8月, 2019 1 次提交
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由 Andrey Grodzovsky 提交于
Integrate the mode2 reset into rest sequence. v2: Check ppfuncs pointer for NULL Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 13 8月, 2019 2 次提交
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由 Huang Rui 提交于
This patch adds renoir support for gpu_info firmware and ip block setting. Acked-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
This patch adds renoir to amd_asic_type enum and amdgpu_asic_name[]. Acked-by: NHuang Rui <ray.huang@amd.com> Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 8月, 2019 2 次提交
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由 Tao Zhou 提交于
atomic 64 bits REG operations are useless currently Reviewed-by: NChristian König <christian.koenig@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Tao Zhou 提交于
what we really want is a read or write that is guaranteed to be 64 bits at a time, atomic64 operations are supported on all architectures Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 07 8月, 2019 2 次提交
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由 Andrey Grodzovsky 提交于
amdgpu_ip_block.status.hw for GMC wasn't set to false on suspend during GPU reset and so on resume gmc_v9_0_resume wasn't called. Caused by 'drm/amdgpu: fix double ucode load by PSP(v3)' Signed-off-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 xinhui pan 提交于
Clear the flag after hw suspend, otherwise it skips the corresponding hw resume. Signed-off-by: Nxinhui pan <xinhui.pan@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 8月, 2019 6 次提交
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由 Leo Li 提交于
Load DC and amdgpu display manager Signed-off-by: NLeo Li <sunpeng.li@amd.com> Reviewed-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
same with navi10 Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
gpu_info firmare store asic configuration details. Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
Add asic type. Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Monk Liu 提交于
previously the ucode loading of PSP was repreated, one executed in phase_1 init/re-init/resume and the other in fw_loading routine Avoid this double loading by clearing ip_blocks.status.hw in suspend or reset prior to the FW loading and any block's hw_init/resume v2: still do the smu fw loading since it is needed by bare-metal v3: drop the change in reinit_early_sriov, just clear all block's status.hw in the head place and set the status.hw after hw_init done is enough Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NEmily Deng <Emily.Deng@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Monk Liu 提交于
we can simplify all those unnecessary function under SRIOV for vega10 since: 1) PSP L1 policy is by force enabled in SRIOV 2) original logic always set all flags which make itself a dummy step besides, 1) the ih_doorbell_range set should also be skipped for VEGA10 SRIOV. 2) the gfx_common registers should also be skipped for VEGA10 SRIOV. Signed-off-by: NMonk Liu <Monk.Liu@amd.com> Reviewed-by: NEmily Deng <Emily.Deng@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 01 8月, 2019 1 次提交
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由 Tao Zhou 提交于
add 64 bits register access functions v2: implement 64 bit functions in low level Signed-off-by: NTao Zhou <tao.zhou1@amd.com> Reviewed-by: NDennis Li <dennis.li@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 31 7月, 2019 1 次提交
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由 Alex Deucher 提交于
When doing a GPU reset or unloading the driver, we need to put the SMU into the apprpriate state for the re-init after the reset or unload to reliably work. I don't think this is necessary for BACO because the SMU actually controls the BACO state to it needs to be active. For suspend (S3), the asic is put into D3 so the SMU would be powered down so I don't think we need to put the SMU into any special state. Reviewed-by: NEvan Quan <evan.quan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 19 7月, 2019 7 次提交
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由 Le Ma 提交于
Add GPU info firmware for Arcturus. Signed-off-by: NLe Ma <le.ma@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Le Ma 提交于
Add IP blocks for Arcturus. Signed-off-by: NLe Ma <le.ma@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Le Ma 提交于
Add asic type for Arcturus. Signed-off-by: NLe Ma <le.ma@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Bhawanpreet Lakha 提交于
enable DC for navi14. Signed-off-by: NBhawanpreet Lakha <Bhawanpreet.Lakha@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
same with navi10 Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
Add navi14 to case statement to load the GPU info firmware. Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
Add CHIP_NAVI14 to the list of asic types. Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 10 7月, 2019 2 次提交
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由 Alex Deucher 提交于
We need to serialize access to the psp ring if there are multiple callers at runtime. Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Alex Deucher 提交于
It's only available on navi and newer. Reviewed-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 09 7月, 2019 1 次提交
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由 Arnd Bergmann 提交于
When CONFIG_PERF_EVENTS is disabled, we cannot compile the pmu portion of the amdgpu driver: drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:48:38: error: no member named 'hw' in 'struct perf_event' struct hw_perf_event *hwc = &event->hw; ~~~~~ ^ drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:51:13: error: no member named 'attr' in 'struct perf_event' if (event->attr.type != event->pmu->type) ~~~~~ ^ ... Use conditional compilation for this file. Fixes: 9c7c85f7 ("drm/amdgpu: add pmu counters") Signed-off-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 06 7月, 2019 1 次提交
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由 xinhui pan 提交于
Perform a ras_suspend to disable ras on all IPs to workaround some ROCm stability issue. Signed-off-by: Nxinhui pan <xinhui.pan@amd.com> Acked-by: NAndrey Grodzovsky <andrey.grodzovsky@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 02 7月, 2019 2 次提交
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由 Jack Xiao 提交于
GPU atomics operation depends on PCIE atomics support. Always enable PCIE atomics ops support in case that it hasn't been enabled. Signed-off-by: NJack Xiao <Jack.Xiao@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Evan Quan 提交于
MGPU fan boost feature should not be enabled until all the devices from the same hive are all back from reset. Signed-off-by: NEvan Quan <evan.quan@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 22 6月, 2019 7 次提交
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由 Harry Wentland 提交于
Enable the IP for navi10. Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Harry Wentland 提交于
[WHY] We don't want to expose sensitive ASIC information before ASIC release. [HOW] Encode the soc_bounding_box in the gpu_info FW (for Linux) and read it at driver load. v2: fix warning when CONFIG_DRM_AMD_DC_DCN2_0 is not set (Alex) Signed-off-by: NHarry Wentland <harry.wentland@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Huang Rui 提交于
Set the IPs for navi10 in early_init like other asics. Signed-off-by: NHuang Rui <ray.huang@amd.com> Reviewed-by: NAlex Deucher <alexander.deucher@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Hawking Zhang 提交于
Since from soc15, make sure only AndMasked bit get changed when applied or_mask Signed-off-by: NHawking Zhang <Hawking.Zhang@amd.com> Reviewed-by: NLe Ma <Le.Ma@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jack Xiao 提交于
When amdgpu_mes is enabled and asic family is navi10 and later asic, enable mes per device. Acked-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Xiaojie Yuan 提交于
to control enablement. Signed-off-by: NXiaojie Yuan <xiaojie.yuan@amd.com> Reviewed-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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由 Jack Xiao 提交于
The MCBP unit test is used to test the functionality of MCBP. It emualtes to send preemption request and resubmit the unfinished jobs. v2: squash in fixes (Alex) v3: squash in memory leak fix (Jack) Acked-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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- 21 6月, 2019 1 次提交
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由 Jack Xiao 提交于
CSA is the Context Save Area for preemption. Acked-by: NHawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: NJack Xiao <Jack.Xiao@amd.com> Signed-off-by: NAlex Deucher <alexander.deucher@amd.com>
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