The idle-states binding documentation[1] mentions that the
'entry-method' property is required on 64-bit platforms and must be
set to "psci".

commit a13f18f5 ("Documentation: arm: Fix typo in the idle-states
bindings examples") attempted to fix this earlier but clearly more is
needed.

Fix the cpu-capacity.txt documentation that uses the incorrect value so
we don't get copy-paste errors like these. Clarify the language in
idle-states.txt by removing the reference to the psci bindings that
might be causing this confusion.

Finally, fix devicetrees of various boards to reflect current
documentation.

[1] Documentation/devicetree/bindings/arm/idle-states.txt (see
idle-states node)
Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org>
Acked-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLi Yang <leoyang.li@nxp.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The latest DTC throws warnings for character '_' in the node names.

Warning (node_name_chars_strict): /thermal-zones/big_cluster: Character '_' not recommended in node name
Warning (node_name_chars_strict): /thermal-zones/little_cluster: Character '_' not recommended in node name
Warning (node_name_chars_strict): /smb@8000000/motherboard/gpio_keys: Character '_' not recommended in node name
Warning (node_name_chars_strict): /pmu_a57: Character '_' not recommended in node name
Warning (node_name_chars_strict): /pmu_a53: Character '_' not recommended in node name

The general recommendation is to use character '-' for all the node names.
This patch fixes the warnings following the recommendation.
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.

Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Commit a8d4636f ("arm64: cacheinfo: Remove CCSIDR-based cache
information probing") removed mechanism to extract cache information
based on CCSIDR register as the architecture explicitly states no
inference about the actual sizes of caches based on CCSIDR registers.

Commit 9a802431 ("arm64: cacheinfo: add support to override cache
levels via device tree") had already provided options to override cache
information from the device tree.

This patch adds the information about L1 and L2 caches on all variants
of Juno platform.

Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

This patch adds the missing CoreSight STM component definition to the
device tree of all the juno variants(r0,r1,r2)

STM component is connected to different funnels depending on Juno
platform variant.
Reviewed-and-tested-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: NMike Leach <mike.leach@linaro.org>
[sudeep.holla@arm.com: minor changelog update and reorganising the STM
	node back into juno-base.dtsi to avoid duplication]
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Currently the Coresight components are supported only on Juno r0
variant. In preparation to add support to Juno r1/r2 variants, this
patch refactors the existing coresight device nodes so that r1/r2
support can be added easily.

It also cleans up some of the device node names which were previously
named so as they were confused as the labels rather than the node names.
Reviewed-and-tested-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Currently juno-clock.dtsi and juno-base.dtsi are nested badly inside
the device tree structure. It's generally good practice to ensure that
individual dtsi stand by themselves at the top of the file.

This patch removes the nesting of the above mentioned dtsi files and
makes them independent.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

The core and the cluster sleep state entry latencies can't be same as
cluster sleep involves more work compared to core level e.g. shared
cache maintenance.

Experiments have shown on an average about 100us more latency for the
cluster sleep state compared to the core level sleep. This patch fixes
the entry latency for the cluster sleep state.

Fixes: 28e10a8f ("arm64: dts: juno: Add idle-states to device tree")
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: "Jon Medhurst (Tixy)" <tixy@linaro.org>
Reviewed-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This patch adds cpu capacity-dmips-mhz information to Juno R0 boards.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jon Medhurst <tixy@linaro.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: NJuri Lelli <juri.lelli@arm.com>
[sudeep.holla@arm.com: reformated subject and updated changelog]
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

Most of the debug-related components on Juno are located in the coreSight
subsystem while others are located in the Cortex-Axx clusters, the SCP
subsystem, and in the main system.

Each core in the two processor clusters contain an Embedded Trace
Macrocell(ETM) which generates real-time trace information that trace
tools can use and an ATB trace output that is sent to a funnel before
going to the CoreSight subsystem.

The trace output signals combine with two trace expansions using another
funnel and fed into the Embedded Trace FIFO(ETF0).

The output trace data stream of the funnel is then replicated before it
is sent to either the:
- Trace Port Interface Unit(TPIU), that sends it out using the trace port.
- ETR that can write the trace data to memory located in the application
  memory space

Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Acked-by: NMathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>

This patch adds idle-states bindings data collected through a set of
benchmarking experiments (latency and energy consumption) on Juno
boards. Latencies data represents the worst case scenarios as required
by the DT idle-states bindings.
Signed-off-by: NJon Medhurst <tixy@linaro.org>
Acked-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

This patch adds the CPU clocks so that the CPU DVFS can be enabled.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>

This patch adds CPU topology on Juno. It will be useful for ther other
IP blocks depending on this topology.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Cc: Jon Medhurst (Tixy) <tixy@linaro.org>

The A57 and A53 PMUs in Juno support different events, so describe them
separately in both the Juno and Juno R1 DTs.
Signed-off-by: NMark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Acked-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>

Prepare the device tree for adding more boards based on Juno r0.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NJon Medhurst <tixy@linaro.org>
Acked-by: NSudeep Holla <sudeep.holla@arm.com>

During the review of the Juno DT files I've noticed that the GIC
node label had two digits swapped leading to a different address
being shown in the /sys/devices fs.

Sudeep also pointed that public revisions of the Juno documentation
list a different frequency for the FAXI system than what the one
I've been using when creating the DT file. Verified with the firmware
people to be the correct value in the shipped systems.
Reported-by: NSudeep Holla <sudeep.holla@arm.com>
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Acked-by: NSudeep Holla <sudeep.holla@arm.com>
Acked-by: NJon Medhurst <tixy@linaro.org>

Make the Juno .dts robust against potential reordering of the CPU nodes
by adding an explicit interrupt-affinity property to the PMU node. While
we're at it, fix the PMU interrupts numbers too.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: NLiviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

Commit 5d425c18 ("arm64: kernel: add support for cpu cache
information") adds cacheinfo support for ARM64. Since there's no
architectural way of detecting the cpus that share particular cache,
device tree can be used and the core cacheinfo already supports the
same.

This patch adds the L2 cache topology on Juno board, FVP/RTSM and
foundation models.
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

Without explicit command-line parameters, the Juno UART ends up running
at 57600 baud in the kernel, which is at odds with the 115200 baud used
by the rest of the firmware. Since commit 7914a7c5 now lets us
fix this by specifying default options in stdout-path, do so.
Acked-by: NMark Rutland <mark.rutland@arm.com>
Signed-off-by: NRobin Murphy <robin.murphy@arm.com>
Signed-off-by: NOlof Johansson <olof@lixom.net>

The Cortex-A5x TRM states in paragraph "9.2 Generic Timer functional
description" that generic timers provide an active-LOW interrupt
output. Fix the device trees to correctly describe this.

While doing this update the CPU mask to match the number of described
CPUs as well.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>

This adds support for ARM's Juno development board (rev 0).
It enables most of the board peripherals: UART, I2C, USB, MMC and
100Mb ethernet. There is no support at the moment for clock setting
and HDLCD driver which depends on it.
Signed-off-by: NLiviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: NArnd Bergmann <arnd@arndb.de>