- 09 12月, 2017 1 次提交
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由 Neil Armstrong 提交于
The clock-names for pclk was wrongly set to "core", but the bindings specifies "pclk". This was not cathed until the legacy non-documented bindings were removed. Reported-by: NAndreas Färber <afaerber@suse.de> Fixes: f72d6f60 ("ARM64: dts: meson-gx: use stable UART bindings with correct gate clock") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 29 10月, 2017 1 次提交
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由 Jerome Brunet 提交于
Add gpio interrupt controller to Amlogic GX family SoCs Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 12 10月, 2017 4 次提交
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由 Neil Armstrong 提交于
This year, Amlogic updated the ARM Trusted Firmware reserved memory mapping for Meson GXL SoCs and products sold since May 2017 uses this alternate reserved memory mapping. But products had been sold using the previous mapping. This issue has been explained in [1] and a dynamic solution is yet to be found to avoid loosing another 3Mbytes of reservable memory. In the meantime, this patch adds this alternate memory zone only for the GXL and GXM SoCs since GXBB based new products stopped earlier. [1] http://lists.infradead.org/pipermail/linux-amlogic/2017-October/004860.html Fixes: bba8e3f4 ("ARM64: dts: meson-gx: Add firmware reserved memory zones") Reported-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Since the Data Strobe pin is optional, take it out of the default eMMC pins and add a separate entry. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Tested-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Jerome Brunet 提交于
TEST_N has moved from the EE controller to the AO controller so the gpio-ranges need to adjusted for it Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Jerome Brunet 提交于
Remove pin offset on the EE controller. Meson pinctrl no longer has this quirk Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 06 9月, 2017 2 次提交
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由 Jerome Brunet 提交于
Add the pinctrl to switch mmc clk pins in gpio (pulled down) mode. This is necessary to be able to gate the clk outside of the SoC while keeping it running in the controller Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Jerome Brunet 提交于
Now that the clock source 0 is properly described in the CCF, use it instead of assuming the default value (xtal) Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 23 8月, 2017 2 次提交
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由 Neil Armstrong 提交于
This patch adds the AO CEC node in all the HDMI enabled boards DTS. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
The AO clkc needs to be updated to new bindings with an system control parent node and moving the clkc node as subnode. Also adds the SoC specific compatible following the bindings requirements. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 09 8月, 2017 1 次提交
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由 Helmut Klein 提交于
This patch switches to the stable UART bindings but also add the correct gate clock to the non-AO UART nodes for GXBB and GXL SoCs. Acked-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NHelmut Klein <hgkr.klein@gmail.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 17 6月, 2017 1 次提交
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由 Neil Armstrong 提交于
Add nodes for the SPICC controller on GX common dtsi, GXBB and GXL dtsi files. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 31 5月, 2017 5 次提交
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由 Neil Armstrong 提交于
This patch adds the SPICC Controller pins nodes for Amlogic GXL SoCs. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
The Amlogic Meson GXL SoCs embeds an 10/100 Ethernet PHY, this patchs adds the Link and Activity LEDs signals pins nodes. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add the AO and EE domain CEC pins nodes for the Amlogic Meson GXL SoCs. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
The pull-enable register base was wrongly copied from the GXBB pinctrl node, but was not used yet. Fixes: fb0fe922 ("ARM64: dts: meson-gxl: Add pinctrl nodes") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
The gpio-range was badly added on the GXL dtsi, the AO pin count is 10 instead of 14. Fixes: 84412e4e ("ARM64: dts: meson-gxl: Add gpio-ranges properties") Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 18 5月, 2017 1 次提交
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由 Andreas Färber 提交于
Sort nodes referenced by label alphabetically. Signed-off-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 05 4月, 2017 1 次提交
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由 Neil Armstrong 提交于
Add HDMI output and connector nodes. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 28 3月, 2017 3 次提交
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由 jbrunet 提交于
Add EE and AO domains pins for the spdif output to the gxl device tree. Acked-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 jbrunet 提交于
Add EE and AO domains pins for the i2s output clocks and data the gxl device tree Acked-by: NKevin Hilman <khilman@baylibre.com> Signed-off-by: NJerome Brunet <jbrunet@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 25 3月, 2017 1 次提交
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由 Neil Armstrong 提交于
Add pinctrl pins nodes following the additions of missing pins in the pinctrl driver. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 24 3月, 2017 2 次提交
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由 Neil Armstrong 提交于
Since we know the GXBB and GXL/GXM share more hardware, we can safely move the remaining peripheral nodes present in the GXBB dtsi to the common GX dtsi. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
This adds the new DT nodes for the missing PWM pins in the EE and AO domain. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 31 1月, 2017 1 次提交
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由 Martin Blumenstingl 提交于
Add the SAR ADC to meson-gxbb.dtsi and meson-gxl.dtsi. GXBB provides a 10-bit ADC while GXL and GXM provide a 12-bit ADC. Some boards use resistor ladder buttons connected through one of the ADC channels. On newer devices (GXL and GXM) some boards use pull-ups/downs to change the resistance (and thus the ADC value) on one of the ADC channels to indicate the board revision. Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NNeil Armstrong <narmstrong@baylibre.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 28 1月, 2017 1 次提交
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由 Martin Blumenstingl 提交于
This adds the pwm_ao_b pin to allow boards which have an LED connected to GPIOAO_9 to use the leds-pwm driver (by activating the pwm_AO_ab node and passing the pwm_ao_b_pin pinctrl-reference). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 19 1月, 2017 3 次提交
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由 Neil Armstrong 提交于
Add pinctrl nodes for HDMI HPD and DDC pins modes for Amlogic Meson GXL and GXBB SoCs. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
This adds pinctrl group nodes for the CTS and RTS pins of each serial controller. This makes it possible to enable the CTS and RTS pins which are controlled by the serial controller hardware (through the meson_uart driver). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Tested-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Martin Blumenstingl 提交于
This adds the missing node for the uart_AO_B port to the meson-gx.dtsi (as this is supported by GXBB, GXL and GXM) along with the required pinctrl pins. This is required as some boards are using it (the boards from the Khadas VIM series for example have it exposed on the pin headers). Signed-off-by: NMartin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 04 1月, 2017 2 次提交
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由 Neil Armstrong 提交于
Add Video Processing Unit and CVBS Output nodes, and enable CVBS on selected boards. Reviewed-by: NLaurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Kevin Hilman 提交于
Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 16 11月, 2016 5 次提交
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由 Neil Armstrong 提交于
Add Ethernet node with Internal PHY selection for the Amlogic GXL SoCs Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add MMC/SD/SDIO nodes clock attributes for Amlogic Meson GXL. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add i2c nodes clock attributes for Amlogic Meson GXL. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add clock node for Amlogic Meson GXL. The GXBB compatible is retained since the GXBB clock tree is used for now. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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由 Neil Armstrong 提交于
Add pinctrl nodes and pin definitions for Amlogic Meson GXL. Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> [khilman: use GXBB include until GXL pinctrl support merged] Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 18 10月, 2016 1 次提交
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由 Carlo Caione 提交于
This patch introduces the basic support for the Amlogic S905X (Meson GXL) and for the Amlogic evaluation board P212. No documentation has been released yet for this SoC, so for now only the bare minimum has been added in the DT. Acked-by: NRob Herring <robh@kernel.org> Reviewed-by: NAndreas Färber <afaerber@suse.de> Signed-off-by: NCarlo Caione <carlo@endlessm.com> Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com>
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- 31 3月, 2016 2 次提交
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由 Kevin Hilman 提交于
Add minimal DT files for the Amlogic P20x development boards, based on the Amlogic S905/GXBB SoC. Cc: Andreas Färber <afaerber@suse.de> Cc: Carlo Caione <carlo@endlessm.com> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Acked-by: NArnd Bergmann <arnd@arndb.de>
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由 Kevin Hilman 提交于
Apparently, it's not valid to have an alias point to a disabled device. Fix this by moving the aliases that are used (serial0) into the files that use them, and remove aliases to disabled devices (serial1). Suggested-by: NArnd Bergmann <arnd@arndb.de> Signed-off-by: NKevin Hilman <khilman@baylibre.com> Reviewed-by: NAndreas Färber <afaerber@suse.de> Acked-by: NArnd Bergmann <arnd@arndb.de>
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