1. 28 3月, 2019 1 次提交
    • F
      ACPICA: Clear status of GPEs before enabling them · c8b1917c
      Furquan Shaikh 提交于
      Commit 18996f2d ("ACPICA: Events: Stop unconditionally clearing
      ACPI IRQs during suspend/resume") was added to stop clearing event
      status bits unconditionally in the system-wide suspend and resume
      paths. This was done because of an issue with a laptop lid appaering
      to be closed even when it was used to wake up the system from suspend
      (see https://bugzilla.kernel.org/show_bug.cgi?id=196249), which
      happened because event status bits were cleared unconditionally on
      system resume. Though this change fixed the issue in the resume path,
      it introduced regressions in a few suspend paths.
      
      First regression was reported and fixed in the S5 entry path by commit
      fa85015c ("ACPICA: Clear status of all events when entering S5").
      Next regression was reported and fixed for all legacy sleep paths by
      commit f317c7dc ("ACPICA: Clear status of all events when entering
      sleep states").  However, there still is a suspend-to-idle regression,
      since suspend-to-idle does not follow the legacy sleep paths.
      
      In the suspend-to-idle case, wakeup is enabled as part of device
      suspend.  If the status bits of wakeup GPEs are set when they are
      enabled, it causes a premature system wakeup to occur.
      
      To address that problem, partially revert commit 18996f2d to
      restore GPE status bits clearing before the GPE is enabled in
      acpi_ev_enable_gpe().
      
      Fixes: 18996f2d ("ACPICA: Events: Stop unconditionally clearing ACPI IRQs during suspend/resume")
      Signed-off-by: NFurquan Shaikh <furquan@google.com>
      Cc: 4.17+ <stable@vger.kernel.org> # 4.17+
      [ rjw: Subject & changelog ]
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      c8b1917c
  2. 25 2月, 2019 1 次提交
  3. 16 1月, 2019 1 次提交
  4. 25 5月, 2018 1 次提交
  5. 19 3月, 2018 3 次提交
    • E
      ACPICA: adding SPDX headers · 95857638
      Erik Schmauss 提交于
      Signed-off-by: NErik Schmauss <erik.schmauss@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      95857638
    • E
      ACPICA: Events: Add parallel GPE handling support to fix potential redundant _Exx evaluations · 8d593495
      Erik Schmauss 提交于
      There is a risk that a GPE method/handler may be invoked twice. Let's
      consider a case, both GPE0(RAW_HANDLER) and GPE1(_Exx) is triggered.
       =======================================+=============================
       IRQ handler (top-half)                 |IRQ polling
       =======================================+=============================
       acpi_ev_detect_gpe()                   |
         LOCK()                               |
         READ (GPE0-7 enable/status registers)|
         ^^^^^^^^^^^^ROOT CAUSE^^^^^^^^^^^^^^^|
         Walk GPE0                            |
           UNLOCK()                           |LOCK()
           Invoke GPE0 RAW_HANDLER            |READ (GPE1 enable/status bit)
                                              |acpi_ev_gpe_dispatch(irq=false)
                                              |  CLEAR (GPE1 enable bit)
                                              |  CLEAR (GPE1 status bit)
           LOCK()                             |UNLOCK()
         Walk GPE1                            +=============================
           acpi_ev_gpe_dispatch(irq=true)     |IRQ polling (defer)
             CLEAR (GPE1 enable bit)          +=============================
             CLEAR (GPE1 status bit)          |acpi_ev_async_execute_gpe_method()
         Walk others                          |  Evaluate GPE1 _Exx
         fi                                   |  acpi_ev_async_enable_gpe()
         UNLOCK()                             |    LOCK()
       =======================================+    SET (GPE enable bit)
       IRQ handler (bottom-half)              |    UNLOCK()
       =======================================+
       acpi_ev_async_execute_gpe_method()     |
         Evaluate GPE1 _Exx                   |
         acpi_ev_async_enable_gpe()           |
           LOCK()                             |
           SET (GPE1 enable bit)              |
           UNLOCK()                           |
       =======================================+=============================
      
      If acpi_ev_detect_gpe() is only invoked from the IRQ context, there won't be
      more than one _Lxx/_Exx evaluations for one status bit flagging if the IRQ
      handlers controlled by the underlying IRQ chip/driver (ex. APIC) are run in
      serial. Note that, this is a known potential gap and we had an approach,
      locking entire non-raw-handler processes in the top-half IRQ handler and
      handling all raw-handlers out of the locked loop to be friendly to those
      IRQ chip/driver. But the approach is too complicated while the issue is not
      so real, thus ACPICA treated such issue (if any) as a parallelism/quality
      issue of the underlying IRQ chip/driver to stop putting it on the radar.
      Bug in link #1 is suspiciously reflecting the same cause, and if so, it can
      also be fixed by this simpler approach.
      
      But it will be no excuse an ACPICA problem now if ACPICA starts to poll
      IRQs itself. In the changed scenario, _Exx will be evaluated from the task
      context due to new ACPICA provided "polling after enabling GPEs" mechanism.
      And the above figure uses edge-triggered GPEs demonstrating the possibility
      of evaluating _Exx twice for one status bit flagging.
      
      As a conclusion, there is now an increased chance of evaluating _Lxx/_Exx
      more than once for one status bit flagging.
      
      However this is still not a real problem if the _Lxx/_Exx checks the
      underlying hardware IRQ reasoning and finally just changes the 2nd and the
      follow-up evaluations into no-ops. Note that _Lxx should always be written
      in this way as a level-trigger GPE could have it's status wrongly
      duplicated by the underlying IRQ delivery mechanisms. But _Exx may have
      very low quality BIOS by BIOS to trigger real issues. For example, trigger
      duplicated button notifications.
      
      To solve this issue, we need to stop reading a bunch of enable/status
      register bits, but read only one GPE's enable/status bit. And GPE status
      register's W1C nature ensures that acknowledging one GPE won't affect
      another GPEs' status bits. Thus the hardware GPE architecture has already
      provided us with the mechanism of implementing such parallelism.
      
      So we can lock around one GPE handling process to achieve the parallelism:
      1. If we can incorporate GPE enable bit check in detection and ensure the
         atomicity of the following process (top-half IRQ handler):
          READ (enable/status bit)
          if (enabled && raised)
            CLEAR (enable bit)
         and handle the GPE after this process, we can ensure that we will only
         invoke GPE handler once for one status bit flagging.
      2. In addtion for edge-triggered GPEs, if we can ensure the atomicity of
         the following process (top-half IRQ handler):
          READ (enable/status bit)
          if (enabled && raised)
            CLEAR (enable bit)
            CLEAR (status bit)
         and handle the GPE after this process, we can ensure that we will only
         invoke GPE handler once for one status bit flagging.
      
      By doing a cleanup in this way, we can remove duplicate GPE handling code
      and ensure that all logics are collected in 1 function. And the function
      will be safe for both IRQ interrupt and IRQ polling, and will be safe for
      us to release and re-acquire acpi_gbl_gpe_lock at any time rather than raw
      handler only during the top-half IRQ handler. Lv Zheng.
      
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=196703 [#1]
      Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NErik Schmauss <erik.schmauss@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      8d593495
    • E
      ACPICA: Events: Stop unconditionally clearing ACPI IRQs during suspend/resume · 18996f2d
      Erik Schmauss 提交于
      Unconditionally clearing ACPI IRQs during suspend/resume can lead to
      unexpected IRQ losts. This patch fixes this issue by removing such IRQ
      clearing code.
      
      If this patch triggers regression, the regression should be in the GPE
      handlers that cannot correctly determine some spurious triggered events as
      no-ops. Please report any regression related to this commit to the ACPI
      component on kernel bugzilla. Lv Zheng.
      
      Link: https://bugzilla.kernel.org/show_bug.cgi?id=196249Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Reported-and-tested-by: NEric Bakula-Davis <ericbakuladavis@gmail.com>
      Tested-by: NMika Westerberg <mika.westerberg@linux.intel.com>
      Signed-off-by: NErik Schmauss <erik.schmauss@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      18996f2d
  6. 06 2月, 2018 1 次提交
  7. 04 10月, 2017 1 次提交
  8. 09 2月, 2017 1 次提交
  9. 13 8月, 2016 1 次提交
    • L
      ACPICA: Events: Introduce acpi_mask_gpe() to implement GPE masking mechanism · 2af52c2b
      Lv Zheng 提交于
      ACPICA commit 23a417ca406a527e7ae1710893e59a8b6db30e14
      
      There is a facility in Linux, developers can control the enabling/disabling
      of a GPE via /sys/firmware/acpi/interrupts/gpexx. This is mainly for
      debugging purposes.
      
      But many users expect to use this facility to implement quirks to mask a
      specific GPE when there is a gap in Linux causing this GPE to flood. This
      is not working correctly because currently this facility invokes
      enabling/disabling counting based GPE driver APIs:
       acpi_enable_gpe()/acpi_disable_gpe()
      and the GPE drivers can still affect the count to mess up the GPE
      masking purposes.
      
      However, most of the IRQ chip designs allow masking/unmasking IRQs via a
      masking bit which is different from the enabled bit to achieve the same
      purpose. But the GPE hardware doesn't contain such a feature, this brings
      the trouble.
      
      In this patch, we introduce a software mechanism to implement the GPE
      masking feature, and acpi_mask_gpe() are provided to the OSPMs to
      mask/unmask GPEs in the above mentioned situation instead of
      acpi_enable_gpe()/acpi_disable_gpe(). ACPICA BZ 1102. Lv Zheng.
      
      Link: https://github.com/acpica/acpica/commit/23a417ca
      Link: https://bugs.acpica.org/show_bug.cgi?id=1102Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      2af52c2b
  10. 05 5月, 2016 1 次提交
  11. 16 1月, 2016 1 次提交
  12. 01 1月, 2016 1 次提交
  13. 15 4月, 2015 1 次提交
    • R
      ACPICA: Store GPE register enable masks upfront · 0ee0d349
      Rafael J. Wysocki 提交于
      It is reported that ACPI interrupts do not work any more on
      Dell Latitude D600 after commit c50f13c6 (ACPICA: Save
      current masks of enabled GPEs after enable register writes).
      The problem turns out to be related to the fact that the
      enable_mask and enable_for_run GPE bit masks are not in
      sync (in the absence of any system suspend/resume events)
      for at least one GPE register on that machine.
      
      Address this problem by writing the enable_for_run mask into
      enable_mask as soon as enable_for_run is updated instead of
      doing that only after the subsequent register write has
      succeeded.  For consistency, update acpi_hw_gpe_enable_write()
      to store the bit mask to be written into the GPE register
      in enable_mask unconditionally before the write.
      
      Since the ACPI_GPE_SAVE_MASK flag is not necessary any more after
      that, drop it along with the symbols depending on it.
      Reported-and-tested-by: NJim Bos <jim876@xs4all.nl>
      Fixes: c50f13c6 (ACPICA: Save current masks of enabled GPEs after enable register writes)
      Cc: 3.19+ <stable@vger.kernel.org> # 3.19+
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      0ee0d349
  14. 05 2月, 2015 7 次提交
    • L
      ACPICA: Events: Introduce ACPI_GPE_DISPATCH_RAW_HANDLER to fix 2 issues for the current GPE APIs · 0d0988af
      Lv Zheng 提交于
      ACPICA commit 199cad16530a45aea2bec98e528866e20c5927e1
      
      Since whether the GPE should be disabled/enabled/cleared should only be
      determined by the GPE driver's state machine:
      1. GPE should be disabled if the driver wants to switch to the GPE polling
         mode when a GPE storm condition is indicated and should be enabled if
         the driver wants to switch back to the GPE interrupt mode when all of
         the storm conditions are cleared. The conditions should be protected by
         the driver's specific lock.
      2. GPE should be enabled if the driver has accepted more than one request
         and should be disabled if the driver has completed all of the requests.
         The request count should be protected by the driver's specific lock.
      3. GPE should be cleared either when the driver is about to handle an edge
         triggered GPE or when the driver has completed to handle a level
         triggered GPE. The handling code should be protected by the driver's
         specific lock.
      Thus the GPE enabling/disabling/clearing operations are likely to be
      performed with the driver's specific lock held while we currently cannot do
      this. This is because:
      1. We have the acpi_gbl_gpe_lock held before invoking the GPE driver's
         handler. Driver's specific lock is likely to be held inside of the
         handler, thus we can see some dead lock issues due to the reversed
         locking order or recursive locking. In order to solve such dead lock
         issues, we need to unlock the acpi_gbl_gpe_lock before invoking the
         handler. BZ 1100.
      2. Since GPE disabling/enabling/clearing should be determined by the GPE
         driver's state machine, we shouldn't perform such operations inside of
         ACPICA for a GPE handler to mess up the driver's state machine. BZ 1101.
      
      Originally this patch includes a logic to flush GPE handlers, it is dropped
      due to the following reasons:
      1. This is a different issue;
      2. Linux OSL has fixed this by flushing SCI in acpi_os_wait_events_complete().
      We will pick up this topic when the Linux OSL fix turns out to be not
      sufficient.
      
      Note that currently the internal operations and the acpi_gbl_gpe_lock are
      also used by ACPI_GPE_DISPATCH_METHOD and ACPI_GPE_DISPATCH_NOTIFY. In
      order not to introduce regressions, we add one
      ACPI_GPE_DISPATCH_RAW_HANDLER type to be distiguished from
      ACPI_GPE_DISPATCH_HANDLER. For which the acpi_gbl_gpe_lock is unlocked before
      invoking the GPE handler and the internal enabling/disabling operations are
      bypassed to allow drivers to perform them at a proper position using the
      GPE APIs and ACPI_GPE_DISPATCH_RAW_HANDLER users should invoke acpi_set_gpe()
      instead of acpi_enable_gpe()/acpi_disable_gpe() to bypass the internal GPE
      clearing code in acpi_enable_gpe(). Lv Zheng.
      
      Known issues:
      1. Edge-triggered GPE lost for frequent enablings
         On some buggy silicon platforms, GPE enable line may not be directly
         wired to the GPE trigger line. In that case, when GPE enabling is
         frequently performed for edge-triggered GPEs, GPE status may stay set
         without being triggered.
         This patch may maginify this problem as it allows GPE enabling to be
         parallel performed during the process the GPEs are handled.
         This is an existing issue, because:
         1. For task context:
            Current ACPI_GPE_DISPATCH_METHOD practices have proven that this
            isn't a real issue - we can re-enable edge-triggered GPE in a work
            queue where the GPE status bit might already be set.
         2. For IRQ context:
            This can even happen when the GPE enabling occurs before returning
            from the GPE handler and after unlocking the GPE lock.
         Thus currently no code is included to protect this.
      
      Link: https://github.com/acpica/acpica/commit/199cad16Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      0d0988af
    • D
      ACPICA: Update Copyright headers to 2015 · 82a80941
      David E. Box 提交于
      ACPICA commit 8990e73ab2aa15d6a0068b860ab54feff25bee36
      
      Link: https://github.com/acpica/acpica/commit/8990e73aSigned-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      82a80941
    • L
      ACPICA: Events: Cleanup GPE dispatcher type obtaining code · 7c43312a
      Lv Zheng 提交于
      ACPICA commit 7926d5ca9452c87f866938dcea8f12e1efb58f89
      
      There is an issue in acpi_install_gpe_handler() and acpi_remove_gpe_handler().
      The code to obtain the GPE dispatcher type from the Handler->original_flags
      is wrong:
          if (((Handler->original_flags & ACPI_GPE_DISPATCH_METHOD) ||
               (Handler->original_flags & ACPI_GPE_DISPATCH_NOTIFY)) &&
      ACPI_GPE_DISPATCH_NOTIFY is 0x03 and ACPI_GPE_DISPATCH_METHOD is 0x02, thus
      this statement is TRUE for the following dispatcher types:
          0x01 (ACPI_GPE_DISPATCH_HANDLER): not expected
          0x02 (ACPI_GPE_DISPATCH_METHOD): expected
          0x03 (ACPI_GPE_DISPATCH_NOTIFY): expected
      
      There is no functional issue due to this because Handler->original_flags is
      only set in acpi_install_gpe_handler(), and an earlier checker has excluded
      the ACPI_GPE_DISPATCH_HANDLER:
          if ((gpe_event_info->Flags & ACPI_GPE_DISPATCH_MASK) ==
                  ACPI_GPE_DISPATCH_HANDLER)
          {
              Status = AE_ALREADY_EXISTS;
              goto free_and_exit;
          }
          ...
          Handler->original_flags = (u8) (gpe_event_info->Flags &
              (ACPI_GPE_XRUPT_TYPE_MASK | ACPI_GPE_DISPATCH_MASK));
      
      We need to clean this up before modifying the GPE dispatcher type values.
      
      In order to prevent such issue from happening in the future, this patch
      introduces ACPI_GPE_DISPATCH_TYPE() macro to be used to obtain the GPE
      dispatcher types. Lv Zheng.
      
      Link: https://github.com/acpica/acpica/commit/7926d5caSigned-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      7c43312a
    • L
      ACPICA: Events: Cleanup to move acpi_gbl_global_event_handler invocation out... · 779ba5a3
      Lv Zheng 提交于
      ACPICA: Events: Cleanup to move acpi_gbl_global_event_handler invocation out of acpi_ev_gpe_dispatch()
      
      ACPICA commit 04f25acdd4f655ae33f83de789bb5f4b7790171c
      
      This patch follows acpi_ev_fixed_event_detect(), which invokes
      acpi_gbl_global_event_handler instead of invoking it in
      acpi_ev_fixed_event_dispatch(), moves acpi_gbl_global_event_handler from
      acpi_ev_gpe_dispatch() to acpi_ev_gpe_detect(). This makes further cleanups
      around acpi_ev_gpe_dispatch() simpler. Lv Zheng.
      
      Link: https://github.com/acpica/acpica/commit/04f25acdSigned-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      779ba5a3
    • D
      ACPICA: Events: Fix uninitialized variable · b7be6883
      David E. Box 提交于
      ACPICA commit 8e21180050270897499652e922c6a41b8eb388b6
      
      Recent changes to acpi_ev_asynch_execute_gpe_method left Status
      variable uninitialized before use. Initialize to AE_OK.
      
      Link: https://github.com/acpica/acpica/commit/8e211800Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      b7be6883
    • L
      ACPICA: Events: Remove acpi_ev_valid_gpe_event() due to current restriction · b18da580
      Lv Zheng 提交于
      ACPICA commit 8823b44ff53859ab24ecfcfd3fba8cc56b17d223
      
      Currently we rely on the logic that GPE blocks will never be deleted,
      otherwise we can be broken by the race between acpi_ev_create_gpe_block(),
      acpi_ev_delete_gpe_block() and acpi_ev_gpe_detect().
      On the other hand, if we want to protect GPE block creation/deletion, we
      need to use a different synchronization facility to protect the period
      between acpi_ev_gpe_dispatch() and acpi_ev_asynch_enable_gpe(). Which leaves us
      no choice but abandoning the ACPI_MTX_EVENTS used during this period.
      
      This patch removes ACPI_MTX_EVENTS used during this period and the
      acpi_ev_valid_gpe_event() to reflect current restriction. Lv Zheng.
      
      Link: https://github.com/acpica/acpica/commit/8823b44fSigned-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      b18da580
    • L
      ACPICA: Events: Remove duplicated sanity check in acpi_ev_enable_gpe() · 833bb931
      Lv Zheng 提交于
      ACPICA commit ca10324788bc9bdaf47fa9e51145129c1299144d
      
      This patch deletes a sanity check from acpi_ev_enable_gpe().
      
      This kind of check is already done in
      acpi_enable_gpe()/acpi_remove_gpe_handler()/acpi_update_all_gpes() before invoking
      acpi_ev_enable_gpe():
      1. acpi_enable_gpe(): same check (skip if DISPATCH_NONE) is now implemented.
      2. acpi_remove_gpe_handler(): a more strict check (skip if !DISPATCH_HANDLER)
                                 is implemented.
      3. acpi_update_all_gpes(): a more strict check (skip if DISPATCH_NONE ||
                              DISPATCH_HANDLER || CAN_WAKE)
      4. acpi_set_gpe(): since it is invoked by the OSPM driver where the GPE
                       handler is known to be available, such check isn't needed.
      So we can simply remove this duplicated check from acpi_ev_enable_gpe().
      Lv Zheng.
      
      Link: https://github.com/acpica/acpica/commit/ca103247Signed-off-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NDavid E. Box <david.e.box@linux.intel.com>
      Signed-off-by: NBob Moore <robert.moore@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      833bb931
  15. 03 12月, 2014 1 次提交
  16. 02 12月, 2014 1 次提交
    • R
      ACPICA: Save current masks of enabled GPEs after enable register writes · c50f13c6
      Rafael J. Wysocki 提交于
      There is a race condition between acpi_hw_disable_all_gpes() or
      acpi_enable_all_wakeup_gpes() and acpi_ev_asynch_enable_gpe() such
      that if the latter wins the race, it may mistakenly enable a GPE
      disabled by the former.  This may lead to premature system wakeups
      during system suspend and potentially to more serious consequences.
      
      The source of the problem is how acpi_hw_low_set_gpe() works when
      passed ACPI_GPE_CONDITIONAL_ENABLE as the second argument.  In that
      case, the GPE will be enabled if the corresponding bit is set in the
      enable_for_run mask of the GPE enable register containing that bit.
      However, acpi_hw_disable_all_gpes() and acpi_enable_all_wakeup_gpes()
      don't modify the enable_for_run masks of GPE registers when writing
      to them.  In consequence, if acpi_ev_asynch_enable_gpe(), which
      eventually calls acpi_hw_low_set_gpe() with the second argument
      equal to ACPI_GPE_CONDITIONAL_ENABLE, is executed in parallel with
      one of these functions, it may reverse changes made by them.
      
      To fix the problem, introduce a new enable_mask field in struct
      acpi_gpe_register_info in which to store the current mask of
      enabled GPEs and modify acpi_hw_low_set_gpe() to take this
      mask into account instead of enable_for_run when its second
      argument is equal to ACPI_GPE_CONDITIONAL_ENABLE.  Also modify
      the low-level routines called by acpi_hw_disable_all_gpes(),
      acpi_enable_all_wakeup_gpes() and acpi_enable_all_runtime_gpes()
      to update the enable_mask masks of GPE registers after all
      (successful) writes to those registers.
      Acked-by: NLv Zheng <lv.zheng@intel.com>
      Signed-off-by: NRafael J. Wysocki <rafael.j.wysocki@intel.com>
      c50f13c6
  17. 21 10月, 2014 1 次提交
  18. 07 7月, 2014 1 次提交
  19. 07 5月, 2014 1 次提交
  20. 11 2月, 2014 1 次提交
  21. 31 10月, 2013 1 次提交
  22. 30 10月, 2013 1 次提交
  23. 16 6月, 2013 1 次提交
  24. 02 6月, 2013 1 次提交
  25. 12 3月, 2013 1 次提交
  26. 25 1月, 2013 1 次提交
  27. 10 1月, 2013 3 次提交
  28. 15 11月, 2012 1 次提交
  29. 21 9月, 2012 2 次提交