- 14 12月, 2012 2 次提交
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由 Ralf Baechle 提交于
Nobody seems to be interested anymore and upstream also never had an ethernet driver. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Normally r4k_dma_cache_inv should only ever be called with cacheline aligned addresses. If however, it isn't there is the theoretical possibility of data corruption. There is no correct way of handling this and anyway, it should only happen if the DMA API is used incorrectly so drop There is a different corruption scenario with these CACHE instructions removed but again there is no way of handling this correctly and it can be triggered only through incorrect use of the DMA API. So just get rid of the complexity. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Reported-by: NJames Rodriguez <jamesr@juniper.net>
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- 14 9月, 2012 1 次提交
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由 Steven J. Hill 提交于
Signed-off-by: NSteven J. Hill <sjhill@mips.com>
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- 19 7月, 2012 1 次提交
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由 Douglas Leung 提交于
This affects certain 4Kc cores. Signed-off-by: NDouglas Leung <douglas@mips.com> Signed-off-by: NSteven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3855/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 07 7月, 2012 1 次提交
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由 Steven J. Hill 提交于
[ralf@linux-mips.org: Fixed whitespace damage.] Signed-off-by: NSteven J. Hill <sjhill@mips.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3773/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 5月, 2012 1 次提交
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由 David Daney 提交于
Signed-off-by: NDavid Daney <david.daney@cavium.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/3821/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 3月, 2012 1 次提交
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由 David Howells 提交于
Disintegrate asm/system.h for MIPS. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NRalf Baechle <ralf@linux-mips.org> cc: linux-mips@linux-mips.org
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- 20 3月, 2012 1 次提交
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由 Cong Wang 提交于
Signed-off-by: NCong Wang <amwang@redhat.com>
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- 08 12月, 2011 1 次提交
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由 Jayachandran C 提交于
Add support for Netlogic's XLP MIPS SoC. This patch adds: * XLP processor ID in cpu_probe.c and asm/cpu.h * XLP case to asm/module.h * CPU_XLP case to mm/tlbex.c * minor change to r4k cache handling to ignore XLP secondary cache * XLP cpu overrides to mach-netlogic/cpu-feature-overrides.h Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2966/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 20 10月, 2011 1 次提交
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由 Ralf Baechle 提交于
Until now flush_kernel_vmap_range() and invalidate_kernel_vmap_range() did not exist on MIPS resulting in heavy cache corruption on XFS filesystems. Left for the post-3.0 time: optimization and make this work with highmem, too. Since the combination of highmem + cache aliases atm doesn't work this isn't a regression. Signed-off-by: NRalf Baechle <ralf@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2505/
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- 26 7月, 2011 1 次提交
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由 Kevin Cernekee 提交于
On processors with deep write buffers, it is likely that many cycles will pass between a CACHE instruction and the time the data actually gets written out to DRAM. Add a SYNC instruction to ensure that the buffers get emptied before the flush functions return. Actual problem seen in the wild: 1) dma_alloc_coherent() allocates cached memory 2) memset() is called to clear the new pages 3) dma_cache_wback_inv() is called to flush the zero data out to memory 4) dma_alloc_coherent() returns an uncached (kseg1) pointer to the freshly allocated pages 5) Caller writes data through the kseg1 pointer 6) Buffered writeback data finally gets flushed out to DRAM 7) Part of caller's data is inexplicably zeroed out This patch adds SYNC between steps 3 and 4, which fixed the problem. Signed-off-by: NKevin Cernekee <cernekee@gmail.com> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 19 5月, 2011 1 次提交
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由 Jayachandran C 提交于
CPU_XLR case added to mm/tlbex.c CPU_XLR case added to mm/c-r4k.c for PINDEX attribute Feature overrides for XLR cpu. Signed-off-by: NJayachandran C <jayachandranc@netlogicmicro.com> To: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/2333/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 11 5月, 2011 1 次提交
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由 Ralf Baechle 提交于
CC arch/mips/mm/c-r4k.o arch/mips/mm/c-r4k.c: In function 'probe_scache': arch/mips/mm/c-r4k.c:1078:6: error: variable 'tmp' set but not used [-Werror=unused-but-set-variable] cc1: all warnings being treated as errors Older GCC versions didn't warn about the unused variable tmp because it was getting initialized. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 06 4月, 2011 1 次提交
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由 Justin P. Mattock 提交于
Signed-off-by: NJustin P. Mattock <justinmattock@gmail.com> Acked-by: NDavid S. Miller <davem@davemloft.net> Signed-off-by: NJiri Kosina <jkosina@suse.cz>
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- 30 10月, 2010 2 次提交
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由 Ralf Baechle 提交于
All callers were passing in 1 anyway. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 25 6月, 2009 1 次提交
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由 Ralf Baechle 提交于
Some of the were relying into smp.h being dragged in by another header which of course is fragile. <asm/cpu-info.h> uses smp_processor_id() only in macros and including smp.h there leads to an include loop, so don't change cpu-info.h. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 6月, 2009 1 次提交
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由 Kevin Cernekee 提交于
Signed-off-by: NKevin Cernekee <cernekee@gmail.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 14 5月, 2009 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 3月, 2009 1 次提交
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由 Manuel Lauss 提交于
This patch removes the various CPU_AU1??? model constants in favor of a single CPU_ALCHEMY one. All currently existing Alchemy models are identical in terms of cpu core and cache size/organization. The parts of the mips kernel which need to know the exact CPU revision extract it from the c0_prid register already; and finally nothing else in-tree depends on those any more. Should a new variant with slightly different "company options" and/or "processor revision" bits in c0_prid appear, it will be supported immediately (minus an exact model string in cpuinfo). Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 24 3月, 2009 1 次提交
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由 Shinya Kuribayashi 提交于
Signed-off-by: NShinya Kuribayashi <shinya.kuribayashi@necel.com> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 31 1月, 2009 1 次提交
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由 Ralf Baechle 提交于
See discussion e9c3a7c20901051031y528d0d31r18d44c5096c59e0@mail.gmail.com. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 06 9月, 2008 1 次提交
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由 Thomas Bogendoerfer 提交于
trap_init issues flush_icache_range(), which uses ipi functions to get icache flushing done on all cpus. But this is done before interrupts are enabled and caused WARN_ON messages. This changeset introduces a new local_flush_icache_range() and uses it before interrupts (and additional CPUs) are enabled to avoid this problem. Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 26 6月, 2008 1 次提交
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由 Jens Axboe 提交于
It's never used and the comments refer to nonatomic and retry interchangably. So get rid of it. Acked-by: NJeremy Fitzhardinge <jeremy.fitzhardinge@citrix.com> Signed-off-by: NJens Axboe <jens.axboe@oracle.com>
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- 16 6月, 2008 2 次提交
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由 Ralf Baechle 提交于
Assuming the call of kmap_coherent in local_r4k_flush_cache_page doesn't need fixing this was skipped in fcae549295bcae801ac48fc1c2030ab8cc487020. Turns out it needed the same change after all. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Build error was caused by commit 35133692. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 29 4月, 2008 2 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Chris Dearman 提交于
Slightly tacky, but there is a precedent in the sparc archirecture code. Signed-off-by: NChris Dearman <chris@mips.com> Signed-off-by: NAtsushi Nemoto <anemo@mba.ocn.ne.jp> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 08 4月, 2008 1 次提交
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由 Ralf Baechle 提交于
flush_cache_vmap / flush_cache_vunmap were calling flush_cache_all which - having been deprecated - turned into a nop ... Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 3月, 2008 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 20 2月, 2008 1 次提交
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由 Ralf Baechle 提交于
So far flush_cache_range() did't consider the I-cache largely because it did rarely ever matter to real world code. This was working primarily because normally code and data are don't share the same pages - with the exception of MIPS16 code which uses address constants embedded between the code. The following sequence of events may break the code: o MIPS16 executable being loaded o dynamic linker relocates the address constants embedded into the code: o Uses mprotect(2) to make code pages PROT_READ|PROT_WRITE o Performs the actual relocations by writing to the pages which likely are COW. Because no PROT_EXEC is set I-cache coherence will not be considered. o Uses mprotect(2) to switch code pages back to PROT_READ|PROT_EXEC. This results in a call to flush_cache_range() which also does not consider I-caches. o => executing the page just having been relocated may now result in the I-cache getting refilled with stale data from memory. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 03 2月, 2008 1 次提交
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由 Joe Perches 提交于
Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NAdrian Bunk <bunk@kernel.org>
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- 29 1月, 2008 4 次提交
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由 Manuel Lauss 提交于
This patch adds IDs for new Au1200 variants: Au1210 and Au1250. They are essentially identical to the Au1200 except for the Au1210 which has a different SoC-ID in the PRId register [bits 31:24]. The Au1250 is a "Au1200 V0.2". Signed-off-by: NManuel Lauss <mano@roarinelk.homelinux.net> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Thomas Bogendoerfer 提交于
R10k non coherent machines need a real dma cache invalidate to get rid of speculative stores in cache. For other machines this promises a slight speedup. Signed-off-by: NThomas Bogendoerfer <tsbogend@alpha.franken.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 16 11月, 2007 1 次提交
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由 Ralf Baechle 提交于
The recent switch of the Sibyte SOCs from the processor specific cache managment code in c-sb1.c to c-r4k.c lost this old hack [MIPS] Hack for SB1 cache issues Removing flush_icache_page a while ago broke SB1 which was using an empty flush_data_cache_page function. This glues things well enough so a more efficient but also more intrusive solution can be found later. Signed-Off-By: NThiemo Seufer <ths@networkno.de> Signed-off-by: NRalf Baechle <ralf@linux-mips.org> in the hope it was no longer needed. As it turns it still is so resurrect it until there is a better solution. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 30 10月, 2007 1 次提交
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由 Ralf Baechle 提交于
When GDB writes a breakpoint into address area of inferior process the kernel needs to invalidate the modified memory in the inferior which is done by calling flush_cache_page which in turns calls r4k_flush_cache_page and local_r4k_flush_cache_page for VSMP or SMTC kernel via r4k_on_each_cpu(). As the VSMP and SMTC SMP kernels for 34K are running on a single shared caches it is possible to get away without interprocessor function calls. This optimization is implemented in r4k_on_each_cpu, so local_r4k_flush_cache_page is only ever called on the local CPU. This is where the following code in local_r4k_flush_cache_page() strikes: /* * If ownes no valid ASID yet, cannot possibly have gotten * this page into the cache. */ if (cpu_context(smp_processor_id(), mm) == 0) return; On VSMP and SMTC had a function of cpu_context() for each CPU(TC). So in case another CPU than the CPU executing local_r4k_cache_flush_page has not accessed the mm but one of the other CPUs has there may be data to be flushed in the cache yet local_r4k_cache_flush_page will falsely return leaving the I-cache inconsistent for the breakpoint. While the issue was discovered with GDB it also exists in local_r4k_flush_cache_range() and local_r4k_flush_cache(). Fixed by introducing a new function has_valid_asid which on MT kernels returns true if a mm is active on any processor in the system. This is relativly expensive since for memory acccesses in that loop cache misses have to be assumed but it seems the most viable solution for 2.6.23 and older -stable kernels. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 17 10月, 2007 1 次提交
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由 Ralf Baechle 提交于
This should help making bug reports for the gadzillion of cores with all their configuration and synthesis options more useful. Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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- 12 10月, 2007 1 次提交
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由 Ralf Baechle 提交于
Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
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