1. 31 10月, 2018 3 次提交
  2. 28 10月, 2018 1 次提交
    • J
      parisc: Fix A500 boot crash · c9fa406f
      John David Anglin 提交于
      I believe the following change will fix the cache/TLB inconsistency
      observed by Meelis.  After changing the page table entries, we need to
      flush the cache and TLB to ensure that we don't have any stale PTE
      values in the cache or TLB.
      
      The alternative patching is done after all CPUs are running.  Thus, we
      need to flush the whole cache and TLB.
      
      I included the init section in the range modified by map_pages as
      suggested by Helge.  Some routines in the init section may require
      patching.
      Signed-off-by: NJohn David Anglin <dave.anglin@bell.net>
      Signed-off-by: NHelge Deller <deller@gmx.de>
      c9fa406f
  3. 27 10月, 2018 27 次提交
  4. 26 10月, 2018 9 次提交