This patch adds an SPI master implementation that operates on top of an
underlying TI-SSP port.
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NCyril Chemparathy <cyril@ti.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>
Signed-off-by: NKevin Hilman <khilman@ti.com>

The Atheros AR71XX/AR724X/AR913X SoCs have a built-in SPI controller. This
patch implements a driver for that.
Signed-off-by: NGabor Juhos <juhosg@openwrt.org>
Cc: David Brownell <dbrownell@users.sourceforge.net>
Cc: spi-devel-general@lists.sourceforge.net
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: linux-mips@linux-mips.org
Cc: Imre Kaloz <kaloz@openwrt.org>
Cc: Luis R. Rodriguez <lrodriguez@atheros.com>
Cc: Cliff Holden <Cliff.Holden@Atheros.com>
Cc: Kathy Giori <Kathy.Giori@Atheros.com>
Patchwork: https://patchwork.linux-mips.org/patch/1960/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>

This patch enables the existing S3C64XX series SPI driver for S5P64X0
and removed dependency on EXPERIMENTAL because we don't need it now.

v3: Changed dependency of S3C64XX_DMA
v2: Removed dependency on EXPERIMENTAL
Signed-off-by: NAbhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: NSangbeom Kim <sbkim73@samsung.com>
Acked-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

1. Change the Kconfig to include i.MX53
2. add devtype entry for i.MX53
Signed-off-by: NYong Shen <yong.shen@freescale.com>
Acked-by: NSascha Hauer <s.hauer@pengutronix.de>
Acked-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

dw_spi driver in upstream only supports PIO mode, and this patch
will support it to cowork with the Designware dma controller used
on Intel Moorestown platform, at the same time it provides a general
framework to support dw_spi core to cowork with dma controllers on
other platforms

It has been tested with a Option GTM501L 3G modem and Infenion 60x60
modem. To use DMA mode, DMA controller 2 of Moorestown has to be enabled

Also change the dma interface suggested by Linus Walleij.
Acked-by: NLinus Walleij <linus.walleij@stericsson.com>
Signed-off-by: NFeng Tang <feng.tang@intel.com>
[Typo fix and renames to match intel_mid_dma renaming]
Signed-off-by: NVinod Koul <vinod.koul@intel.com>
Signed-off-by: NAlan Cox <alan@linux.intel.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Sodaville's SPI controller is very much the same as in PXA25x. The
difference:
- The RX/TX FIFO is only 4 words deep instead of 16
- No DMA support
- The SPI controller offers a CS functionality
Signed-off-by: NSebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: NDirk Brandewie <dirk.brandewie@gmail.com>

Add manufacturer name to the Kconfig prompt string and move
the controller name to the begining of the prompt.

This helps locate the driver easily among the list of existing
drivers.

While at it, also add information about being able to build
the driver as module.
Tested-By: NBrian Niebuhr <bniebuhr@efjohnson.com>
Signed-off-by: NSekhar Nori <nsekhar@ti.com>

Now that the of_platform_bus_type has been merged with the platform
bus type, a single platform driver can handle both OF and non-OF use
cases.  This patch merges the OF support into the platform driver.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Tested-by: NMichal Simek <monstr@monstr.eu>

This patch merges the platform driver support into the main body of
xilinx_spi.c in preparation for merging the OF and non-OF support
code.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
Tested-by: NMichal Simek <monstr@monstr.eu>

v2 changes:
  from Thierry Reding:
    * add "select TEGRA_SYSTEM_DMA" to Kconfig
  from Grant Likely:
    * add oneline description to header
    * inline references to DRIVER_NAME
    * inline references to BUSY_TIMEOUT
    * open coded bytes_per_word()
    * spi_readl/writel -> spi_tegra_readl/writel
    * move transfer validation to spi_tegra_transfer
    * don't request_mem_region iomem as platform bus does that for us
    * __exit -> __devexit

v3 changes:
  from Russell King:
    * put request_mem_region back int
  from Grant Likely:
    * remove #undef DEBUG
    * add SLINK_ to register bit defines
    * remove unused bytes_per_word
    * make spi_tegra_readl/writel static linine
    * various refactoring for clarity
    * mark err if BSY bit is not cleared after 1000 retries
    * move spinlock to protect setting of RDY bit
    * subsys_initcall -> module_init

v3 changes:
  from Grant Likely:
    * update spi_tegra to use PTR_ERRless dma API

v4 changes:
  from Grant Likely:
    * remove empty spi_tegra_cleanup fucntion
    * allow device ids of -1
Signed-off-by: NErik Gilling <konkers@android.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Cc: Thierry Reding <thierry.reding@avionic-design.de>
Cc: Russell King <linux@arm.linux.org.uk>

spi: tegra: cleanups from upstream review

Change-Id: Icecf7e64efcb39de072a15234ba1faa4bad40d25
Signed-off-by: NErik Gilling <konkers@android.com>

Add eSPI controller support based on the library code spi_fsl_lib.c.

The eSPI controller is newer controller 85xx/Pxxx devices supported.
There're some differences comparing to the SPI controller:

1. Has different register map and different bit definition
   So leave the code operated the register to the driver code, not
   the common code.

2. Support 4 dedicated chip selects
   The software can't controll the chip selects directly, The SPCOM[CS]
   field is used to select which chip selects is used, and the
   SPCOM[TRANLEN] field is set to tell the controller how long the CS
   signal need to be asserted. So the driver doesn't need the chipselect
   related function when transfering data, just set corresponding register
   fields to controll the chipseclect.

3. Different Transmit/Receive FIFO access register behavior
   For SPI controller, the Tx/Rx FIFO access register can hold only
   one character regardless of the character length, but for eSPI
   controller, the register can hold 4 or 2 characters according to
   the character lengths. Access the Tx/Rx FIFO access register of the
   eSPI controller will shift out/in 4/2 characters one time. For SPI
   subsystem, the command and data are put into different transfers, so
   we need to combine all the transfers to one transfer in order to pass
   the transfer to eSPI controller.

4. The max transaction length limitation
   The max transaction length one time is limitted by the SPCOM[TRANSLEN]
   field which is 0xFFFF. When used mkfs.ext2 command to create ext2
   filesystem on the flash, the read length will exceed the max value of
   the SPCOM[TRANSLEN] field.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Refactor the common code in file spi_fsl_spi.c to spi_fsl_lib.c used
by SPI/eSPI controller driver as a library, and leave the QE/CPM SPI
controller code in the SPI controller driver spi_fsl_spi.c.

Because the register map of the SPI controller and eSPI controller
is so different, also leave the code operated the register to the
driver code, not the common code.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This will pave the way to refactor out the common code which can be used
by the eSPI controller driver, and rename the SPI controller dirver to the
file spi_fsl_spi.c.
Signed-off-by: NMingkai Hu <Mingkai.hu@freescale.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

The original didn't specify Topcliff in the config prompt text.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Topcliff PCH is the platform controller hub that is going to be used
in Intel's upcoming general embedded platform. All IO peripherals in
Topcliff PCH are actually devices sitting on AMBA bus.  This patch
adds a driver for the SPI bus integrated into the Topcliff device.
Signed-off-by: NMasayuki Ohtake <masa-korg@dsn.okisemi.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

i.MX51 comes with two eCSPI interfaces (that are quite different from
what was known before---the tried and tested Freescale way) and a CSPI
interface that is identical to the devices found on i.MX25 and i.MX35.

This patch is a merge of two very similar patches (by Jason Wang and Sascha
Hauer resp.) plus a (now hopefully correct) reimplementation of the
clock calculation.
Acked-by: NJason Wang <jason77.wang@gmail.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

This has the advantage not to need to much cpu_is_... macros.  Still more
when imx51 support is added which has two different spi interfaces which
would introduce additional checks on the device id.

With this setup it's not possible for the compiler anymore to detect the
unused functions, so four additional kconfig symbols are introduced to
ifdef out the unneeded functions in the callback array and all these
functions are marked with __maybe_unused to suppress the corresponding
gcc warnings.

Comparing the driver footprint with and without the patch for a mx27
kernel yields:

add/remove: 2/0 grow/shrink: 2/0 up/down: 280/0 (280)
function                                     old     new   delta
spi_imx_devtype                                -     192    +192
spi_imx_probe                                980    1032     +52
spi_imx_devtype_data                           -      32     +32
spi_imx_setupxfer                            276     280      +4

Later when the platform code is updated to use the platform ids, the
autodetection can be removed which will make the driver a bit smaller
again.  (~60 Bytes in my test.)
Acked-by: NJason Wang <jason77.wang@gmail.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Acked-by: NJason Wang <jason77.wang@gmail.com>
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>

Signed-off-by: NJohn Rigby <jcrigby@gmail.com>
Signed-off-by: NAnatolij Gustschin <agust@denx.de>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds an SPI master driver for the Cirrus EP93xx SPI controller found
in EP93xx chips.
Signed-off-by: NMika Westerberg <mika.westerberg@iki.fi>
Signed-off-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: NH Hartley Sweeten <hsweeten@visionengravers.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Change dependency to ARCH_OMAP2PLUS to allow systems based on
omap24xx, omap34xx or omap44xx

Cc: spi-devel-general@lists.sourceforge.net
Signed-off-by: NSyed Rafiuddin <rafiuddin.syed@ti.com>
Signed-off-by: NAbraham Arce <x0066660@ti.com>
Signed-off-by: NTony Lindgren <tony@atomide.com>

Replace ARCH_OMAP34XX with ARCH_OMAP3
Signed-off-by: NTony Lindgren <tony@atomide.com>

Convert ARCH_OMAP24XX to ARCH_OMAP2
Signed-off-by: NTony Lindgren <tony@atomide.com>

dw_spi_mmio is dependent on the clock framework. This marks it as such
in Kconfig.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Adds a memory-mapped I/O dw_spi platform device.
Signed-off-by: NJean-Hugues Deschenes <jean-hugues.deschenes@octasic.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add support for the QSPI controller found some on Freescale/Motorola
Coldfire MCUs.

Full duplex, active high cs, spi modes 0-3 and word sizes 8-16 bits are
supported.  The hardware drives the MISO, MOSI and SCLK lines, but the chip
selects are managed via GPIO and must be configured by the board code.

The QSPI controller has an 80 byte buffer which allows us to transfer up to 16
words at a time.  For transfers longer than 16 words, we split the buffer in
half so we can update in one half while the controller is operating on the
other half.  Interrupt latencies then ultimately limits our sustained thru-put
to something less than half the maximum speed supported by the part.
Signed-off-by: NSteven King <sfking@fdwdc.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds support for a SPI master driver for the
DaVinci series of SOCs
Signed-off-by: NSandeep Paulraj <s-paulraj@ti.com>
Signed-off-by: NMark A. Greer <mgreer@mvista.com>
Signed-off-by: NPhilby John <pjohn@in.mvista.com>
Signed-off-by: NSudhakar Rajashekhara <sudhakar.raj@ti.com>
Signed-off-by: NKevin Hilman <khilman@deeprootsystems.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Each SPI controller has exactly one CS line and as such doesn't
provide for multi-cs. We implement a workaround to support
multi-cs by _not_ configuring the mux'ed CS pin for each SPI
controller. The CS mechanism is assumed to be fully machine
specific - the driver doesn't even assume some GPIO pin is used
to control the CS.

The driver selects between DMA and POLLING mode depending upon
the xfer size - DMA mode for xfers bigger than FIFO size, POLLING
mode otherwise.

The driver has been designed to be capable of running SoCs since
s3c64xx and till date, for that reason some of the register fields
have been passed via, SoC specific, platform data.
Signed-off-by: NJassi Brar <jassi.brar@samsung.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Add pseudo-DMA by FIQ to the S3C24XX SPI driver.  This allows the driver
to get DMA-like performance where there are either no free DMA channels or
when doing transfers that required both TX and RX data paths.

Since this patch requires the addition of an assembly file to hold the FIQ
code, we rename the module (instead of adding a rename of the .c file to
this patch).  We expect most users are loading this via udev and thus
there should be no change to the userland configuration.
Signed-off-by: NBen Dooks <ben@simtec.co.uk>
Signed-off-by: NSimtec Linux Team <linux@simtec.co.uk>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Driver for the Designware SPI core, it supports multipul interfaces like
PCI/APB etc.  User can use "dw_apb_ssi_db.pdf" from Synopsys as HW
datasheet.

[randy.dunlap@oracle.com: fix build]
[akpm@linux-foundation.org: build fix]
Signed-off-by: NFeng Tang <feng.tang@intel.com>
Cc: David Brownell <david-b@pacbell.net>
Signed-off-by: NRandy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: NAndrew Morton <akpm@linux-foundation.org>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This change adds the OMAP SPI 100k driver created by
Fabrice Crohas <fcrohas@gmail.com>.  This SPI bus is found on
OMAP7xx-series smartphones, and for many, the touchscreen is
attached to this bus.

The lion's share of the work was done by Fabrice on this driver --
I am merely porting it from the Linwizard project on his behalf.
Signed-off-by: NCory Maccarrone <darkstar6262@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

Signed-off-by: NWan ZongShun <mcuos.com@gmail.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch is V2 of SPI Master support for the SuperH MSIOF.
Full duplex, spi mode 0-3, active high cs, 3-wire and lsb
first should all be supported, but the driver has so far
only been tested with "mmc_spi".

The MSIOF hardware comes with 32-bit FIFOs for receive and
transmit, and this driver simply breaks the SPI messages
into FIFO-sized chunks. The MSIOF hardware manages the pins
for clock, receive and transmit (sck/miso/mosi), but the chip
select pin is managed by software and must be configured as
a regular GPIO pin by the board code.

Performance wise there is still room for improvement, but
on a Ecovec board with the built-in sh7724 MSIOF0 this driver
gets Mini-sd read speeds of about half a megabyte per second.

Future work include better clock setup and merging of 8-bit
transfers into 32-bit words to reduce interrupt load and
improve throughput.
Signed-off-by: NMagnus Damm <damm@opensource.se>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds in a platform device driver using the xilinx_spi common module.
Tested-by: NJohn Linn <John.Linn@xilinx.com>
Signed-off-by: NRichard Röjfors <richard.rojfors@mocean-labs.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds in support for the DS570 IP.

It's register compatible with the DS464, but adds support for 8/16/32 SPI.

The 8/16/32 support is added by attaching callbacks reading/writing the
proper amount of data. To indicate to the driver which amount of bits
to use a new field is introduced in the platform data struct.
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Tested-by: NJohn Linn <John.Linn@xilinx.com>
Signed-off-by: NRichard Röjfors <richard.rojfors@mocean-labs.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch changes the out_(be)(8|16|32) and in_(be)(8|16|32) calls to 32 bits ioread/iowrite.

The read and write function are attached to the internal struct as callbacks, callback
is selected depending on endianess.

This will also build on platforms not supporting the in/out calls for instance x86.
Acked-by: NGrant Likely <grant.likely@secretlab.ca>
Tested-by: NJohn Linn <John.Linn@xilinx.com>
Signed-off-by: NRichard Röjfors <richard.rojfors@mocean-labs.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch splits the xilinx_spi driver into a generic part and a
OF driver part.

The reason for this is to later add in a platform driver as well.
Tested-by: NJohn Linn <John.Linn@xilinx.com>
Signed-off-by: NRichard Röjfors <richard.rojfors@mocean-labs.com>
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>

This patch adds QE buffer descriptors mode support for the
spi_mpc8xxx driver, and as a side effect we now support CPM1
and CPM2 SPI controllers.

That means that today we support almost all MPC SPI controllers:

- MPC834x-style controllers (support PIO mode only);
- CPM1 and CPM2 controllers (support DMA mode only);
- QE SPI controllers in CPU mode (PIO mode with shift quirks);
- QE SPI controllers in buffer descriptors (DMA) mode;

The only controller we don't currently support is a newer eSPI
(with a dedicated chip selects and a bit different registers map).
Signed-off-by: NAnton Vorontsov <avorontsov@ru.mvista.com>
Acked-by: NDavid Brownell <dbrownell@users.sourceforge.net>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>

Adds support for the dedicated SPI device on the Freescale MPC5200(b)
SoC.
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>