1. 05 11月, 2019 1 次提交
  2. 01 11月, 2019 3 次提交
  3. 31 10月, 2019 3 次提交
  4. 19 10月, 2019 1 次提交
  5. 04 10月, 2019 1 次提交
  6. 03 10月, 2019 1 次提交
    • M
      drm/i915/dp: Fix dsc bpp calculations, v5. · cffb4c3e
      Maarten Lankhorst 提交于
      There was a integer wraparound when mode_clock became too high,
      and we didn't correct for the FEC overhead factor when dividing,
      with the calculations breaking at HBR3.
      
      As a result our calculated bpp was way too high, and the link width
      limitation never came into effect.
      
      Print out the resulting bpp calcululations as a sanity check, just
      in case we ever have to debug it later on again.
      
      We also used the wrong factor for FEC. While bspec mentions 2.4%,
      all the calculations use 1/0.972261, and the same ratio should be
      applied to data M/N as well, so use it there when FEC is enabled.
      
      This fixes the FIFO underrun we are seeing with FEC enabled.
      
      Changes since v2:
      - Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville)
      - Fix initial hardware readout for FEC. (Ville)
      Changes since v3:
      - Remove bogus fec_to_mode_clock. (Ville)
      Changes since v4:
      - Use the correct register for icl. (Ville)
      - Split hw readout to a separate patch.
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Fixes: d9218c8f ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC")
      Cc: <stable@vger.kernel.org> # v5.0+
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.comReviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      (cherry picked from commit ed06efb8)
      Signed-off-by: NRodrigo Vivi <rodrigo.vivi@intel.com>
      cffb4c3e
  7. 02 10月, 2019 1 次提交
  8. 01 10月, 2019 1 次提交
  9. 25 9月, 2019 1 次提交
    • M
      drm/i915/dp: Fix dsc bpp calculations, v5. · ed06efb8
      Maarten Lankhorst 提交于
      There was a integer wraparound when mode_clock became too high,
      and we didn't correct for the FEC overhead factor when dividing,
      with the calculations breaking at HBR3.
      
      As a result our calculated bpp was way too high, and the link width
      limitation never came into effect.
      
      Print out the resulting bpp calcululations as a sanity check, just
      in case we ever have to debug it later on again.
      
      We also used the wrong factor for FEC. While bspec mentions 2.4%,
      all the calculations use 1/0.972261, and the same ratio should be
      applied to data M/N as well, so use it there when FEC is enabled.
      
      This fixes the FIFO underrun we are seeing with FEC enabled.
      
      Changes since v2:
      - Handle fec_enable in intel_link_compute_m_n, so only data M/N is adjusted. (Ville)
      - Fix initial hardware readout for FEC. (Ville)
      Changes since v3:
      - Remove bogus fec_to_mode_clock. (Ville)
      Changes since v4:
      - Use the correct register for icl. (Ville)
      - Split hw readout to a separate patch.
      Signed-off-by: NMaarten Lankhorst <maarten.lankhorst@linux.intel.com>
      Fixes: d9218c8f ("drm/i915/dp: Add helpers for Compressed BPP and Slice Count for DSC")
      Cc: <stable@vger.kernel.org> # v5.0+
      Cc: Manasi Navare <manasi.d.navare@intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190925082110.17439-1-maarten.lankhorst@linux.intel.comReviewed-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      ed06efb8
  10. 09 9月, 2019 1 次提交
  11. 06 9月, 2019 1 次提交
  12. 05 9月, 2019 1 次提交
  13. 04 9月, 2019 1 次提交
  14. 02 9月, 2019 1 次提交
  15. 27 8月, 2019 1 次提交
  16. 22 8月, 2019 1 次提交
    • V
      drm/i915: Do not create a new max_bpc prop for MST connectors · 1b9bd096
      Ville Syrjälä 提交于
      We're not allowed to create new properties after device registration
      so for MST connectors we need to either create the max_bpc property
      earlier, or we reuse one we already have. Let's do the latter apporach
      since the corresponding SST connector already has the prop and its
      min/max are correct also for the MST connector.
      
      The problem was highlighted by commit 4f5368b5 ("drm/kms:
      Catch mode_object lifetime errors") which results in the following
      spew:
      [ 1330.878941] WARNING: CPU: 2 PID: 1554 at drivers/gpu/drm/drm_mode_object.c:45 __drm_mode_object_add+0xa0/0xb0 [drm]
      ...
      [ 1330.879008] Call Trace:
      [ 1330.879023]  drm_property_create+0xba/0x180 [drm]
      [ 1330.879036]  drm_property_create_range+0x15/0x30 [drm]
      [ 1330.879048]  drm_connector_attach_max_bpc_property+0x62/0x80 [drm]
      [ 1330.879086]  intel_dp_add_mst_connector+0x11f/0x140 [i915]
      [ 1330.879094]  drm_dp_add_port.isra.20+0x20b/0x440 [drm_kms_helper]
      ...
      
      Cc: stable@vger.kernel.org
      Cc: Lyude Paul <lyude@redhat.com>
      Cc: sunpeng.li@amd.com
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Cc: Sean Paul <sean@poorly.run>
      Fixes: 5ca0ef8a ("drm/i915: Add max_bpc property for DP MST")
      Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
      Link: https://patchwork.freedesktop.org/patch/msgid/20190820161657.9658-1-ville.syrjala@linux.intel.comReviewed-by: NJosé Roberto de Souza <jose.souza@intel.com>
      Reviewed-by: NLyude Paul <lyude@redhat.com>
      1b9bd096
  17. 21 8月, 2019 1 次提交
  18. 17 8月, 2019 1 次提交
  19. 07 8月, 2019 2 次提交
  20. 17 6月, 2019 1 次提交
  21. 14 6月, 2019 1 次提交
  22. 03 5月, 2019 1 次提交
  23. 30 4月, 2019 2 次提交
  24. 12 4月, 2019 1 次提交
  25. 08 4月, 2019 4 次提交
  26. 27 3月, 2019 5 次提交
  27. 06 2月, 2019 1 次提交