- 19 8月, 2014 2 次提交
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由 Feng Kan 提交于
This change is made to preserve the GIC v2 bypass bits in the GIC_CPU_CTRL register (also known as the GICC_CTLR register in spec). This code will preserve all bits configured by the bootloader regarding v2 bypass group bits. In the X-Gene platform, the bypass functionality is not used and bypass bits should not be changed by the kernel gic code as it could lead to incorrect behavior. Signed-off-by: NFeng Kan <fkan@apm.com> Reviewed-by: NVinayak Kale <vkale@apm.com> Reviewed-by: NAnup Patel <apatel@apm.com> Link: https://lkml.kernel.org/r/1406757419-18729-3-git-send-email-fkan@apm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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由 Feng Kan 提交于
This is to cleanup some hex numbers used in the code and replace them with defines to make the code cleaner. Signed-off-by: NFeng Kan <fkan@apm.com> Reviewed-by: NAnup Patel <apatel@apm.com> Link: https://lkml.kernel.org/r/1406757419-18729-2-git-send-email-fkan@apm.comSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 19 5月, 2014 1 次提交
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由 Haojian Zhuang 提交于
Bit[9:0] is interrupt ID field in GICC_IAR. Bit[12:10] is CPU ID field, and others are reserved. So we should use GICC_IAR_INT_ID_MASK to get interrupt ID. It's not a good way to use ~0x1c00 (CPU ID field) to get interrupt ID. Signed-off-by: NHaojian Zhuang <haojian.zhuang@linaro.org> Link: https://lkml.kernel.org/r/1399795571-17231-3-git-send-email-haojian.zhuang@linaro.orgSigned-off-by: NJason Cooper <jason@lakedaemon.net>
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- 05 2月, 2014 1 次提交
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由 Sricharan R 提交于
In some socs the gic can be preceded by a crossbar IP which routes the peripheral interrupts to the gic inputs. The peripheral interrupts are associated with a fixed crossbar input line and the crossbar routes that to one of the free gic input line. The DT entries for peripherals provides the fixed crossbar input line as its interrupt number and the mapping code should associate this with a free gic input line. This patch adds the support inside the gic irqchip to handle such routable irqs. The routable irqs are registered in a linear domain. The registered routable domain's callback should be implemented to get a free irq and to configure the IP to route it. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Santosh Shilimkar <santosh.shilimkar@ti.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Tony Lindgren <tony@atomide.com> Cc: Rajendra Nayak <rnayak@ti.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: Grant Likely <grant.likely@linaro.org> Cc: Rob Herring <rob.herring@calxeda.com> Signed-off-by: NSricharan R <r.sricharan@ti.com> Reviewed-by: NThomas Gleixner <tglx@linutronix.de> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NLinus Walleij <linus.walleij@linaro.org>
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- 22 12月, 2013 1 次提交
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由 Christoffer Dall 提交于
Define CPU interface offsets for the GICC_ABPR, GICC_APR, and GICC_IIDR registers. Define distributor registers for the GICD_SPENDSGIR and the GICD_CPENDSGIR. KVM/ARM needs to know about these definitions to fully support save/restore of the VGIC. Also define some masks and shifts for the various GICH_VMCR fields. Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: NMarc Zyngier <marc.zyngier@arm.com> Signed-off-by: NChristoffer Dall <christoffer.dall@linaro.org>
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- 24 9月, 2013 2 次提交
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由 Nicolas Pitre 提交于
The regular gic_raise_softirq() takes as input a CPU mask which is not adequate when we need to send an IPI to a CPU which is not represented in the kernel to GIC mapping. That is the case with the b.L switcher when GIC migration to the inbound CPU has not yet occurred. Signed-off-by: NNicolas Pitre <nico@linaro.org>
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由 Nicolas Pitre 提交于
In order to have early assembly code signal other CPUs in the system, we need to get the physical address for the SGIR register used to send IPIs. Because the register will be used with a precomputed CPU interface ID number, there is no need for any locking in the assembly code where this register is written to. Signed-off-by: NNicolas Pitre <nico@linaro.org>
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- 29 8月, 2013 1 次提交
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由 Nicolas Pitre 提交于
When processors are about to hit low power states, the assertion of standbywfi signal, triggered by the wfi instruction, is essential to entering low power modes. If an IRQ is pending on the processor at the time wfi is issued, the wfi instruction completes and the processor restarts execution without asserting the standbywfi signal. Depending on the platform power controller HW this behaviour can be acceptable or not; if this behaviour must be prevented software should be provided with a way to disable the routing of interrupts to the core IRQ pins. On systems where raw GIC distributor interrupts are connected to the power controller as wake-up events (hence the power controller still senses IRQs and can wake up cores upon IRQ pending), the GIC CPU interface can be disabled on power down, so that the GIC CPU IF output is gated and wfi cannot complete, thereby preventing the standbywfi issue. This patch adds a simple function to the GIC driver that allows to disable the GIC CPU IF from power down procedures. Signed-off-by: NNicolas Pitre <nico@linaro.org> Signed-off-by: NLorenzo Pieralisi <lorenzo.pieralisi@arm.com> [rewrote commit log] Signed-off-by: NOlof Johansson <olof@lixom.net>
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- 30 7月, 2013 2 次提交
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由 Nicolas Pitre 提交于
Currently, GIC IDs are hardcoded making the code dependent on the 4+4 b.L configuration. Let's allow for GIC IDs to be discovered upon switcher initialization to support other b.L configurations such as the 1+1 one, or 2+3 as on the VExpress TC2. Signed-off-by: NNicolas Pitre <nico@linaro.org>
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由 Nicolas Pitre 提交于
This is required by the big.LITTLE switcher code. The gic_migrate_target() changes the CPU interface mapping for the current CPU to redirect SGIs to the specified interface, and it also updates the target CPU for each interrupts to that CPU interface if they were targeting the current interface. Finally, pending SGIs for the current CPU are forwarded to the new interface. Because Linux does not use it, the SGI source information for the forwarded SGIs is not preserved. Neither is the source information for the SGIs sent by the current CPU to other CPUs adjusted to match the new CPU interface mapping. The required registers are banked so only the target CPU could do it. Signed-off-by: NNicolas Pitre <nico@linaro.org>
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- 27 3月, 2013 1 次提交
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由 Catalin Marinas 提交于
All the calls to gic_secondary_init() pass 0 as the first argument. Since this function is called on each CPU when starting, it can be done in a platform-independent way via a CPU notifier registered by the GIC code. Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Acked-by: NStephen Warren <swarren@nvidia.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NRob Herring <rob.herring@calxeda.com> Acked-by: NSimon Horman <horms+renesas@verge.net.au> Tested-by: NSimon Horman <horms+renesas@verge.net.au> Acked-by: NSrinidhi Kasagar <srinidhi.kasagar@stericsson.com> Tested-by: NDinh Nguyen <dinguyen@altera.com> Acked-by: NNicolas Pitre <nico@linaro.org> Tested-by: NMarc Zyngier <marc.zyngier@arm.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Will Deacon <will.deacon@arm.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Barry Song <baohua.song@csr.com>
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- 12 2月, 2013 3 次提交
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由 Marc Zyngier 提交于
The GIC include file being used by some of the KVM assembly code, wrap the C definitions with a #ifdef __ASSEMBLY__ guard. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Marc Zyngier 提交于
The GICH_* constants are defined by the GIC HW spec, and even though they only be used by KVM to begin with, define them generically in gic.h. Reviewed-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Christoffer Dall 提交于
Add missing register map offsets for the distributor and rename GIC_DIST_ACTIVE_BIT to GIC_DIST_ACTIVE_SET to be consistent. Reviewed-by: NWill Deacon <will.deacon@arm.com> Signed-off-by: NChristoffer Dall <c.dall@virtualopensystems.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 13 1月, 2013 3 次提交
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由 Rob Herring 提交于
Now that we have GIC moved to drivers/irqchip and all GIC DT init for platforms using irqchip_init, move gic.h and update the remaining includes. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Samuel Ortiz <sameo@linux.intel.com>
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由 Rob Herring 提交于
Convert all GIC DT initialization over to use common irqchip_init function. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Cc: Tony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Viresh Kumar <viresh.linux@gmail.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org>
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由 Rob Herring 提交于
Now that the GIC initialization sets up the handle_arch_irq pointer, we can remove it for all machines and make it static. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Anton Vorontsov <avorontsov@mvista.com> Cc: Kyungmin Park <kyungmin.park@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: NTony Lindgren <tony@atomide.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Cc: Dinh Nguyen <dinguyen@altera.com> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: NStephen Warren <swarren@nvidia.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Acked-by: NKukjin Kim <kgene.kim@samsung.com> Acked-by: NShawn Guo <shawn.guo@linaro.org> Acked-by: NOlof Johansson <olof@lixom.net> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 11 1月, 2013 2 次提交
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由 Rob Herring 提交于
In preparation of moving gic code to drivers/irqchip, remove the direct platform dependencies on gic_raise_softirq. Move the setup of smp_cross_call into the gic code and use arch_send_wakeup_ipi_mask function to trigger wake-up IPIs. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Russell King <linux@arm.linux.org.uk> Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Sascha Hauer <kernel@pengutronix.de> Cc: David Brown <davidb@codeaurora.org> Cc: Daniel Walker <dwalker@fifo99.com> Cc: Bryan Huntsman <bryanh@codeaurora.org> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Cc: Paul Mundt <lethal@linux-sh.org> Cc: Magnus Damm <magnus.damm@gmail.com> Acked-by: NViresh Kumar <viresh.kumar@linaro.org> Cc: Shiraz Hashim <shiraz.hashim@st.com> Acked-by: NStephen Warren <swarren@nvidia.com> Cc: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com> Cc: Linus Walleij <linus.walleij@linaro.org> Acked-by: NOlof Johansson <olof@lixom.net>
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由 Rob Herring 提交于
With multi irq handler and all GIC users converted to it, we don't need asm/hardware/gic.h to be included in assembly. Clean-up ifdefs and unnecessary includes. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Acked-by: NOlof Johansson <olof@lixom.net>
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- 16 2月, 2012 1 次提交
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由 Grant Likely 提交于
This patch removes the simplistic implementation of irq_domains and enables the powerpc infrastructure for all irq_domain users. The powerpc infrastructure includes support for complex mappings between Linux and hardware irq numbers, and can manage allocation of irq_descs. This patch also converts the few users of irq_domain_add()/irq_domain_del() to call irq_domain_add_legacy() instead. v3: Fix bug that set up too many irqs in translation range. v2: Fix removal of irq_alloc_descs() call in gic driver Signed-off-by: NGrant Likely <grant.likely@secretlab.ca> Cc: Rob Herring <rob.herring@calxeda.com> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Milton Miller <miltonm@bga.com> Tested-by: NOlof Johansson <olof@lixom.net>
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- 16 11月, 2011 3 次提交
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由 Marc Zyngier 提交于
Now that MULTI_IRQ_HANDLER is selected by all the in-tree GIC users, make it mandatory and remove the unused macros. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Marc Zyngier 提交于
Provide the GIC code with a low level handler that can be used by platforms using CONFIG_MULTI_IRQ_HANDLER. Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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由 Marc Zyngier 提交于
The GIC support code is heavily using the fact that hardware implementations are exposing banked registers. Unfortunately, it looks like at least one GIC implementation (EXYNOS) offers both the distributor and the CPU interfaces at different addresses, depending on the CPU. This problem is solved by allowing the distributor and CPU interface addresses to be per-cpu variables for the platforms that require it. The EXYNOS code is updated not to mess with the GIC internals while handling interrupts, and struct gic_chip_data is back to being private. The DT binding for the gic is updated to allow an optional "cpu-offset" value, which is used to compute the various base addresses. Finally, a new config option (GIC_NON_BANKED) is used to control this feature, so the overhead is only present on kernels compiled with support for EXYNOS. Tested on Origen (EXYNOS4) and Panda (OMAP4). Cc: Kukjin Kim <kgene.kim@samsung.com> Cc: Will Deacon <will.deacon@arm.com> Cc: Thomas Abraham <thomas.abraham@linaro.org> Acked-by: NRob Herring <rob.herring@calxeda.com> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 31 10月, 2011 3 次提交
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由 Rob Herring 提交于
Commit "ARM: gic: add irq_domain support" (b49b6ff) breaks SPARSE_IRQ on platforms with GIC. When SPARSE_IRQ is enabled, all NR_IRQS or mach_desc->nr_irqs will be allocated by arch_probe_nr_irqs(). This caused irq_alloc_descs to allocate irq_descs after the pre-allocated space. Make irq_alloc_descs search for an exact irq range and assume it has been pre-allocated on failure. For DT probing dynamic allocation is used. DT enabled platforms should set their nr_irqs to NR_IRQ_LEGACY and have all irq_chips allocate their irq_descs with irq_alloc_descs if SPARSE_IRQ is enabled. gic_init irq_start param is changed to be signed with negative meaning do dynamic Linux irq assigment. Signed-off-by: NRob Herring <rob.herring@calxeda.com>
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由 Rob Herring 提交于
This adds ARM gic interrupt controller initialization using device tree data. The initialization function is intended to be called by of_irq_init function like this: const static struct of_device_id irq_match[] = { { .compatible = "arm,cortex-a9-gic", .data = gic_of_init, }, {} }; static void __init init_irqs(void) { of_irq_init(irq_match); } Signed-off-by: NRob Herring <rob.herring@calxeda.com> Reviewed-by: NJamie Iles <jamie@jamieiles.com> Tested-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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由 Rob Herring 提交于
Convert the gic interrupt controller to use irq domains in preparation for device-tree binding and MULTI_IRQ. This allows for translation between GIC interrupt IDs and Linux irq numbers. The meaning of irq_offset has changed. It now is just the number of skipped GIC interrupt IDs for the controller. It will be 16 for primary GIC and 32 for secondary GICs. Signed-off-by: NRob Herring <rob.herring@calxeda.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Reviewed-by: NJamie Iles <jamie@jamieiles.com> Tested-by: NThomas Abraham <thomas.abraham@linaro.org> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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- 23 10月, 2011 1 次提交
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由 Marc Zyngier 提交于
This patch remove the hardcoded link between local timers and PPIs, and convert the PPI users (TWD, MCT and MSM timers) to the new *_percpu_irq interface. Also some collateral cleanup (local_timer_ack() is gone, and the interrupt handler is strictly private to each driver). PPIs are now useable for more than just the local timers. Additional testing by David Brown (msm8250 and msm8660) and Shawn Guo (imx6q). Cc: David Brown <davidb@codeaurora.org> Cc: Thomas Gleixner <tglx@linutronix.de> Acked-by: NDavid Brown <davidb@codeaurora.org> Tested-by: NDavid Brown <davidb@codeaurora.org> Tested-by: NShawn Guo <shawn.guo@linaro.org> Signed-off-by: NMarc Zyngier <marc.zyngier@arm.com>
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- 23 9月, 2011 1 次提交
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由 Colin Cross 提交于
When the cpu is powered down in a low power mode, the gic cpu interface may be reset, and when the cpu cluster is powered down, the gic distributor may also be reset. This patch uses CPU_PM_ENTER and CPU_PM_EXIT notifiers to save and restore the gic cpu interface registers, and the CPU_CLUSTER_PM_ENTER and CPU_CLUSTER_PM_EXIT notifiers to save and restore the gic distributor registers. Original-author: Gary King <gking@nvidia.com> Signed-off-by: NColin Cross <ccross@android.com> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Tested-and-Acked-by: NShawn Guo <shawn.guo@linaro.org> Tested-by: NVishwanath BS <vishwanath.bs@ti.com>
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- 20 7月, 2011 1 次提交
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由 Changhwan Youn 提交于
Since Samsung EXYNOS4210 cannot support register banking in GIC, so needs to update CPU interface base address. The 'gic_chip_data' is used for it, this patch moves gic_chip_data structure declaraton to arch/arm/include/asm/hardware/gic.h to use it. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NChanghwan Youn <chaos.youn@samsung.com> Signed-off-by: NKukjin Kim <kgene.kim@samsung.com>
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- 09 3月, 2011 1 次提交
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由 Santosh Shilimkar 提交于
Few architectures combine the GIC with an external interrupt controller. On such systems it may be necessary to update both the GIC registers and the external controller's registers to control IRQ behavior. This can be addressed in couple of possible methods. 1. Export common GIC routines along with 'struct irq_chip gic_chip' and allow architectures to have custom function by override. 2. Provide architecture specific function pointer hooks within GIC library and leave platforms to add the necessary code as part of these hooks. First one might be non-intrusive but have few shortcomings like arch needs to have there own custom gic library. Locks used should be common since it caters to same IRQs etc. Maintenance point of view also it leads to multiple file fixes. The second probably is cleaner and portable. It ensures that all the common GIC infrastructure is not touched and also provides archs to address their specific issue. Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NSantosh Shilimkar <santosh.shilimkar@ti.com> Acked-by: NColin Cross <ccross@android.com> Tested-by: NColin Cross <ccross@android.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 15 12月, 2010 4 次提交
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由 Russell King 提交于
Avoid adding nasty genirq-specific code to local timers to enable PPI interrupts. Instead, provide a gic function to do this. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Every architecture using the GIC has a gic_cpu_base_addr pointer for GIC 0 for their entry assembly code to use to decode the cause of the current interrupt. Move this into the common GIC code. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
We don't need to re-pass the base address for the CPU interfaces to the GIC for secondary CPUs, as it will never be different from the boot CPU - and even if it was, we'd overwrite the boot CPU's base address. Get rid of this argument, and rename to gic_secondary_init(). Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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由 Russell King 提交于
Provide gic_init() which initializes the GIC distributor and current CPU's GIC interface for the boot (or single) CPU. Reviewed-by: NCatalin Marinas <catalin.marinas@arm.com> Tested-by: NAbhijeet Dharmapurikar <adharmap@codeaurora.org> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 17 5月, 2009 1 次提交
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由 Russell King 提交于
The ARM SMP code wasn't properly updated for the cpumask changes, which results in smp_timer_broadcast() broadcasting ticks to non-online CPUs. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 03 8月, 2008 1 次提交
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由 Russell King 提交于
Move platform independent header files to arch/arm/include/asm, leaving those in asm/arch* and asm/plat* alone. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 15 2月, 2007 1 次提交
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由 Catalin Marinas 提交于
The current implementation only assumes one GIC to be present in the system. However, there are platforms with more than one cascaded interrupt controllers (RealView/EB MPCore for example). Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com> Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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- 19 8月, 2005 1 次提交
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由 Russell King 提交于
Add support for the ARM Generic Interrupt Controller. Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
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