- 16 9月, 2014 40 次提交
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由 Alexander Shiyan 提交于
This patch adds simple-card support to the i.MX SoCs. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Alexander Shiyan 提交于
This patch adds support for the Freescale (Motorola) i.MX1 ADS board. This change is intended to further remove non-DT support for this board. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
Add USB support for Freescale Vybrid tower. The USB hosts over-current protection signal is not connected to the PHY's over- current protection, hence we need to disable it. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
Add USB support for Colibri VF61 modules. The Colibri standard pinout defines a pin for USB over-current. However, due to lack of pinmux options, the USB hosts over-current protection signal of the Colibri standard could not be connected to the PHY's over-current protection. Hence we need to disable the over-current functionality of the USB controller. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
Add device tree node for usbmisc which controls the non-core USB registers. This is required to use the property to disable the over- current detection. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
This adds USB PHY and USB controller nodes. Vybrid SoCs have two independent USB cores which each supports DR (dual role). However, real OTG is not supported since the OTG ID pin is not available. The PHYs are located within the anadig register range, hence we need to change the length of the anadig registers. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Uwe Kleine-König 提交于
Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Marc Kleine-Budde 提交于
Signed-off-by: NMarc Kleine-Budde <mkl@pengutronix.de> [ukl: rebase from ancient kernel version] Signed-off-by: NUwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Michael Grzeschik 提交于
This patch adds pin configurations for: - csi aud6 - cspi1 uart3 - csi uart5 - cc - csi sdhc2 - csi cspi3 - sd1 cspi2 - cspi1 pwm Signed-off-by: NMichael Grzeschik <m.grzeschik@pengutronix.de> Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Markus Pargmann 提交于
The preloaded script addresses on imx25 and imx35 are different, so imx25 is not compatible with imx35-sdma unless a custom firmware is loaded. Signed-off-by: NMarkus Pargmann <mpa@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Bill Pringlemeir 提交于
The ttyLP1 is already the default console/serial port. The tower board will route ttyLP2 to the same connectors depending on the JP23/24 settings. See: http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/276457.html http://lists.infradead.org/pipermail/linux-arm-kernel/2014-July/275576.htmlSigned-off-by: NBill Pringlemeir <bpringlemeir@nbsps.com> Acked-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Anson Huang 提交于
Add thermal sensor support for i.MX6SL. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Alexander Shiyan 提交于
This patch adds basic devicetree template for i.MX1 based SoCs. Signed-off-by: NAlexander Shiyan <shc_work@mail.ru> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Philipp Zabel 提交于
Signed-off-by: NPhilipp Zabel <p.zabel@pengutronix.de> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Michael Olbrich 提交于
Signed-off-by: NMichael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Michael Olbrich 提交于
Signed-off-by: NMichael Olbrich <m.olbrich@pengutronix.de> Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Lucas Stach 提交于
Everything in the PCI specification assumes devices to be enumerable on startup. This is only possible if they have power available. A future improvement may allow this regulator to be switched off for D3hot and D3cold power states, but there is a lot of work to do the pcie host controller side for this to work. To keep things simple always enable the regulator for now. Signed-off-by: NLucas Stach <l.stach@pengutronix.de> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
The Colibri VF61 is a module which needs a carrier board to actually run. Different carrier board have different hardware support, hence we should reflect this in the device tree files. This patch adds the Colibri Evaluation Board, which supports almost all peripherals defined in the Colibri standard. Also align the compatible naming, file splitting and file naming with the scheme which was choosen for the Tegra based modules. Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
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由 Shawn Guo 提交于
Immutable branch between MFD and some ARM sub-arch maintainers.
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由 Fabio Estevam 提交于
The rtc isl1208 driver is used by mx6 nitrogen board, so let's enable it by default. The fsl sai driver is used by the vf610-twr board, so let's enable it by default. simple-audio-card driver is used by the vf610-twr board, so let's enable it by default. Generated this patch by doing: - make imx_v6_v7_defconfig - make menuconfig and manually select options - make savedefconfig - cp defconfig arch/arm/configs/imx_v6_v7_defconfig ,which results in some additional cleanups. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Fabio Estevam 提交于
The imx weim driver is used by some mx27/mx1 boards, so let's enable it by default. Generated this patch by doing: - make imx_v4_v5_defconfig - make menuconfig and manually select CONFIG_IMX_WEIM - make savedefconfig - cp defconfig arch/arm/configs/imx_v4_v5_defconfig ,which results in some additional cleanups. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Joe Perches 提交于
Use the more common pr_warn. Signed-off-by: NJoe Perches <joe@perches.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Anson Huang 提交于
On i.MX6Q TO > 1.0, i.MX6DL and i.MX6SX, gpt per clock can be from OSC instead of ipg_per, as ipg_per's rate may be scaled when system enter low bus mode, to keep system timer NOT drift, better to make gpt per clock at fixed rate, here add support for gpt per clock to be from OSC which is at fixed rate always. There are some difference on this implementation of gpt per clock source, see below for details: i.MX6Q TO > 1.0: GPT_CR_CLKSRC, b'101 selects fix clock of OSC / 8 for gpt per clk; i.MX6DL and i.MX6SX: GPT_CR_CLKSRC, b'101 selects OSC for gpt per clk, and we must enable GPT_CR_24MEM to enable OSC clk source for gpt per, GPT_PR_PRESCALER24M is for pre-scaling of this OSC clk, here set it to 8 to make gpt per clk is 3MHz; i.MX6SL: ipg_per can be from OSC directly, so no need to implement this new clk source for gpt per. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Anson Huang 提交于
Add gpt_3m clock for i.mx6qdl, as gpt can source clock from OSC, some i.MX6 series SOCs has fixed divider of 8 for gpt clock, so here add a fix clk of gpt_3m. i.MX6Q TO1.0 has no gpt_3m option, so force it to be from ipg_per. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
There is a copy&paste error on register offset of pll7_usb_host gate clock introduced by i.MX6 PLL bypass support patches. The error breaks the ENET function, because it overwrites the pll6_enet gate bit. Correct the offset for all i.MX6 clock drivers. Thanks to Fugang Duan <B38611@freescale.com> for spotting the error. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shengjiu Wang 提交于
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
Since ENABLE and BYPASS bits of PLLs are now implemented as separate gate and mux clocks by clock drivers, the code handling these two bits can be removed from clk-pllv3 driver. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
This is the same change for imx6sx clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sx. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
This is the same change for imx6sl clock driver as "ARM: imx6q: add BYPASS support for PLL clocks" for imx6q. The difference is that only anaclk1 is available on imx6sl. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
The imx6q clock driver currently hard-codes all PLL clocks to source from OSC24M without BYPASS support. The patch adds the missing lvds_in clock which is mutually exclusive with lvds_gate, and implements BYPASS and BYPASS_CLK_SRC selection for PLL clocks as per Figure 10-3. Primary Clock Generation in IMX6DQRM, i.e. both BYPASS_CLK_SRC and BYPASS bits are implemented as mux clocks, and ENABLE bit of PLL clocks is implemented as a gate clock after BYPASS mux. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shawn Guo 提交于
There are a couple of gate clocks are mutually exclusive on i.MX6, i.e. LVDSCLK1_IBEN and LVDSCLK1_OBEN. They cannot be enabled simultaneously. This patches adds an exclusive gate clock type specifically for such case. The clock driver will need to call imx_clk_gate_exclusive() to register a gate clock with parameter exclusive_mask indicating the mask of gate bits which are mutually exclusive to this gate clock. Right now, it only handles the exclusive gate clocks which are defined in a single hardware register, which is the case we're running into today. But it can be extended to handle exclusive gate clocks defined in different registers later if needed. Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shengjiu Wang 提交于
Each SSI has "ssi", "ssi_ipg" clocks, and they share same gate bits. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shengjiu Wang 提交于
ASRC has "asrc", "asrc_ipg", "asrc_mem" clocks, and they share the same gate bits. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Fancy Fang 提交于
The parent clocks of IMX6SL_CLK_PXP_AXI_SEL and IMX6SL_CLK_EPDC_AXI_SEL clocks are not the same. So split the epdc_pxp_sels into two different clock selections 'pxp_axi_sels' and 'epdc_axi_sels'. Signed-off-by: NFancy Fang <chen.fang@freescale.com> Signed-off-by: NRobby Cai <R63905@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Shengjiu Wang 提交于
There are three clock for ESAI, esai_extal, esai_ipg, esai_mem. Rename 'esai' to 'esai_extal', 'esai_ahb' to 'esai_mem', and add 'esai_ipg'. Make the clock for ESAI more clear and align them with imx6sx. Signed-off-by: NShengjiu Wang <shengjiu.wang@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Fabio Estevam 提交于
PLL5 is well suited for being the parent of IMX6SL_CLK_LCDIF_PIX_SEL and PLL2_PFD for IMX6SL_CLK_LCDIF_AXI_SEL. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Fabio Estevam 提交于
Currently csi_lcdif_sels[] is a shared array for the providing the possible clock parents for csi and lcdif blocks. This is not correct, as csi and lcdif do not share the same clock parents. Introduce csi_sels[] for the csi and lcdif_axi_sels[] for the lcdif clocks in order to describe the parents correctly. Signed-off-by: NFabio Estevam <fabio.estevam@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Stefan Agner 提交于
This commit adds PLL7 which is required for USBPHY1. It also adds the USB PHY and USB Controller clocks and the gates to enable them. Acked-by: NJingchang Lu <jingchang.lu@freescale.com> Signed-off-by: NStefan Agner <stefan@agner.ch> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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由 Anson Huang 提交于
Add cpufreq support for i.MX6SX, using common i.MX6Q cpufreq driver. Signed-off-by: NAnson Huang <b20788@freescale.com> Signed-off-by: NShawn Guo <shawn.guo@freescale.com>
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