1. 21 9月, 2006 1 次提交
  2. 18 9月, 2006 1 次提交
  3. 29 6月, 2006 1 次提交
    • R
      [ARM] nommu: adjust headers for !MMU ARM systems · 002547b4
      Russell King 提交于
      Majorily based on Hyok Choi's patches, this fixes up the asm-arm
      header files for mmuless systems.  Over and above Hyok's patches:
      
      - nommu.h merged into mmu.h (it's only a structure)
      - nommu_context.h is essentially the same as mmu_context.h, but
        without the MM switching code.
      
      so there's no point having separate files.  Also, in memory.h,
      there's no point #ifndef'ing PHYS_OFFSET and END_MEM - both
      CONFIG_DRAM_BASE and CONFIG_DRAM_SIZE will always be set by the
      configuration scripts.
      
      Other files have minor formatting changes, but are essentially
      the same.  Hyok's original patches were signed off thusly:
      Signed-off-by: NHyok S. Choi <hyok.choi@samsung.com>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      002547b4
  4. 26 4月, 2006 1 次提交
  5. 29 3月, 2006 1 次提交
    • L
      [ARM] 3377/2: add support for intel xsc3 core · 23bdf86a
      Lennert Buytenhek 提交于
      Patch from Lennert Buytenhek
      
      This patch adds support for the new XScale v3 core.  This is an
      ARMv5 ISA core with the following additions:
      
      - L2 cache
      - I/O coherency support (on select chipsets)
      - Low-Locality Reference cache attributes (replaces mini-cache)
      - Supersections (v6 compatible)
      - 36-bit addressing (v6 compatible)
      - Single instruction cache line clean/invalidate
      - LRU cache replacement (vs round-robin)
      
      I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
      cores have separate errata and have to handle things like L2, so it
      is simpler to keep it separate.
      
      L2 cache support is currently a build option because the L2 enable
      bit must be set before we enable the MMU and there is no easy way to
      capture command line parameters at this point.
      
      There are still optimizations that can be done such as using LLR for
      copypage (in theory using the exisiting mini-cache code) but those
      can be addressed down the road.
      Signed-off-by: NDeepak Saxena <dsaxena@plexity.net>
      Signed-off-by: NLennert Buytenhek <buytenh@wantstofly.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      23bdf86a
  6. 15 1月, 2006 1 次提交
    • N
      [ARM] 3101/1: ARM EABI: slab memory must be 64-bit aligned · da2b1cd6
      Nicolas Pitre 提交于
      Patch from Nicolas Pitre
      
      Although ARM is still using 32-bit pointers, version 5 and later
      versions of the ARM architecture introduced the ldrd and strd
      instructions to move 64-bit data which must be 64-bit aligned in memory,
      and the EABI includes new constraints on structure data alignment to
      allow for the compiler to use those instructions. This means that any
      slab allocation must start on a 64-bit boundary which is not equivalent
      to BYTES_PER_WORD, especially on those architecture versions that
      implements the ldrd/strd instructions.
      
      Overriding the default alignment disables some slab debug features. If
      those debug features are really needed then the kernel will have to be
      compiled for version 4 of the ARM architecture.
      Signed-off-by: NNicolas Pitre <nico@cam.org>
      Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk>
      da2b1cd6
  7. 05 9月, 2005 1 次提交
  8. 10 5月, 2005 2 次提交
  9. 17 4月, 2005 1 次提交
    • L
      Linux-2.6.12-rc2 · 1da177e4
      Linus Torvalds 提交于
      Initial git repository build. I'm not bothering with the full history,
      even though we have it. We can create a separate "historical" git
      archive of that later if we want to, and in the meantime it's about
      3.2GB when imported into git - space that would just make the early
      git days unnecessarily complicated, when we don't have a lot of good
      infrastructure for it.
      
      Let it rip!
      1da177e4