Ths patch allows runtime PM for sdhci-pci, runtime suspending after
inactivity of 50ms and ensuring runtime resume before SDHC registers
are accessed.  During runtime suspend, interrupts are masked.
The host controller state is restored at runtime resume.

For Medfield, the host controller's card detect mechanism is
supplanted by an always-on GPIO which provides for card detect wake-up.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

We are cleaning up the implicit presence of module.h; these guys are
some of the people who just assume it will be there.  Call it out
explitly for those that really need it.
Signed-off-by: NPaul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Since commit [e58aa3d2: genirq: Run irq handlers with interrupts
disabled], we run all interrupt handlers with interrupts disabled
and we even check and yell when an interrupt handler returns with
interrupts enabled (see commit [b738a50a: genirq: Warn when handler
enables interrupts]).

So now this flag is a NOOP and can be removed.
Signed-off-by: NYong Zhang <yong.zhang0@gmail.com>
Acked-by: NKishore Kadiyala <kishore.kadiyala@ti.com>
Acked-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Intel Medfield platform blocks access to eMMC boot partitions which
results in switch errors.  Since there is no access, mmcboot0/1
devices should not be created.  Add a host capability to reflect that.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

This patch adds the basic support for imx6q usdhc, which is a
derivative of esdhc controller.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Provide platforms with a simplified way to specify MMCIF DMA slave IDs in
a way, similar to SDHI and other sh_dma clients.
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Implement eMMC hardware reset for Medfield.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Add an SDHCI operation for hardware reset and connect it to the
host controller operation.
Signed-off-by: NAdrian Hunter <adrian.hunter@intel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

The error condition indicates that mmci_post_request() should cleanup
after the mmci_pre_request(). In this case the resources allocated by
device_prep_slave_sg() are freed by calling dmaengine_terminate_all().
dma_unmap_sg() should always be performed if the host_cookie is set.
Signed-off-by: NPer Forlin <per.forlin@linaro.org>
Acked-by: NLinus Walleij <linus.walleij@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NTanmay Upadhyay <tanmay.upadhyay@einfochips.com>
Acked-by: NZhangfei Gao <zhangfei.gao@marvell.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Currently if card_power_gpio is passed from platform data, it is acquired
and its value is either set or reset. After that we overwrite it with 1,
which is not required.

So, this patch removes the extra line which sets its value.
Signed-off-by: NViresh Kumar <viresh.kumar@st.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Freescale eSDHC registers only support 32-bit accesses, this patch
ensures that all Freescale eSDHC register accesses are 32-bit.
Signed-off-by: NXu lei <B33228@freescale.com>
Signed-off-by: NRoy Zang <tie-fei.zang@freescale.com>
Signed-off-by: NKumar Gala <galak@kernel.crashing.org>
Acked-by: NAnton Vorontsov <cbouatmailru@gmail.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

The default controller configuration which was previously setup by
platform helper functions is moved into the driver.

Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: NThomas Abraham <thomas.abraham@linaro.org>
Acked-by: NKukjin Kim <kgene.kim@samsung.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

The previous patch which implemented a DT binding for sdhci-tegra did not
allow all platform data fields to be initialized from DT. The following
were missing:

is_8bit: Implemented by this patch.

pm_flags: Not implemented yet. There are no mainline users of this field.
  I'm not quite sure what it's for, and hence how to represent this
  in DT; the value ends up being assigned to host->mmc->pm_caps.

While we're at it, fix the binding documentation to refer to "SD/MMC"
instead of "eSDHC", since that's the correct name; "eSDHC" was cut/paste
from the Freescale binding docs.
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

The Patch adds the support for SDIO interrupts for all slots.
It includes enabling of SDIO interrupts through dw_mci_enable_sdio_irq
and the handling of the slot specific interrupts in the Interrupt Service
Routine.
Signed-off-by: NShashidhar Hiremath <shashidharh@vayavyalabs.com>
Acked-by: NJames Hogan <james.hogan@imgtec.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

If DMA resource is not available then SDCC driver
should atleast work in PIO data transfer mode.
Signed-off-by: NSubhash Jadavani <subhashj@codeaurora.org>
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Intialize busclk_timer before it is accessed in probe.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Not all targets have IRQ1 line routed from the SD controller to
the processor. So we cannot rely on IRQ1 for PIO interrupts.
This patch moves all PIO interrupts to IRQ0 and enables the PIO
mode.
Signed-off-by: NMurali Palnati <palnatim@codeaurora.org>
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

On some targets, MCI_IRQ_MASK1 is not routed to the MSM in which
case only "cmd_irq" must be used even for PIO. With this change,
all the targets will use only "cmd_irq" for both CMD and PIO.
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

For clocks that support rates which can be set (most clocks other
than _pclk AHB clocks), a rate must be set using clk_set_rate()
before the clock is enabled for the first time with clk_enable().
Subsequent calls to clk_enable() need not be preceded with the
clk_set_rate() calls unless we wish to change the clock rate that
is set previously.

SDC host->clk is currently enabled without setting the clock rate
even once. This patch fixes this, by ensuring that the clock rate
for this clock is first set before enabling the clock.
Signed-off-by: NMurali Palnati <palnatim@codeaurora.org>
Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

This allows boards with non-standard sdio cards to fill the CIS/CCCR data.
It is particularly important for old msm72k boards using wl1251.
Also drop the obsolete embedded_sdio_data structure from the header
as it was intended to surve a similiar purpose but was not implemented.
Signed-off-by: NAlexander Tarasikov <alexander.tarasikov@gmail.com>
Acked-by: NSahitya Tummala <stummala@codeaurora.org>
[davidb: minor formatting cleanup]
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

The use of && instead of || caused a NULL pointer dereference if
gpio setup was not passed via platform data
Signed-off-by: NAlexander Tarasikov <alexander.tarasikov@gmail.com>
Acked-by: NSahitya Tummala <stummala@codeaurora.org>
Signed-off-by: NDavid Brown <davidb@codeaurora.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Allow named IRQs to use corresponding specific handlers. If named IRQs are
used, at least an "sdcard" IRQ has to be specified by the platform. If
names are not used, an arbitrary number of IRQs can be provided by the
platform, in which case the generic ISR will be used for each of them.

Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms@verge.net.au>
[g.liakhovetski@gmx.de: style and typo corrections, platform data check]
Signed-off-by: NGuennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Provide separate interrupt handlers which may be used by platforms where
SDHI has three interrupt sources.

This patch also removes the commented-out handling of CRC and other errors.

Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms@verge.net.au>
Signed-off-by: NChris Ball <cjb@laptop.org>

This avoids the need to look up the masks each time an interrupt is handled.
As suggested by Guennadi.

Cc: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms@verge.net.au>
Signed-off-by: NChris Ball <cjb@laptop.org>

The individual SoC dependency in Kconfig hardly scales anymore.
Instead of having such a fine grained dependency just depend
on ARCH_MXC and risk that the uninformed user has to look in
the help text to figure out which driver is the correct one.
Signed-off-by: NSascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: NChris Ball <cjb@laptop.org>

Add hooks to read gpio configuration out of the device tree node.

[grant.likely: Rewrite of original patch from John Bonesio]
Signed-off-by: NGrant Likely <grant.likely@secretlab.ca>
[swarren: Fixed tegra_sdhci_get_ro() to retrieve pdata correctly]
[swarren: Reworked to avoid #ifdef CONFIG_OF]
[swarren: Reworked binding based on fsl-imx-esdhc.txt]
[swarren: Documented binding]
Signed-off-by: NStephen Warren <swarren@nvidia.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Eanble the ADMA2 mode for freescale esdhc imx driver, tested on MX25
3DS board, MX51 BBG board and MX53 LOCO board.

This patch is only used to enable the ADMA2 for MX51/53 platforms.
MX25/35 can't support the ADMA2 mode, set BROKEN_ADMA quirk on
MX25/35 platforms.

The ADMA mode supported or not can be distinguished by bit 20 of
the Capability Register (offset 0x40) in the FSL eSDHC module.
Signed-off-by: NRichard Zhu <richard.zhu@linaro.org>
Tested-and-acked-by: NEric Miao <eric.miao@linaro.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

Remove the use of irq_to_gpio() in the card detection interrupt
handler. The information is available in the board structure and
we can avoid using a function that has little meaning.
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: NJean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

This patch fixes a potential issue about PDC interrupts. For example we
have a ENDRX pending interrupt and a RXBUFF pending interrupt. We have
received the RXBUFF interrupt but the transfer is not finished (so we
didn't have time to give a new buffer to the PDC controller). Then we
will compute ENDRX interrupt and we will give a new buffer to the PDC
controller, just after we will compute the RXBUFF interrupt and give
one or two new buffers to the PDC controller but we are not sure that
the first buffer given has been filled. So in this situation we may
have "lost" one sg buffer. It's the same for transmission.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Assuming that a sg buffer size is a page size is false so use sg_dma_len.
A 4096 bytes can be required with two 2048-bytes sg buffer.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Rename atmci_start_command() to atmci_send_command() which is more
appropriate; atmci_start_command suggests we're sending a start command.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Add pdc support for atmel-mci. It makes at91-mci driver useless because it
was only used for the old atmel MCI core which has pdc but no dma support.
To allow removing at91-mci, the capabilities of the MCI core are detected
at runtime -- then the driver will use pio, pdc or dma transfers.
Warning: at91rm9200 is not supported, to support it we need to use swab32
on data but I have no board to test it.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Change atmci_readl and atmci_writel macros: remove string concatenation.
We can use these macros with registers which are not prefixed by ATMCI_.
This is the case if we want to write PDC registers which are common to
several devices so they are not prefixed with ATMCI_.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

Homogenize namespace to atmci.
Signed-off-by: NLudovic Desroches <ludovic.desroches@atmel.com>
Signed-off-by: NNicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: NChris Ball <cjb@laptop.org>

This patch fixes the problem in sdhci-s3c host driver for Samsung Soc's.
During the card identification stage the mmc core driver enumerates for
the best bus width in combination with the highest available data rate.
It starts enumerating from the highest bus width (8) to lowest width (1).

In case of few MMC cards the 4-bit bus enumeration fails and tries
the 1-bit bus enumeration. When switched to 1-bit bus mode the host driver
has to clear the previous bus width setting and apply the new setting.

The current patch will clear the previous bus mode and apply the new
mode setting.
Signed-off-by: NGirish K S <girish.shivananjappa@linaro.org>
Acked-by: NJaehoon Chung <jh80.chung@samsung.com>
Cc: <stable@kernel.org>
Signed-off-by: NChris Ball <cjb@laptop.org>

This corrects a logic error that I introduced in
"mmc: sdhi: Add write16_hook"
Reported-by: NMagnus Damm <magnus.damm@gmail.com>
Signed-off-by: NSimon Horman <horms@verge.net.au>
Signed-off-by: NChris Ball <cjb@laptop.org>