- 31 7月, 2013 1 次提交
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由 Chris Metcalf 提交于
The "inv" (invalidate) instruction is generally less safe than "finv" (flush and invalidate), as it will drop dirty data from the cache. It turns out we have almost no need for "inv" (other than for the older 32-bit architecture in some limited cases), so convert to "finv" where possible and delete the extra "inv" infrastructure. Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
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- 29 3月, 2012 1 次提交
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由 David Howells 提交于
Disintegrate asm/system.h for Tile. Signed-off-by: NDavid Howells <dhowells@redhat.com> Acked-by: NChris Metcalf <cmetcalf@tilera.com>
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- 05 5月, 2011 1 次提交
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由 Chris Metcalf 提交于
They are only applicable for locally-homecached memory ranges, so change their names to {flush,finv}_buffer_local(). Change inv_buffer() to just do an mf instead of any kind of fancier barrier, since you're obviously not going to be waiting for anything once the local homecache is invalidated. Fix tilepro.c network driver not to bother calling finv_buffer when stopping the EPP, but just mf after memset to ensure that it will not see any packet data after we finish stopping; use finv_buffer_remote() when doing exit-time cleanup. This also fixes a (not very interesting) generic Linux build failure where drivers/scsi/st.c declares its own flush_buffer(). Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
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- 02 3月, 2011 1 次提交
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由 Chris Metcalf 提交于
It now takes an additional argument so it can be used to flush-and-invalidate pages that are cached using hash-for-home as well those that are cached with coherence point on a single cpu. This allows it to be used more widely for changing the coherence point of arbitrary pages when necessary. Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
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- 25 11月, 2010 1 次提交
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由 Chris Metcalf 提交于
This change adds the first network driver for the tile architecture, supporting the on-chip XGBE and GBE shims. The infrastructure is present for the TILE-Gx networking drivers (another three source files in the new directory) but for now the the actual tilegx sources are waiting on releasing hardware to initial customers. Note that arch/tile/include/hv/* are "upstream" headers from the Tilera hypervisor and will probably benefit less from LKML review. Signed-off-by: NChris Metcalf <cmetcalf@tilera.com>
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- 07 7月, 2010 1 次提交
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由 Chris Metcalf 提交于
This code is used in other places in our system than in Linux, so to share it we now implement it as an inline function in our low-level <arch> headers, and instantiate it in one file in Linux's arch/tile/lib. The file is now cacheflush.c and is C code rather than the strangely-named and assembler-implemented __invalidate_icache.S. Signed-off-by: NChris Metcalf <cmetcalf@tilera.com> Acked-by: NArnd Bergmann <arnd@arndb.de>
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- 05 6月, 2010 1 次提交
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由 Chris Metcalf 提交于
This change is the core kernel support for TILEPro and TILE64 chips. No driver support (except the console driver) is included yet. This includes the relevant Linux headers in asm/; the low-level low-level "Tile architecture" headers in arch/, which are shared with the hypervisor, etc., and are build-system agnostic; and the relevant hypervisor headers in hv/. Signed-off-by: NChris Metcalf <cmetcalf@tilera.com> Acked-by: NArnd Bergmann <arnd@arndb.de> Acked-by: NFUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Reviewed-by: NPaul Mundt <lethal@linux-sh.org>
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