1. 08 5月, 2010 7 次提交
  2. 07 5月, 2010 23 次提交
  3. 06 5月, 2010 10 次提交
    • L
      Merge branch 'for-linus' of git://git.monstr.eu/linux-2.6-microblaze · e8e8fade
      Linus Torvalds 提交于
      * 'for-linus' of git://git.monstr.eu/linux-2.6-microblaze:
        microblaze: Defconfig update
        microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros
        microblaze: Fix consistent-sync code
        microblaze: Define correct L1_CACHE_SHIFT value
        microblaze: cpuinfo shows cache line length
        microblaze: Fix kmalloc alignment on non-coherent DMA platforms
        microblaze: Fix typo fault in cache code
        microblaze: Fix consistent code
        microblaze: pci-dma: use include/linux/dma-mapping.h
        microblaze: page.h: Remove get_user_page and free_user_page
        microblaze: Remove "cache" optimized copy_page function
        microblaze: invoke oom-killer from page fault
        microblaze: fix divide by zero exception message
        microblaze: Add isa_dma_bridge_buggy to dma.h
        microblaze: Remove ancient code
        microblaze: Quiet section mismatch warnings for MMU version
        microblaze: Quiet section mismatch warnings
        microblaze: Fix IRQ entry/exit ftracing
        microblaze: resource/PCI: align functions now return start of resource
        microblaze: PCI: add pci_bus_for_each_resource(), remove direct bus->resource[] refs
      e8e8fade
    • L
      Merge master.kernel.org:/home/rmk/linux-2.6-arm · 325ce9e3
      Linus Torvalds 提交于
      * master.kernel.org:/home/rmk/linux-2.6-arm:
        [ARM] pxa/colibri: fix missing #include <mach/mfp.h> in colibri.h
        [ARM] pxa/spitz: fix On/off key name to fix warning during boot
        [ARM] pxa: fix the incorrect cpu_is_pxa950()
        [ARM] pxa: update cpuid pattern for pxa9xx in head.S
        [ARM] pxa/viper: fix timeout usage for I2C
        [ARM] pxa/raumfeld: fix button name
        [ARM] pxa/imote2: Fix iMote2 defconfig
        [ARM] pxa: add missing new line to regs-u2d.h
        ARM: 6093/1: Fix kernel memory printing for sparsemem
        arch/arm/include/asm/elf.h: forward-declare the task-struct
        arch/arm/plat-pxa/dma.c: correct NULL test
        ARM: 6076/1: SA1100: add processor check to sa1110-cpufreq driver
        ARM: 6075/1: SA1100: fix wrong CPU type for h3100 and h3600
        ARM: Update mach-types
        ARM: 6066/1: Fix "BUG: scheduling while atomic: swapper/0/0x00000002
        ARM: 6068/1: Fix build break with KPROBES enabled
        mx5: Fix build error for mx51_defconfig
      325ce9e3
    • L
      Merge branch 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6 · bbfdbe9d
      Linus Torvalds 提交于
      * 'sh/for-2.6.34' of git://git.kernel.org/pub/scm/linux/kernel/git/lethal/sh-2.6:
        sh: fix a number of Oopses and leaks in SH framebuffer driver
        SH: fix error paths in DMA driver
        sh: sh7751 pci controller io port fix
        sh: Fix maximum number of SCIF ports in R2D defconfigs
        SH: fix TS field shift calculation for DMA drivers
      bbfdbe9d
    • M
      microblaze: Defconfig update · 65134121
      Michal Simek 提交于
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      65134121
    • M
      microblaze: Optimize CACHE_LOOP_LIMITS and CACHE_RANGE_LOOP macros · 3274c570
      Michal Simek 提交于
      1. Remove CACHE_ALL_LOOP2 macro because it is identical to CACHE_ALL_LOOP
      2. Change BUG_ON to WARN_ON
      3. Remove end aligned from CACHE_LOOP_LIMITS.
      C implementation do not need aligned end address and ASM code do aligned
      in their macros
      4. ASM optimized  CACHE_RANGE_LOOP_1/2 macros needs to get aligned end address.
      Because end address is compound from start + size, end address is the first address
      which is exclude.
      
      Here is the corresponding code which describe it.
      +       int align = ~(line_length - 1);
      +       end = ((end & align) == end) ? end - line_length : end & align;
      
      a) end is aligned:
      it is necessary to subtruct line length because we don't want to work with
      next cacheline
      b) end address is not aligned:
      Just align it to be ready for ASM code.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      3274c570
    • M
      microblaze: Fix consistent-sync code · 385e1efa
      Michal Simek 提交于
      PCI_DMA_FROMDEVICE should call invalidation not flushing.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      385e1efa
    • M
      microblaze: Define correct L1_CACHE_SHIFT value · 598acab4
      Michal Simek 提交于
      Microblaze cacheline length is configurable and current cpu
      uses two cacheline length 4 and 8.
      
      We are taking conservative maximum value to be sure that cacheline
      alignment is satisfied for all cases.
      
      Here is the calculation for cacheline lenght 8  32bit=4Byte values
      which is corresponding with SHIFT 5.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      598acab4
    • M
      microblaze: cpuinfo shows cache line length · 77543ceb
      Michal Simek 提交于
      Show cache line length in /proc/cpuinfo.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      77543ceb
    • M
      microblaze: Fix kmalloc alignment on non-coherent DMA platforms · de925d9d
      Michal Simek 提交于
      Based on PowerPC patche 52142e75
      
      PowerPC description:
      On platforms doing non-coherent DMA (4xx, 8xx, ...), it's important
      that the kmalloc minimum alignment is set to the cache line size, to
      avoid sharing cache lines between different objects, so that DMA to
      one of the objects doesn't corrupt the other.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      de925d9d
    • M
      microblaze: Fix typo fault in cache code · c17e1a1c
      Michal Simek 提交于
      Copy & paste error.
      Signed-off-by: NMichal Simek <monstr@monstr.eu>
      c17e1a1c