- 08 10月, 2018 40 次提交
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由 Chaotian Jing 提交于
when gate MSDC0_HCLK, access register will hang, even the MSDC driver will never accessing register after HCLK was gated, but for safety, need gate the bus_clk(which used to access register) too. Signed-off-by: NChaotian Jing <chaotian.jing@mediatek.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Anand Moon 提交于
Add tuning for sdr and ddr timing for USH-I mode sdr104/sdr50/ddr50 for host controller. Cc: Jaehoon Chung <jh80.chung@samsung.com> Cc: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: NAnand Moon <linux.amoon@gmail.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Gustavo A. R. Silva 提交于
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Notice that in this particular case, I replaced the "fall-through:" comment with a proper "fall through", which is what GCC is expecting to find. Addresses-Coverity-ID: 1373880 ("Missing break in switch") Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Gustavo A. R. Silva 提交于
In preparation to enabling -Wimplicit-fallthrough, mark switch cases where we are expecting to fall through. Notice that in this particular case, I replaced the "deliberate fall-through" comment with a proper "fall through" at the bottom of the case, which is what GCC is expecting to find. Addresses-Coverity-ID: 1373887 ("Missing break in switch") Signed-off-by: NGustavo A. R. Silva <gustavo@embeddedor.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ludovic Barre 提交于
Recent versions of checkpatch have a new warning based on a documented preference of Linus to not use bool in structures due to wasted space and the size of bool is implementation dependent. For more information, see the email thread at https://lkml.org/lkml/2017/11/21/384 fix checkpatch --strict issues: -CHECK: Avoid using bool structure members because of possible alignment issues - see: https://lkml.org/lkml/2017/11/21/384 -WARNING: Avoid using bool as bitfield. Prefer bool bitfields as unsigned int or u<8|16|32> Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ludovic Barre 提交于
This patch internalizes the dma_inprogress into mmci dma interfaces. This allows to simplify and prepare the next dma callbacks for mmci host ops. dma_inprogress is called in mmci_dma_data_error and mmci_dma_finalize. Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Ludovic Barre 提交于
This patch internalizes the management of dma map/unmap into mmci dma interfaces. This allows to simplify and prepare the next dma callbacks for mmci host ops. mmci_dma_unmap was called in mmci_data_irq & mmci_cmd_irq functions and can be integrated in mmci_dma_data_error. Signed-off-by: NLudovic Barre <ludovic.barre@st.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Yu Zhao 提交于
This device reports SDHCI_CLOCK_INT_STABLE even though it's not ready to take SDHCI_CLOCK_CARD_EN. The symptom is that reading SDHCI_CLOCK_CONTROL after enabling the clock shows absence of the bit from the register (e.g. expecting 0x0000fa07 = 0x0000fa03 | SDHCI_CLOCK_CARD_EN but only observed the first operand). mmc1: Timeout waiting for hardware cmd interrupt. mmc1: sdhci: ============ SDHCI REGISTER DUMP =========== mmc1: sdhci: Sys addr: 0x00000000 | Version: 0x00000603 mmc1: sdhci: Blk size: 0x00000000 | Blk cnt: 0x00000000 mmc1: sdhci: Argument: 0x00000000 | Trn mode: 0x00000000 mmc1: sdhci: Present: 0x01ff0001 | Host ctl: 0x00000001 mmc1: sdhci: Power: 0x0000000f | Blk gap: 0x00000000 mmc1: sdhci: Wake-up: 0x00000000 | Clock: 0x0000fa03 mmc1: sdhci: Timeout: 0x00000000 | Int stat: 0x00000000 mmc1: sdhci: Int enab: 0x00ff0083 | Sig enab: 0x00ff0083 mmc1: sdhci: AC12 err: 0x00000000 | Slot int: 0x00000000 mmc1: sdhci: Caps: 0x25fcc8bf | Caps_1: 0x00002077 mmc1: sdhci: Cmd: 0x00000000 | Max curr: 0x005800c8 mmc1: sdhci: Resp[0]: 0x00000000 | Resp[1]: 0x00000000 mmc1: sdhci: Resp[2]: 0x00000000 | Resp[3]: 0x00000000 mmc1: sdhci: Host ctl2: 0x00000008 mmc1: sdhci: ADMA Err: 0x00000000 | ADMA Ptr: 0x00000000 mmc1: sdhci: ============================================ The problem happens during wakeup from S3. Adding a delay quirk after power up reliably fixes the problem. Signed-off-by: NYu Zhao <yuzhao@google.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
The OMAP HSMMC driver has some elaborate and hairy handling for passing GPIO card detect and write protect lines from a boardfile into the driver: the machine defines a struct omap2_hsmmc_info that is copied into struct omap_hsmmc_platform_data by omap_hsmmc_pdata_init() in arch/arm/mach-omap2/hsmmc.c. However the .gpio_cd and .gpio_wp fields are not copied from omap2_hsmmc_info to omap_hsmmc_platform_data by omap_hsmmc_pdata_init() so they remain unused. The only platform defining omap2_hsmmc_info also define both to -1, unused. It turn out there are no boardfiles passing any valid GPIO lines into the OMAP HSMMC driver at all. And since we are not going to add any more OMAP2 boardfiles, we can delete this card detect and write protect handling altogether. This seems to also fix a bug: the card detect callback mmc_gpio_get_cd() in the slot GPIO core needs to be called by drivers utilizing slot GPIO. It appears the the boardfile quirks were not doing this right, so this would only get called for boardfiles, i.e. since no boardfile was using it, never. Just assign mmc_gpio_get_cd() unconditionally to omap_hsmmc_ops .get_cd() so card detects from the device tree works. AFAICT card detect with GPIO lines assigned from mmc_of_parse() are not working at the moment, but that is no regression since it probably never worked. Cc: Tony Lindgren <tony@atomide.com> Cc: linux-omap@vger.kernel.org Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
Cover detection appears to be a feature protecting the SD card on mobile phones with a slide-cover, such as some Nokia phones. The idea seems to be to not allow access to the SD card when the cover is open. It is only usable with platform data from board files, but no board file in the kernel is using it, yet it takes up a sizeable chunk of code in the OMAP HSMMC driver. Since we do not add new board files for the OMAPs any target that need this should anyway reimplement it properly using the device tree, so delete this legacy code. The driver is marked as orphan in MAINTAINERS by the way. Cc: Tony Lindgren <tony@atomide.com> Cc: linux-omap@vger.kernel.org Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Acked-by: NTony Lindgren <tony@atomide.com> Acked-by: NKishon Vijay Abraham I <kishon@ti.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Lubomir Rintel 提交于
The sd8686 "libertas" SDIO adapter's power is controlled with WLAN_RST and WLAN_PD pins -- pretty much the same way as sd8787. Allow building the power sequencing driver along with the libertas Wi-Fi driver. Signed-off-by: NLubomir Rintel <lkundrak@v3.sk> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
This driver is complicating things for no reason: the "cd" GPIO can easily be retrieved from the device tree if present using just mmc_gpiod_request_cd(), which will fetch the descriptor from the device tree using the standard binding just fine. If the retrieveal is successful, we also request the IRQ. As a result the private subdriver data can be removed entirely. Cc: Weijun Yang <york.yang@csr.com> Cc: Barry Song <baohua@kernel.org> Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
The platform data for the PXAv3 driver allows passing a card detect GPIO, but this code is not used in the kernel. In order to not encourage the use of the old global GPIO numberspace we need to remove this. Card detect (and write protect) GPIO can easily be added into the driver using machine descriptor tables instead, and the descriptor-based (gpiod) variants of the slot GPIO APIs. Cc: Jisheng Zhang <jszhang@marvell.com> Cc: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Reviewed-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
This driver is complicating things for no reason: the "cd" GPIO can easily be retrieved from the device tree if present using just mmc_gpiod_request_cd(), which will fetch the descriptor from the device tree using the standard binding just fine. Cc: Viresh Kumar <vireshk@kernel.org> Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Linus Walleij 提交于
All the machines using the MMCI are passing GPIOs for the card detect and write protect using the device tree or descriptor table (one single case, Integrator/AP IM-PD1). Drop support for passing global GPIO numbers through platform data, noone is using it. Signed-off-by: NLinus Walleij <linus.walleij@linaro.org> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Jisheng Zhang 提交于
If hosts provides ops->adma_write_desc, we should not fall back to the general sdhci_adma_write_desc(). Signed-off-by: NJisheng Zhang <Jisheng.Zhang@synaptics.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 jun qian 提交于
As you are already in ISR, it is unnecessary to call spin_lock_irqsave. Signed-off-by: Njun qian <hangdianqj@163.com> Reviewed-by: NVladimir Zapolskiy <vz@mleia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Niklas Söderlund 提交于
Fix warning when running with CONFIG_DMA_API_DEBUG_SG=y by allocating a device_dma_parameters structure and filling in the max segment size. The size used is the result of a discussion with Renesas hardware engineers and unfortunately not found in the datasheet. renesas_sdhi_internal_dmac ee140000.sd: DMA-API: mapping sg segment longer than device claims to support [len=126976] [max=65536] Reported-by: NGeert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: NNiklas Söderlund <niklas.soderlund+renesas@ragnatech.se> [wsa: simplified some logic after validating intended dma_parms life cycle and added comment] Signed-off-by: NWolfram Sang <wsa+renesas@sang-engineering.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
The eMMC controller is also a new timing mode controller, but it doesn't have the timing mode switch. It does however have signal delay and calibration controls, typical of Allwinner MMC controllers that support the new timing mode. Enable the new timing mode setting for the A64 eMMC controller. This also enables MMC HS-DDR modes, which gives higher throughput for eMMC chips that support it, and can deliver such throughput. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chen-Yu Tsai 提交于
Newer sunxi mmc controller variants support what they call the "new timing mode". Support for this was implemented in two ways, according to the hardware that was seen at the time. The first type retained the old timing mode, and both the clock and mmc controllers had switches to select which mode was used. Both switches had to be set to the same setting. This variant was denoted with the .has_timings_switch field in the sunxi_mmc_cfg structure. This hardware is only seen on the A83T. The second type did away with the old timing mode. The clock controller no longer had the mode selection or clock delay setting bits. In some cases the mmc controller retained its mode selection bit, but this always needed to be set to the new mode, or instabilities would occur. In a few cases, such as the A64 and H6 eMMC controller, the mode selection bit is gone, but the controller still behaves like the new timing mode, requiring the module clock to be double the card clock in DDR transfer modes. This variant is denoted with the .needs_new_timings field. This patch adds more comments explaining the two fields, as well as the possibly nonexistent mode switch in the mmc controller. The .has_timings_switch is renamed to .ccu_has_timings_switch to clarify its meaning. Signed-off-by: NChen-Yu Tsai <wens@csie.org> Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
This patch adds the initial support of Secure Digital Host Controller Interface compliant controller found in some latest Spreadtrum chipsets. This patch has been tested on the version of SPRD-R11 controller. R11 is a variant based on SD v4.0 specification. With this driver, R11 mmc can be initialized, can be mounted, read and written. Original-by: NBillows Wu <billows.wu@unisoc.com> Signed-off-by: NChunyan Zhang <chunyan.zhang@unisoc.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
When Host Version 4 Enable is set to 1, SDMA uses ADMA System Address register (05Fh-058h) instead of using register (000h-004h) to indicate its system address of data location. The register (000h-004h) is re-assigned to 32-bit Block Count and Auto CMD23 argument, so then SDMA may use Auto CMD23. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
As SD Host Controller Specification v4.10 documents: Host Controller Version 4.10 defines this "Auto CMD Auto Select" mode. Selection of Auto CMD depends on setting of CMD23 Enable in the Host Control 2 register which indicates whether card supports CMD23. If CMD23 Enable =1, Auto CMD23 is used and if CMD23 Enable =0, Auto CMD12 is used. In case of Version 4.10 or later, use of Auto CMD Auto Select is recommended rather than use of Auto CMD12 Enable or Auto CMD23 Enable. This patch add this new mode support. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
Host Controller Version 4.10 re-defines SDMA System Address register as 32-bit Block Count for v4 mode, and SDMA uses ADMA System Address register (05Fh-058h) instead if v4 mode is enabled. Also when using 32-bit block count, 16-bit block count register need to be set to zero. Since using 32-bit Block Count would cause problems for auto-cmd23, it can be chosen via host->quirk2. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
ADMA2 64-bit addressing support is divided into V3 mode and V4 mode. So there are two kinds of descriptors for ADMA2 64-bit addressing i.e. 96-bit Descriptor for V3 mode, and 128-bit Descriptor for V4 mode. 128-bit Descriptor is aligned to 8-byte. For V4 mode, ADMA2 64-bit addressing is enabled via Host Control 2 register. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> [Ulf: Fixed conflict while applying] Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
According to the SD host controller specification version 4.10, when Host Version 4 is enabled, SDMA uses ADMA System Address register (05Fh-058h) instead of using SDMA System Address register to support both 32-bit and 64-bit addressing. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
For SD host controller version 4.00 or later ones, there're two modes of implementation - Version 3.00 compatible mode or Version 4 mode. This patch introduced an interface to enable v4 mode. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Chunyan Zhang 提交于
Added definitions for v400, v410, v420. Signed-off-by: NChunyan Zhang <zhang.chunyan@linaro.org> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 YueHaibing 提交于
Fix inconsistent IS_ERR and PTR_ERR in tegra_sdhci_init_pinctrl_info, the proper pointer to be passed as argument is 'pinctrl_state_1v8' Signed-off-by: NYueHaibing <yuehaibing@huawei.com> Reviewed-by: NAapo Vienamo <aapo.vienamo@iki.fi> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Rerun the pad calibration procedure before sdhci_request() if the 100 ms recalibration interval has been exceeded. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Implement HS400 specific delay line calibration procedure. This is a Tegra specific procedure and has to be performed regardless whether enhanced strobe or HS400 tuning is used. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Implement eMMC HS400 enhanced strobe. Enhanced strobe is an alternative mechanism to the HS400 tuning procedure. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Parse and program the HS400 DQS trim value from DT. Program a fallback value in case the property is missing. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Acked-by: NThierry Reding <treding@nvidia.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Set nvquirks to enable higher speed modes. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Set nvquirks to enable higher speed modes. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Implement tegra210_sdhci_writew() to disable card clock and issue a reset when the tuning command is sent. This is done to prevent an intermittent hang with around 10 % failure rate during tuning. Add tegra186_sdhci_ops because this workaround is specific to Tegra210. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
tegra_sdhci_writew() defers the write to SDHCI_TRANSFER_MODE until SDHCI_COMMAND is written. This is not necessary on Tegra210 and Tegra186 and it breaks read-modify-write operations on SDHCI_TRANSFER_MODE because writes to SDHCI_TRANSFER_MODE aren't visible until SDHCI_COMMAND has been written to. This results in tuning failures on Tegra210. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Add a new sdhci_ops struct for Tegra210 and Tegra186 which doesn't set the custom tuning callback used on previous SoC generations. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Program the outbound sampling trim value in tegra_sdhci_reset(). Unlike the outbound tap value this does not depend on the signaling mode and needs to be only programmed once. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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由 Aapo Vienamo 提交于
Set the default inbound timing adjustment tap value on reset and on non-tunable modes. The default tap value is not programmed on tunable modes because the tuning sequence is used instead to determine the tap value. Signed-off-by: NAapo Vienamo <avienamo@nvidia.com> Acked-by: NThierry Reding <treding@nvidia.com> Acked-by: NAdrian Hunter <adrian.hunter@intel.com> Signed-off-by: NUlf Hansson <ulf.hansson@linaro.org>
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