- 20 9月, 2011 2 次提交
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由 Dimitris Papastamos 提交于
This is the simplest form of a cache available in regcache. Any registers whose default value is 0 are ignored. If any of those registers are modified in the future, they will be placed in the cache on demand. The cache layout is essentially using the provided register defaults by the regcache core directly and does not re-map it to another representation. Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Dimitris Papastamos 提交于
This patch introduces caching support for regmap. The regcache API has evolved essentially out of ASoC soc-cache so most of the actual caching types (except LZO) have been tested in the past. The purpose of regcache is to optimize in time and space the handling of register caches. Time optimization is achieved by not having to go over a slow bus like I2C to read the value of a register, instead it is cached locally in memory and can be retrieved faster. Regarding space optimization, some of the cache types are better at packing the caches, for e.g. the rbtree and the LZO caches. By doing this the sacrifice in time still wins over doing I2C transactions. Signed-off-by: NDimitris Papastamos <dp@opensource.wolfsonmicro.com> Tested-by: NLars-Peter Clausen <lars@metafoo.de> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 10 9月, 2011 1 次提交
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由 Mark Brown 提交于
Add the externally visible interface introduced by Lars-Peter's commit 6f3064 (regmap: Add support for device specific write and read flag masks) separately in order to allow merge into other subsystems for integration with drivers. Drivers relying on this feature will not be functional until they are merged with the implementation. Signed-off-by: NLars-Peter Clausen <lars@metafoo.de> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 06 9月, 2011 2 次提交
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由 Lars-Peter Clausen 提交于
Some buses like SPI have no standard notation of read or write operations. The general scheme here is to set or clear specific bits in the register address to indicate whether the operation is a read or write. We already support having a read flag mask per bus, but as there is no standard the bits which need to be set or cleared differ between devices and vendors, thus we need a mechanism to specify them per device. This patch adds two new entries to the regmap_config struct, read_flag_mask and write_flag_mask. These will be or'ed onto the top byte when doing a read or write operation. If both masks are empty the device will fallback to the regmap_bus masks. Signed-off-by: NLars-Peter Clausen <lars@metafoo.de> Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Mark Brown 提交于
No longer used as users link directly with the bus types so the core module infrastructure does refcounting for us. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 21 8月, 2011 1 次提交
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由 Mark Brown 提交于
It is useful for the register cache code to be able to specify the default values for the device registers. The major use is when restoring the register cache after suspend, knowing the register defaults allows us to skip registers that are at their default values when we resume which can be a substantial win on larger modern devices. For some devices (mostly older ones) the hardware does not support readback so the only way we can know the values is from code and so initializing the cache with default values makes it much easier for drivers work with read/modify/write updates. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 09 8月, 2011 2 次提交
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由 Mark Brown 提交于
We no longer enumerate the bus types, we rely on the driver telling us this on init. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Mark Brown 提交于
Field names didn't match between the documentation and the code. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 08 8月, 2011 3 次提交
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由 Mark Brown 提交于
Some devices are sensitive to reads on their registers, especially for things like clear on read interrupt status registers. Avoid creating problems with these with things like debugfs by allowing drivers to tell the core about them. If a register is marked as precious then the core will not internally generate any reads of it. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Mark Brown 提交于
This is currently unused but we need to know which registers exist and their properties in order to implement diagnostics like register map dumps and the cache features. We use callbacks partly because properties can vary at runtime (eg, through access locks on registers) and partly because big switch statements are a good compromise between readable code and small data size for providing information on big register maps. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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由 Mark Brown 提交于
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com>
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- 23 7月, 2011 3 次提交
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由 Mark Brown 提交于
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NLiam Girdwood <lrg@ti.com> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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由 Mark Brown 提交于
Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NLiam Girdwood <lrg@ti.com> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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由 Mark Brown 提交于
There are many places in the tree where we implement register access for devices on non-memory mapped buses, especially I2C and SPI. Since hardware designers seem to have settled on a relatively consistent set of register interfaces this can be effectively factored out into shared code. There are a standard set of formats for marshalling data for exchange with the device, with the actual I/O mechanisms generally being simple byte streams. We create an abstraction for marshaling data into formats which can be sent on the control interfaces, and create a standard method for plugging in actual transport underneath that. This is mostly a refactoring and renaming of the bottom level of the existing code for sharing register I/O which we have in ASoC. A subsequent patch in this series converts ASoC to use this. The main difference in interface is that reads return values by writing to a location provided by a pointer rather than in the return value, ensuring we can use the full range of the type for register data. We also use unsigned types rather than ints for the same reason. As some of the devices can have very large register maps the existing ASoC code also contains infrastructure for managing register caches. This cache work will be moved over in a future stage to allow for separate review, the current patch only deals with the physical I/O. Signed-off-by: NMark Brown <broonie@opensource.wolfsonmicro.com> Acked-by: NLiam Girdwood <lrg@ti.com> Acked-by: NGreg Kroah-Hartman <gregkh@suse.de> Acked-by: NWolfram Sang <w.sang@pengutronix.de> Acked-by: NGrant Likely <grant.likely@secretlab.ca>
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