1. 31 10月, 2014 3 次提交
  2. 18 10月, 2014 1 次提交
    • G
      dsa: Fix conversion from host device to mii bus · b184e497
      Guenter Roeck 提交于
      Commit b4d2394d ("dsa: Replace mii_bus with a generic host device")
      replaces mii_bus with a generic host_dev, and introduces
      dsa_host_dev_to_mii_bus() to support conversion from host_dev to mii_bus.
      However, in some cases it uses to_mii_bus to perform that conversion.
      Since host_dev is not the phy bus device but typically a platform device,
      this fails and results in a crash with the affected drivers.
      
      BUG: unable to handle kernel NULL pointer dereference at           (null)
      IP: [<ffffffff81781d35>] __mutex_lock_slowpath+0x75/0x100
      PGD 406783067 PUD 406784067 PMD 0
      Oops: 0002 [#1] SMP
      ...
      Call Trace:
      [<ffffffff810a538b>] ? pick_next_task_fair+0x61b/0x880
      [<ffffffff81781de3>] mutex_lock+0x23/0x37
      [<ffffffff81533244>] mdiobus_read+0x34/0x60
      [<ffffffff8153b95a>] __mv88e6xxx_reg_read+0x8a/0xa0
      [<ffffffff8153b9bc>] mv88e6xxx_reg_read+0x4c/0xa0
      
      Fixes: b4d2394d ("dsa: Replace mii_bus with a generic host device")
      Cc: Alexander Duyck <alexander.h.duyck@intel.com>
      Signed-off-by: NGuenter Roeck <linux@roeck-us.net>
      Acked-by: NAlexander Duyck <alexander.h.duyck@redhat.com>
      Acked-by: NFlorian Fainelli <f.fainelli@gmail.com>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      b184e497
  3. 16 9月, 2014 1 次提交
  4. 14 9月, 2014 1 次提交
  5. 01 5月, 2014 1 次提交
  6. 10 1月, 2013 4 次提交
  7. 25 1月, 2012 1 次提交
  8. 29 11月, 2011 2 次提交
  9. 27 11月, 2011 2 次提交
  10. 06 7月, 2009 1 次提交
  11. 26 11月, 2008 1 次提交
  12. 09 10月, 2008 2 次提交
    • L
      dsa: add support for the Marvell 88E6131 switch chip · 2e5f0320
      Lennert Buytenhek 提交于
      Add support for the Marvell 88E6131 switch chip.  This chip only
      supports the original (ethertype-less) DSA tagging format.
      
      On the 88E6131, there is a PHY Polling Unit (PPU) which has exclusive
      access to each of the PHYs's MII management registers.  If we want to
      talk to the PHYs from software, we have to disable the PPU and wait
      for it to complete its current transaction before we can do so, and we
      need to re-enable the PPU afterwards to make sure that the switch will
      notice changes in link state and speed on the individual ports as they
      occur.
      
      Since disabling the PPU is rather slow, and since MII management
      accesses are typically done in bursts, this patch keeps the PPU disabled
      for 10ms after a software access completes.  This makes handling the
      PPU slightly more complex, but speeds up something like running ethtool
      on one of the switch slave interfaces from ~300ms to ~30ms on typical
      hardware.
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      Tested-by: NNicolas Pitre <nico@marvell.com>
      Tested-by: NPeter van Valderen <linux@ddcrew.com>
      Tested-by: NDirk Teurlings <dirk@upexia.nl>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      2e5f0320
    • L
      net: Distributed Switch Architecture protocol support · 91da11f8
      Lennert Buytenhek 提交于
      Distributed Switch Architecture is a protocol for managing hardware
      switch chips.  It consists of a set of MII management registers and
      commands to configure the switch, and an ethernet header format to
      signal which of the ports of the switch a packet was received from
      or is intended to be sent to.
      
      The switches that this driver supports are typically embedded in
      access points and routers, and a typical setup with a DSA switch
      looks something like this:
      
      	+-----------+       +-----------+
      	|           | RGMII |           |
      	|           +-------+           +------ 1000baseT MDI ("WAN")
      	|           |       |  6-port   +------ 1000baseT MDI ("LAN1")
      	|    CPU    |       |  ethernet +------ 1000baseT MDI ("LAN2")
      	|           |MIImgmt|  switch   +------ 1000baseT MDI ("LAN3")
      	|           +-------+  w/5 PHYs +------ 1000baseT MDI ("LAN4")
      	|           |       |           |
      	+-----------+       +-----------+
      
      The switch driver presents each port on the switch as a separate
      network interface to Linux, polls the switch to maintain software
      link state of those ports, forwards MII management interface
      accesses to those network interfaces (e.g. as done by ethtool) to
      the switch, and exposes the switch's hardware statistics counters
      via the appropriate Linux kernel interfaces.
      
      This initial patch supports the MII management interface register
      layout of the Marvell 88E6123, 88E6161 and 88E6165 switch chips, and
      supports the "Ethertype DSA" packet tagging format.
      
      (There is no officially registered ethertype for the Ethertype DSA
      packet format, so we just grab a random one.  The ethertype to use
      is programmed into the switch, and the switch driver uses the value
      of ETH_P_EDSA for this, so this define can be changed at any time in
      the future if the one we chose is allocated to another protocol or
      if Ethertype DSA gets its own officially registered ethertype, and
      everything will continue to work.)
      Signed-off-by: NLennert Buytenhek <buytenh@marvell.com>
      Tested-by: NNicolas Pitre <nico@marvell.com>
      Tested-by: NByron Bradley <byron.bbradley@gmail.com>
      Tested-by: NTim Ellis <tim.ellis@mac.com>
      Tested-by: NPeter van Valderen <linux@ddcrew.com>
      Tested-by: NDirk Teurlings <dirk@upexia.nl>
      Signed-off-by: NDavid S. Miller <davem@davemloft.net>
      91da11f8