1. 10 2月, 2015 1 次提交
  2. 09 2月, 2015 3 次提交
  3. 05 2月, 2015 1 次提交
  4. 31 1月, 2015 7 次提交
  5. 30 1月, 2015 2 次提交
  6. 29 1月, 2015 11 次提交
  7. 28 1月, 2015 1 次提交
    • C
      agp/intel: Serialise after GTT updates · 983d308c
      Chris Wilson 提交于
      An interesting bug occurs on Pineview through which the root cause is
      that the writes of the PTE values into the GTT is not serialised with
      subsequent memory access through the GTT (when using WC updates of the
      PTE values). This is despite there being a posting read after the GTT
      update. However, by changing the address of the posting read, the memory
      access is indeed serialised correctly.
      
      Whilst we are manipulating the memory barriers, we can remove the
      compiler :memory restraint on the intermediate PTE writes knowing that
      we explicitly perform a posting read afterwards.
      
      v2: Replace posting reads with explicit write memory barriers - in
      particular this is advantages in case of single page objects. Update
      comments to mention this issue is only with WC writes.
      
      Testcase: igt/gem_exec_big #pnv
      Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88191
      Tested-by: huax.lu@intel.com (v1)
      Signed-off-by: NChris Wilson <chris@chris-wilson.co.uk>
      Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
      Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
      983d308c
  8. 27 1月, 2015 14 次提交