Use DEFINE_SHOW_ATTRIBUTE macro to simplify the code.
Signed-off-by: NYangtao Li <tiny.windzz@gmail.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

devm_kasprintf() may return NULL on failure of internal allocation thus
the assignment to  .label  is not safe if not checked. On error
npcm7xx_gpio_of() returns negative values so -ENOMEM in the
(unlikely) failure case of devm_kasprintf() should be fine here.
Signed-off-by: NNicholas Mc Guire <hofrat@osadl.org>
Fixes: 3b588e43 ("pinctrl: nuvoton: add NPCM7xx pinctrl and GPIO driver")
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Let's add "qcom,pms405-gpio" to match table, as commit ed80f6eb
("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support") already
adds the compatible.
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Rather than gpio1-gpio11 for pms405, there are 12 GPIOs for pms405.
But gpio1, gpio9 and gpio10 are not available.  Fix the bindings doc
to make it correct for pms405.

Fixes: ed80f6eb ("dt-bindings: pinctrl: qcom-pmic-gpio: Add pms405 support")
Signed-off-by: NShawn Guo <shawn.guo@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Merge tag 'sh-pfc-for-v4.21-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into devel

pinctrl: sh-pfc: Updates for v4.21

  - Fix VIN (Video IN) versioned groups on R-Car V2H, H3, and M3-W,
  - Add I2C[0-3], DU1, VIN, QSPI1, and SDHI pin groups on RZ/G1C,
  - Add audio, SDHI, VIN, HSCIF, and CAN(FD) support on R-Car E3,
  - Add QSPI pin groups on R-Car V3M and V3H,
  - Add VIN and CAN(FD) pin groups on R-Car M3-N,
  - Add I2C[035] pin groups on R-Car H3 and M3-W,
  - Add pinctrl and GPIO support for the new RZ/A2M (R7S9210) SoC,
  - Small cleanups,
  - Maintainership updates.

The suniv F1C100s chip (several new F-series SoCs) of Allwinner has a
pin
controller like other SoCs from Allwinner.

Add support for it.
Signed-off-by: NMesih Kilinc <mesihkilinc@gmail.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add compatible string for Allwinner suniv F1C100s SoC's pinctrl.
Signed-off-by: NMesih Kilinc <mesihkilinc@gmail.com>
Acked-by: NMaxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adds support for the pin and gpio controller found in R7S9210 (RZ/A2) SoCs.
Signed-off-by: NChris Brandt <chris.brandt@renesas.com>
Reviewed-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add device tree binding documentation and header file for Renesas R7S9210
(RZ/A2) SoCs.
Signed-off-by: NChris Brandt <chris.brandt@renesas.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Reviewed-by: NJacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Add the QSPI{0|1} pins/groups/functions to the R8A77980 PFC driver.

[Sergei: ported to the upstream driver, fixed up the swapped QSPI0 SPCLK/
SSL pins, fixed up the comments, moved the QSPI pins/groups/functions to
be in the alphanumeric order, removed unneeded empty lines, renamed the
patch.]
Signed-off-by: NDmitry Shifrin <dmitry.shifrin@cogentembedded.com>
Signed-off-by: NSergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

In preparation to remove the node name pointer from struct device_node,
convert printf users to use the %pOFn format specifier.

Cc: Matthias Brugger <matthias.bgg@gmail.com>
Cc: linux-mediatek@lists.infradead.org
Cc: linux-gpio@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: NRob Herring <robh@kernel.org>
Acked-by: NSean Wang <sean.wang@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add PM suspend callbacks to the msm core driver that select the
sleep and default pinctrl states. Then wire those callbacks up
in the sdm845 driver, for those boards that may have GPIO hogs
that need to change state during suspend.
Signed-off-by: NEvan Green <evgreen@chromium.org>
Reviewed-by: NStephen Boyd <swboyd@chromium.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This updates bindings for MT7629 pinctrl driver.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Reviewed-by: NSean Wang <sean.wang@kernel.org>
Reviewed-by: NRob Herring <robh@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This adds MT7629 pinctrl driver based on MediaTek pinctrl-moore core.
Signed-off-by: NRyder Lee <ryder.lee@mediatek.com>
Acked-by: NSean Wang <sean.wang@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

After patch b96eea71 ("pinctrl: fsl: add scu based pinctrl support"),
NO_PAD_CTL pads map are not skipped anymore which results in
a possible memory corruption. As we actually only need to create config
maps for SCU pads and MMIO pads which are not using the default config
(a.k.a IMX_NO_PAD_CTL), so let's add a proper check before creating
the config maps. And during MMIO pads parsing, we also need update the
list_p point as SCU case to ensure the pin data next parsed is correct.

Cc: Linus Walleij <linus.walleij@linaro.org>
Fixes: b96eea71 ("pinctrl: fsl: add scu based pinctrl support")
Reported-by: NMartin Kaiser <martin@kaiser.cx>
Suggested-by: NLeonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: NDong Aisheng <aisheng.dong@nxp.com>
Reviewed-by: NMartin Kaiser <martin@kaiser.cx>
Tested-by: NLeonard Crestez <leonard.crestez@nxp.com>
Tested-by: NKevin Hilman <khilman@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pinctrl and gpio driver for Actions Semi S700 SoC. The driver
supports pinctrl, pinmux, pinconf, gpio and interrupt functionalities
through a range of registers common to both gpio driver and pinctrl driver.
Signed-off-by: NParthiban Nallathambi <pn@denx.de>
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add pinctrl and pio bindings for Actions Semi S700 SoC.
Signed-off-by: NParthiban Nallathambi <pn@denx.de>
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Reviewed-by: NRob Herring <robh@kernel.org>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

pad control for s900 and s700 are differs in number of
pull control configuraions
s900 has 4 pull controls - high impedence, pull up, pull down, repeater
s700, s500 has 2 pull controls - pull up and pull down

so pad control configuration has to SoC specific, moved out from pinctrl
common to s900 specific.
Signed-off-by: NParthiban Nallathambi <pn@denx.de>
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Move generic defines common to the Owl family out of S900 driver.
Signed-off-by: NParthiban Nallathambi <pn@denx.de>
Signed-off-by: NSaravanan Sekar <sravanhome@gmail.com>
Acked-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

If a hwspinlock if defined in device tree use it to protect
configuration registers.
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@st.com>
Acked-by: NAlexandre TORGUE <alexandre.torgue@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add hwlocks as optional property
Signed-off-by: NBenjamin Gaignard <benjamin.gaignard@st.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

This patch adds CAN FD{0,1} pins, groups and functions to the R8A77990
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
[geert: Move canfd from common to automotive]
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN{0,1} pins, groups and functions to the R8A77990 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN FD{0,1} pins, groups and functions to the R8A77965
SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds CAN{0,1} pins, groups and functions to the R8A77965 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NMarek Vasut <marek.vasut+renesas@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7796 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds I2C{0,3,5} pins, groups and functions to
the R8A7795 ES1.x SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

This patch adds I2C{0,3,5} pins, groups and functions to the R8A7795 SoC.

These pins are physically muxed with other pins. Therefore, setup of
MOD_SEL is needed for exclusive control with other pins.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

Used by I2C controllers 0, 3 and 5 in R8A7795 and R8A7796 SoCs.
Signed-off-by: NUlrich Hecht <uli+renesas@fpond.eu>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The PINMUX_IPSR_MSEL2() and PINMUX_IPSR_PHYS() macros are unused, and
will conflict with generic macros that are to be added.
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: NSimon Horman <horms+renesas@verge.net.au>

This patch adds HSCIF{0,1,2,3,4} pins, groups and functions to
the R8A77990 SoC.
Signed-off-by: NTakeshi Kihara <takeshi.kihara.df@renesas.com>
Signed-off-by: NYoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: NGeert Uytterhoeven <geert+renesas@glider.be>

The rk3188 has pins that are not handled through the regular iomuxing
for handling either nand-flash or an emmc and are set through only one
specifal setting. So utilize the routing function to simply do that
setting depending on one of the core nand/emmc signals that are actually
regular pins handled through pinctrl.
Signed-off-by: NHeiko Stuebner <heiko.stuebner@bq.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Right now we expect the pin-rounting settings to be in the same area
as the iomux setting itself. And while that seems to be true for all
newer Rockchip socs, back in the wild west days of old this wasn't true.

Nowadays pin settings in the GRF normally stay in the GRF and the same
is true for pins configured from PMU registers. But old socs like the
rk3188 really sprinkle pin settings somewhat randomly through both
for its bank0.

Therefore add the option to specify a location for the route setting,
so that we can map older socs correctly. We'll keep "same" as the
default, so that we only need to specify a location in the corner-cases
described above.
Signed-off-by: NHeiko Stuebner <heiko.stuebner@bq.com>
Reviewed-by: NDavid Wu <david.wu@rock-chips.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

When attempting to setup up a gpio hog, device probing will repeatedly
fail with -EPROBE_DEFERED errors. It is caused by a circular dependency
between the gpio and pinctrl frameworks. If the gpio-ranges property is
present in device tree, then the gpio framework will handle the gpio pin
registration and eliminate the circular dependency.

See Christian Lamparter's commit a86caa9b ("pinctrl: msm: fix
gpio-hog related boot issues") for a detailed commit message that
explains the issue in much more detail. The code comment in this commit
came from Christian's commit.

I did not test this change against any hardware supported by this
particular driver, however I was able to validate this same fix works
for pinctrl-spmi-gpio.c using a LG Nexus 5 (hammerhead) phone.
Signed-off-by: NBrian Masney <masneyb@onstation.org>
Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Adopt the SPDX license identifier headers to ease license compliance
management.

Cc: Simon Arlott <simon@arlott.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: NStefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: NEric Anholt <eric@anholt.net>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Modify GPIO direction setting in pin configuration function by using
generic GPIO functions to set the GPIO direction instead of direct
access to the GPIO direction register.
Signed-off-by: NTomer Maimon <tmaimon77@gmail.com>
Tested-by: NKun Yi <kunyi@google.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add initial pinctrl driver for Mediatek MT6797 SoC supporting only
GPIO and pinmux configurations.
Tested-by: NMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: NSean Wang <sean.wang@kernel.org>
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Add devicetree bindings for Mediatek MT6797 SoC Pin Controller.
Signed-off-by: NManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

The GPIOX tsin_a pins wrongly uses the SDCard pinctrl bits, this
patch completely removes these pins entries until we find out what
are the correct bits and registers to be used instead.

Fixes: 5a6ae9b8 ("pinctrl: meson-gxl: add tsin_a pins")
Signed-off-by: NNeil Armstrong <narmstrong@baylibre.com>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>

Fixes the following config-time warning:

WARNING: unmet direct dependencies detected for EINT_MTK
  Depends on [n]: PINCTRL [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n]) && (PINCTRL_MTK [=n] || PINCTRL_MTK_MOORE [=n] || COMPILE_TEST [=n])
  Selected by [y]:
  - PINCTRL_MTK_PARIS [=y] && PINCTRL [=y] && OF [=y] && (ARCH_MEDIATEK [=y] || COMPILE_TEST [=n])

Fixes: 80525098 ("pinctrl: mediatek: add pinctrl-paris that implements the vendor dt-bindings")
Signed-off-by: NOlof Johansson <olof@lixom.net>
Acked-by: NSean Wang <sean.wang@kernel.org>
Signed-off-by: NLinus Walleij <linus.walleij@linaro.org>