- 29 5月, 2010 1 次提交
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由 Len Brown 提交于
commit d306ebc2 (ACPI: Be in TS_POLLING state during mwait based C-state entry) fixed an important power & performance issue where ACPI c2 and c3 C-states were clearing TS_POLLING even when using MWAIT (ACPI_STATE_FFH). That bug had been causing us to receive redundant scheduling interrups when we had already been woken up by MONITOR/MWAIT. Following up on that... In the MWAIT case, we don't have to subsequently check need_resched(), as that c heck was there for the TS_POLLING-clearing case. Note that not only does the cpuidle calling function already check need_resched() before calling us, the low-level entry into monitor/mwait calls it twice -- guaranteeing that a write to the trigger address can not go un-noticed. Also, in this case, we don't have to set TS_POLLING when we wake, because we never cleared it. Signed-off-by: NLen Brown <len.brown@intel.com> Acked-by: NVenkatesh Pallipadi <venki@google.com>
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- 30 3月, 2010 1 次提交
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由 Tejun Heo 提交于
include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h percpu.h is included by sched.h and module.h and thus ends up being included when building most .c files. percpu.h includes slab.h which in turn includes gfp.h making everything defined by the two files universally available and complicating inclusion dependencies. percpu.h -> slab.h dependency is about to be removed. Prepare for this change by updating users of gfp and slab facilities include those headers directly instead of assuming availability. As this conversion needs to touch large number of source files, the following script is used as the basis of conversion. http://userweb.kernel.org/~tj/misc/slabh-sweep.py The script does the followings. * Scan files for gfp and slab usages and update includes such that only the necessary includes are there. ie. if only gfp is used, gfp.h, if slab is used, slab.h. * When the script inserts a new include, it looks at the include blocks and try to put the new include such that its order conforms to its surrounding. It's put in the include block which contains core kernel includes, in the same order that the rest are ordered - alphabetical, Christmas tree, rev-Xmas-tree or at the end if there doesn't seem to be any matching order. * If the script can't find a place to put a new include (mostly because the file doesn't have fitting include block), it prints out an error message indicating which .h file needs to be added to the file. The conversion was done in the following steps. 1. The initial automatic conversion of all .c files updated slightly over 4000 files, deleting around 700 includes and adding ~480 gfp.h and ~3000 slab.h inclusions. The script emitted errors for ~400 files. 2. Each error was manually checked. Some didn't need the inclusion, some needed manual addition while adding it to implementation .h or embedding .c file was more appropriate for others. This step added inclusions to around 150 files. 3. The script was run again and the output was compared to the edits from #2 to make sure no file was left behind. 4. Several build tests were done and a couple of problems were fixed. e.g. lib/decompress_*.c used malloc/free() wrappers around slab APIs requiring slab.h to be added manually. 5. The script was run on all .h files but without automatically editing them as sprinkling gfp.h and slab.h inclusions around .h files could easily lead to inclusion dependency hell. Most gfp.h inclusion directives were ignored as stuff from gfp.h was usually wildly available and often used in preprocessor macros. Each slab.h inclusion directive was examined and added manually as necessary. 6. percpu.h was updated not to include slab.h. 7. Build test were done on the following configurations and failures were fixed. CONFIG_GCOV_KERNEL was turned off for all tests (as my distributed build env didn't work with gcov compiles) and a few more options had to be turned off depending on archs to make things build (like ipr on powerpc/64 which failed due to missing writeq). * x86 and x86_64 UP and SMP allmodconfig and a custom test config. * powerpc and powerpc64 SMP allmodconfig * sparc and sparc64 SMP allmodconfig * ia64 SMP allmodconfig * s390 SMP allmodconfig * alpha SMP allmodconfig * um on x86_64 SMP allmodconfig 8. percpu.h modifications were reverted so that it could be applied as a separate patch and serve as bisection point. Given the fact that I had only a couple of failures from tests on step 6, I'm fairly confident about the coverage of this conversion patch. If there is a breakage, it's likely to be something in one of the arch headers which should be easily discoverable easily on most builds of the specific arch. Signed-off-by: NTejun Heo <tj@kernel.org> Guess-its-ok-by: NChristoph Lameter <cl@linux-foundation.org> Cc: Ingo Molnar <mingo@redhat.com> Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
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- 23 2月, 2010 1 次提交
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由 Pallipadi, Venkatesh 提交于
ACPI deep C-state entry had a long standing bug/missing feature, wherein we were sending resched IPIs when an idle CPU is in mwait based deep C-state. Only mwait based C1 was using the write to the monitored address to wake up mwait'ing CPU. This patch changes the code to retain TS_POLLING bit if we are entering an mwait based deep C-state. The patch has been verified to reduce the number of resched IPIs in general and also improves the performance/power on workloads with low system utilization (i.e., when mwait based deep C-states are being used). Fixes "netperf ~50% regression with 2.6.33-rc1, bisect to 1b9508f6" http://marc.info/?l=linux-kernel&m=126441481427331&w=4Reported-by: NLin Ming <ming.m.lin@intel.com> Tested-by: NAlex Shi <alex.shi@intel.com> Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 16 2月, 2010 1 次提交
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由 Arjan van de Ven 提交于
Since the rewrite of the CPU idle governor in 2.6.32, two laptops have surfaced where the BIOS advertises a C2 power state, but for some reason this state is not functioning (as verified in both cases by powertop before the patch in .32). The old governor had the accidental behavior that if a non-working state was chosen too many times, it would end up falling back to C1. The new governor works differently and this accidental behavior is no longer there; the result is a high temperature on these two machines. This patch adds these 2 machines to the DMI table for C state anomalies; by just not using C2 both these machines are better off (the TSC can be used instead of the pm timer, giving a performance boost for example). Addresses http://bugzilla.kernel.org/show_bug.cgi?id=14742Signed-off-by: NArjan van de Ven <arjan@linux.intel.com> Reported-by: <akwatts@ymail.com> Cc: <stable@kernel.org> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 28 1月, 2010 1 次提交
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由 Lin Ming 提交于
acpi_integer is now obsolete and removed from the ACPICA code base, replaced by u64. Signed-off-by: NLin Ming <ming.m.lin@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 20 1月, 2010 3 次提交
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由 Len Brown 提交于
no functional change -- cleanup only. acpi_processor_power_verify_c2() was nearly empty due to a previous patch, so expand its remains into its one caller and delete it. Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Len Brown 提交于
Do for C3 what the previous patch did for C2. The C2 patch was in response to a highly visible and multiply reported C-state/turbo failure, while this change has no bug report in-hand. This will enable C3 in Linux on systems where BIOS overstates C3 latency in _CST. It will also enable future systems which may actually have C3 > 1000usec. Linux has always ignored ACPI BIOS C3 with exit latency > 1000 usec, and the ACPI spec is clear that is correct FADT-supplied C3. However, the ACPI spec explicitly states that _CST-supplied C-states have no latency limits. So move the 1000usec C3 test out of the code shared by FADT and _CST code-paths, and into the FADT-specific path. Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Len Brown 提交于
Linux has always ignored ACPI BIOS C2 with exit latency > 100 usec, and the ACPI spec is clear that is correct FADT-supplied C2. However, the ACPI spec explicitly states that _CST-supplied C-states have no latency limits. So move the 100usec C2 test out of the code shared by FADT and _CST code-paths, and into the FADT-specific path. This bug has not been visible until Nehalem, which advertises a CPU-C2 worst case exit latency on servers of 205usec. That (incorrect) figure is being used by BIOS writers on mobile Nehalem systems for the AC configuration. Thus, Linux ignores C2 leaving just C1, which is saves less power, and also impacts performance by preventing the use of turbo mode. http://bugzilla.kernel.org/show_bug.cgi?id=15064Tested-by: NAlex Chiang <achiang@hp.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 16 12月, 2009 1 次提交
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由 Hidetoshi Seto 提交于
I got following warning on ia64 box: In function 'acpi_processor_power_verify': 642: warning: passing argument 2 of 'smp_call_function_single' from incompatible pointer type This smp_call_function_single() was introduced by a commit f833bab8: > @@ -162,8 +162,9 @@ > pr->power.timer_broadcast_on_state = state; > } > > -static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) > +static void lapic_timer_propagate_broadcast(void *arg) > { > + struct acpi_processor *pr = (struct acpi_processor *) arg; > unsigned long reason; > > reason = pr->power.timer_broadcast_on_state < INT_MAX ? > @@ -635,7 +636,8 @@ > working++; > } > > - lapic_timer_propagate_broadcast(pr); > + smp_call_function_single(pr->id, lapic_timer_propagate_broadcast, > + pr, 1); > > return (working); > } The problem is that the lapic_timer_propagate_broadcast() has 2 versions: One is real code that modified in the above commit, and the other is NOP code that used when !ARCH_APICTIMER_STOPS_ON_C3: static void lapic_timer_propagate_broadcast(struct acpi_processor *pr) { } So I got warning because of !ARCH_APICTIMER_STOPS_ON_C3. We really want to do nothing here on !ARCH_APICTIMER_STOPS_ON_C3, so modify lapic_timer_propagate_broadcast() of real version to use smp_call_function_single() in it. Signed-off-by: NHidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Acked-by: NSuresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 28 9月, 2009 1 次提交
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由 Linus Torvalds 提交于
Commit 3d5b6fb4 ("ACPI: Kill overly verbose "power state" log messages") removed the actual use of this variable, but didn't remove the variable itself, resulting in build warnings like drivers/acpi/processor_idle.c: In function ‘acpi_processor_power_init’: drivers/acpi/processor_idle.c:1169: warning: unused variable ‘i’ Just get rid of the now unused variable. Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 27 9月, 2009 1 次提交
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由 Roland Dreier 提交于
I was recently lucky enough to get a 64-CPU system, so my kernel log ends up with 64 lines like: ACPI: CPU0 (power states: C1[C1] C2[C3]) This is pretty useless clutter because this info is already available after boot from both /sys/devices/system/cpu/cpu*/cpuidle/state?/ as well as /proc/acpi/processor/CPU*/power. So just delete the code that prints the C-states in processor_idle.c. Signed-off-by: NRoland Dreier <rolandd@cisco.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 29 8月, 2009 1 次提交
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由 Len Brown 提交于
Linux/ACPI core files using internal.h all PREFIX "ACPI: ", however, not all ACPI drivers use/want it -- and they should not have to #undef PREFIX to define their own. Add GPL commment to internal.h while we are there. This does not change any actual console output, asside from a whitespace fix. Signed-off-by: NLen Brown <len.brown@intel.com>
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- 20 8月, 2009 1 次提交
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由 Suresh Siddha 提交于
Currently clockevents_notify() is called with interrupts enabled at some places and interrupts disabled at some other places. This results in a deadlock in this scenario. cpu A holds clockevents_lock in clockevents_notify() with irqs enabled cpu B waits for clockevents_lock in clockevents_notify() with irqs disabled cpu C doing set_mtrr() which will try to rendezvous of all the cpus. This will result in C and A come to the rendezvous point and waiting for B. B is stuck forever waiting for the spinlock and thus not reaching the rendezvous point. Fix the clockevents code so that clockevents_lock is taken with interrupts disabled and thus avoid the above deadlock. Also call lapic_timer_propagate_broadcast() on the destination cpu so that we avoid calling smp_call_function() in the clockevents notifier chain. This issue left us wondering if we need to change the MTRR rendezvous logic to use stop machine logic (instead of smp_call_function) or add a check in spinlock debug code to see if there are other spinlocks which gets taken under both interrupts enabled/disabled conditions. Signed-off-by: NSuresh Siddha <suresh.b.siddha@intel.com> Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Cc: "Pallipadi Venkatesh" <venkatesh.pallipadi@intel.com> Cc: "Brown Len" <len.brown@intel.com> LKML-Reference: <1250544899.2709.210.camel@sbs-t61.sc.intel.com> Signed-off-by: NThomas Gleixner <tglx@linutronix.de>
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- 24 6月, 2009 2 次提交
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由 Len Brown 提交于
drivers/acpi/processor_idle.c:1162: warning: unused variable ‘entry’ Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Zhao Yakui 提交于
Now whether the ACPI processor proc I/F is registered depends on the CONFIG_PROC. It had better depend on the CONFIG_ACPI_PROCFS. When the CONFIG_ACPI_PROCFS is unset in kernel configuration, the ACPI processor proc I/F won't be registered. Signed-off-by: NZhao Yakui <yakui.zhao@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 18 6月, 2009 1 次提交
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由 Len Brown 提交于
cosmetic only. The lapic_timer workaround routines are specific to the lapic_timer, and are not acpi-generic. old: acpi_timer_check_state() acpi_propagate_timer_broadcast() acpi_state_timer_broadcast() new: lapic_timer_check_state() lapic_timer_propagate_broadcast() lapic_timer_state_broadcast() also, simplify the code in acpi_processor_power_verify() so that lapic_timer_check_state() is simply called from one place for all valid C-states, including C1. Signed-off-by: NLen Brown <len.brown@intel.com>
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- 28 5月, 2009 1 次提交
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由 Pallipadi, Venkatesh 提交于
ARB_DISABLE is a NOP on all of the recent Intel platforms. For such platforms, reduce contention on c3_lock by skipping the fake ARB_DISABLE. Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 27 5月, 2009 2 次提交
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由 Shaohua Li 提交于
When AMD C1E is enabled, local APIC timer will stop even in C1. To avoid suspend/resume hang, this patch removes C1 and replace it with a cpu_relax() in suspend/resume path. This hasn't any impact in runtime path. http://bugzilla.kernel.org/show_bug.cgi?id=13233 [ impact: avoid suspend/resume hang in AMD CPU with C1E enabled ] Tested-by: NDmitry Lyzhyn <thisistempbox@yahoo.com> Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Shaohua Li 提交于
When AMD C1E is enabled, local APIC timer will stop even in C1. This patch uses broadcast IPI to replace local APIC timer in C1. http://bugzilla.kernel.org/show_bug.cgi?id=13233 [ impact: avoid boot hang in AMD CPU with C1E enabled ] Tested-by: NDmitry Lyzhyn <thisistempbox@yahoo.com> Signed-off-by: NShaohua Li <shaohua.li@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 16 5月, 2009 3 次提交
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由 Len Brown 提交于
Processor idle power states C2 and C3 stop the TSC on many machines. Linux recognizes this situation and marks the TSC as unstable: Marking TSC unstable due to TSC halts in idle But if those same machines are booted with "processor.max_cstate=1", then there is no need to validate C2 and C3, and no need to disable the TSC, which can be reliably used as a clocksource. Signed-off-by: NLen Brown <len.brown@intel.com> Acked-by: NThomas Gleixner <tglx@linutronix.de>
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由 Len Brown 提交于
A previous 2.6.30 patch, a71e4917, (ACPI: idle: mark_tsc_unstable() at init-time, not run-time) erroneously disabled the TSC on systems that did not actually have valid deep C-states. Move the check after the deep-C-states are validated, via new helper, tsc_check_state(), hich replaces tsc_halts_in_c(). Signed-off-by: NLen Brown <len.brown@intel.com> Acked-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Acked-by: NThomas Gleixner <tglx@linutronix.de> Tested-by: NFrans Pop <elendil@planet.nl>
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由 Len Brown 提交于
In 2.6.29, 31878dd8 "ACPI: remove BM_RLD access from idle entry path" moved BM_RLD initialization to init-time from run time. But we discovered that some BIOS do not restore BM_RLD after suspend, causing device errors on C3 and C4 after resume. So now the kernel restores BM_RLD. http://bugzilla.kernel.org/show_bug.cgi?id=13032Signed-off-by: NLen Brown <len.brown@intel.com>
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- 15 5月, 2009 2 次提交
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由 Ingo Molnar 提交于
We had a disable/enable around acpi_idle_do_entry() due to an erratum in an early prototype CPU i had access to. That erratum has been fixed in the BIOS so remove the quirk. The quirk also kept us from profiling interrupts that hit the ACPI idle instruction - so this is an improvement as well, beyond a cleanup and a micro-optimization. [ Impact: improve profiling scope, cleanup, micro-optimization ] Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> LKML-Reference: <new-submission> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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由 Peter Zijlstra 提交于
The current disable/enable mechanism is: token = hw_perf_save_disable(); ... /* do bits */ ... hw_perf_restore(token); This works well, provided that the use nests properly. Except we don't. x86 NMI/INT throttling has non-nested use of this, breaking things. Therefore provide a reference counter disable/enable interface, where the first disable disables the hardware, and the last enable enables the hardware again. [ Impact: refactor, simplify the PMU disable/enable logic ] Signed-off-by: NPeter Zijlstra <a.p.zijlstra@chello.nl> Cc: Paul Mackerras <paulus@samba.org> Cc: Corey Ashford <cjashfor@linux.vnet.ibm.com> LKML-Reference: <new-submission> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 24 4月, 2009 2 次提交
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由 Len Brown 提交于
As processor.max_cstate is an init-time-only modparam, sanity checking it at init-time is sufficient. http://bugzilla.kernel.org/show_bug.cgi?id=13142Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Len Brown 提交于
Linux tells ICH4 users that they can (manually) invoke "hpet=force" to enable the undocumented ICH-4M HPET. The HPET becomes available for both clocksource and clockevents. But as of ff69f2bb (acpi: fix of pmtimer overflow that make Cx states time incorrect) the HPET may be used via clocksource for idle accounting, and hpet=force on an ICH4 box hangs boot. It turns out that touching the MMIO HPET withing the ARB_DIS part of C3 will hang the hardware. The fix is to simply move the timer access outside the ARB_DIS region. This is a no-op on modern hardware because ARB_DIS is no longer used. http://bugzilla.kernel.org/show_bug.cgi?id=13087Acked-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 23 4月, 2009 2 次提交
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由 Len Brown 提交于
Linux-2.6.29 deleted the legacy ACPI idle handler, leaving the CPU_IDLE handler, which does not track bus master activity. So delete the unused bm_activity field -- it is confusing to print an always zero value. This patch could break programs that parse /proc/acpi/processor/*/power, since it deletes this line from that file: bus master activity: 00000000 http://bugzilla.kernel.org/show_bug.cgi?id=13145 is not fixed by this patch, but provoked this patch. Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Len Brown 提交于
The c2 and c3 idle handlers check tsc_halts_in_c() after every time they return from idle. Um, when?:-) Move this check to init-time to remove the unnecessary run-time overhead, and also to have the check complete before the first entry into the idle handler. ff69f2bb (acpi: fix of pmtimer overflow that make Cx states time incorrect) replaced the hard-coded use of the PM-timer inside idle, with ktime_get_readl(), which possibly uses the TSC -- so it is now especially prudent to detect a broken TSC before entering idle. http://bugzilla.kernel.org/show_bug.cgi?id=13087Signed-off-by: NLen Brown <len.brown@intel.com>
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- 08 4月, 2009 1 次提交
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由 Venkatesh Pallipadi 提交于
Add support for Always Running APIC timer, CPUID_0x6_EAX_Bit2. This bit means the APIC timer continues to run even when CPU is in deep C-states. The advantage is that we can use LAPIC timer on these CPUs always, and there is no need for "slow to read and program" external timers (HPET/PIT) and the timer broadcast logic and related code in C-state entry and exit. Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Acked-by: NH. Peter Anvin <hpa@zytor.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 04 4月, 2009 1 次提交
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由 Thomas Renninger 提交于
The recent ACPICA patch (ACPICA: FADT: Favor 32-bit register addresses for compatibility) makes machine to use the right FADT HW addresses and C-states now work fine. http://bugzilla.kernel.org/show_bug.cgi?id=8246Signed-off-by: NThomas Renninger <trenn@suse.de> Tested-by: NMark Doughty <me@markdoughty.co.uk> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 27 3月, 2009 2 次提交
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由 Bob Moore 提交于
Rename acpi_get_register and acpi_set_register to clarify the purpose of these functions. New names are acpi_read_bit_register and acpi_write_bit_register. Signed-off-by: NBob Moore <robert.moore@intel.com> Signed-off-by: NLin Ming <ming.m.lin@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Bob Moore 提交于
Removed locking for reads from the ACPI bit registers in PM1 Status, Enable, Control, and PM2 Control. The lock is not required when reading the single-bit registers. The acpi_get_register_unlocked function is no longer needed and has been removed. This will improve performance for reads on these registers. ACPICA BZ 760. http://www.acpica.org/bugzilla/show_bug.cgi?id=760Signed-off-by: NBob Moore <robert.moore@intel.com> Signed-off-by: NLin Ming <ming.m.lin@intel.com> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 17 3月, 2009 1 次提交
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由 alex.shi 提交于
We found Cx states time abnormal in our some of machines which have 16 LCPUs, the C0 take too many time while system is really idle when kernel enabled tickless and highres. powertop output is below: PowerTOP version 1.9 (C) 2007 Intel Corporation Cn Avg residency P-states (frequencies) C0 (cpu running) (40.5%) 2.53 Ghz 0.0% C1 0.0ms ( 0.0%) 2.53 Ghz 0.0% C2 128.8ms (59.5%) 2.40 Ghz 0.0% 1.60 Ghz 100.0% Wakeups-from-idle per second : 4.7 interval: 20.0s no ACPI power usage estimate available Top causes for wakeups: 41.4% ( 24.9) <interrupt> : extra timer interrupt 20.2% ( 12.2) <kernel core> : usb_hcd_poll_rh_status (rh_timer_func) After tacking detailed for this issue, Yakui and I find it is due to 24 bit PM timer overflows when some of cpu sleep more than 4 seconds. With tickless kernel, the CPU want to sleep as much as possible when system idle. But the Cx sleep time are recorded by pmtimer which length is determined by BIOS. The current Cx time was gotten in the following function from driver/acpi/processor_idle.c: static inline u32 ticks_elapsed(u32 t1, u32 t2) { if (t2 >= t1) return (t2 - t1); else if (!(acpi_gbl_FADT.flags & ACPI_FADT_32BIT_TIMER)) return (((0x00FFFFFF - t1) + t2) & 0x00FFFFFF); else return ((0xFFFFFFFF - t1) + t2); } If pmtimer is 24 bits and it take 5 seconds from t1 to t2, in above function, just about 1 seconds ticks was recorded. So the Cx time will be reduced about 4 seconds. and this is why we see above powertop output. To resolve this problem, Yakui and I use ktime_get() to record the Cx states time instead of PM timer as the following patch. the patch was tested with i386/x86_64 modes on several platforms. Acked-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Tested-by: NAlex Shi <alex.shi@intel.com> Signed-off-by: NAlex Shi <alex.shi@intel.com> Signed-off-by: NYakui.zhao <yakui.zhao@intel.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLen Brown <len.brown@intel.com>
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- 16 2月, 2009 1 次提交
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由 Ingo Molnar 提交于
Fix merge error in drivers/acpi/processor_idle.c. This resulted in non-working perfcounters on certain Nehalem systems. Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 07 2月, 2009 1 次提交
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由 Len Brown 提交于
CPU_IDLE=y has been default for ACPI=y since Nov-2007, and has shipped in many distributions since then. Here we delete the CPU_IDLE=n ACPI idle code, since nobody should be using it, and we don't want to maintain two versions. Signed-off-by: NLen Brown <len.brown@intel.com>
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- 29 1月, 2009 2 次提交
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由 Len Brown 提交于
It is true that BM_RLD needs to be set to enable bus master activity to wake an older chipset (eg PIIX4) from C3. This is contrary to the erroneous wording the ACPI 2.0, 3.0 specifications that suggests that BM_RLD is an indicator rather than a control bit. ACPI 1.0's correct wording should be restored in ACPI 4.0: http://www.acpica.org/bugzilla/show_bug.cgi?id=689 But the kernel should not have to clear BM_RLD when entering a non C3-type state just to set it again when entering a C3-type C-state. We should be able to set BM_RLD at boot time and leave it alone -- removing the overhead of accessing this IO register from the idle entry path. Signed-off-by: NLen Brown <len.brown@intel.com>
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由 Len Brown 提交于
PM1a_STS and PM1b_STS are twins that get OR'd together on reads, and all writes are repeated to both. The fields in PM1x_STS are single bits only, there are no multi-bit fields. So it is not necessary to lock PM1x_STS reads against writes because it is impossible to read an intermediate value of a single bit. It will either be 0 or 1, even if a write is in progress during the read. Reads are asynchronous to writes no matter if a lock is used or not. Signed-off-by: NLen Brown <len.brown@intel.com>
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- 07 1月, 2009 1 次提交
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由 Russell King 提交于
While looking at reducing the amount of architecture namespace pollution in the generic kernel, I found that asm/irq.h is included in the vast majority of compilations on ARM (around 650 files.) Since asm/irq.h includes a sub-architecture include file on ARM, this causes a negative impact on the ccache's ability to re-use the build results from other sub-architectures, so we have a desire to reduce the dependencies on asm/irq.h. It turns out that a major cause of this is the needless include of linux/hardirq.h into asm-generic/local.h. The patch below removes this include, resulting in some 250 to 300 files (around half) of the kernel then omitting asm/irq.h. My test builds still succeed, provided two ARM files are fixed (arch/arm/kernel/traps.c and arch/arm/mm/fault.c) - so there may be negative impacts for this on other architectures. Note that x86 does not include asm/irq.h nor linux/hardirq.h in its asm/local.h, so this patch can be viewed as bringing the generic version into line with the x86 version. [kosaki.motohiro@jp.fujitsu.com: add #include <linux/irqflags.h> to acpi/processor_idle.c] [adobriyan@gmail.com: fix sparc64] Signed-off-by: NRussell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: NKOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: NAndrew Morton <akpm@linux-foundation.org> Signed-off-by: NLinus Torvalds <torvalds@linux-foundation.org>
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- 17 12月, 2008 1 次提交
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由 Venki Pallipadi 提交于
Impact: reward non-stop TSCs with good TSC-based clocksources, etc. Add support for CPUID_0x80000007_Bit8 on Intel CPUs as well. This bit means that the TSC is invariant with C/P/T states and always runs at constant frequency. With Intel CPUs, we have 3 classes * CPUs where TSC runs at constant rate and does not stop n C-states * CPUs where TSC runs at constant rate, but will stop in deep C-states * CPUs where TSC rate will vary based on P/T-states and TSC will stop in deep C-states. To cover these 3, one feature bit (CONSTANT_TSC) is not enough. So, add a second bit (NONSTOP_TSC). CONSTANT_TSC indicates that the TSC runs at constant frequency irrespective of P/T-states, and NONSTOP_TSC indicates that TSC does not stop in deep C-states. CPUID_0x8000000_Bit8 indicates both these feature bit can be set. We still have CONSTANT_TSC _set_ and NONSTOP_TSC _not_set_ on some older Intel CPUs, based on model checks. We can use TSC on such CPUs for time, as long as those CPUs do not support/enter deep C-states. Signed-off-by: NVenkatesh Pallipadi <venkatesh.pallipadi@intel.com> Signed-off-by: NIngo Molnar <mingo@elte.hu>
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- 11 12月, 2008 1 次提交
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由 Ingo Molnar 提交于
Impact: cleanup Rename them to better match up the usual IRQ disable/enable APIs: hw_perf_disable_all() => hw_perf_save_disable() hw_perf_restore_ctrl() => hw_perf_restore() Signed-off-by: NIngo Molnar <mingo@elte.hu>
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