提交 c6f9fa88 编写于 作者: O Olof Johansson

Merge tag 'samsung-dt-4.21-2' of...

Merge tag 'samsung-dt-4.21-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/late

Samsung DTS ARM changes for v4.21, part 2

1. Add missing CPUs in cooling maps for Odroid X2 (missed in previous
   round of fixups).
2. Fix clock configuration in audio subsystem on Odroid XU3/XU4.

* tag 'samsung-dt-4.21-2' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  ARM: dts: exynos: Specify I2S assigned clocks in proper node
  ARM: dts: exynos: Add missing CPUs in cooling maps for Odroid X2
  ARM: dts: exynos: remove display-port node from Arndale
  ARM: dts: exynos: Add opp-suspend to DMC and leftbus devfreq OPPs on Exynos4
  ARM: dts: s5pv210: Add s5p-jpeg codec node.
  ARM: dts: exynos: Use Samsung SoC specific compatible for DWC2 module
  ARM: dts: exynos: Add all CPUs in cooling maps
  ARM: dts: exynos: Clarify comment explaining purpose of Odroid XU3 DTSI
  ARM: dts: exynos: Add pin configuration for SD write protect on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Update maximum frequency for eMMC to 200MHz on Odroid XU3/XU4
  ARM: dts: exynos: Update maximum frequency for SD card to 200MHz on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Fix LDO13 min values on Odroid XU3/XU4/HC1
  ARM: dts: exynos: Add UHS-I bus speed support to Odroid XU3/XU4/HC1
  ARM: dts: exynos: Add missing clocks to RTC node for Arndale board
  ARM: dts: exynos: Add compatible for s5m8767 clocks node on Itop Core
  ARM: dts: exynos: Add compatible for s2mps11 clocks node on Exynos542x
Signed-off-by: NOlof Johansson <olof@lixom.net>
...@@ -36,11 +36,13 @@ cpu_thermal: cpu-thermal { ...@@ -36,11 +36,13 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 500MHz */ /* Corresponds to 500MHz */
cooling-device = <&cpu0 5 5>; cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
}; };
map1 { map1 {
/* Corresponds to 200MHz */ /* Corresponds to 200MHz */
cooling-device = <&cpu0 8 8>; cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
}; };
}; };
}; };
......
...@@ -121,11 +121,13 @@ cpu_thermal: cpu-thermal { ...@@ -121,11 +121,13 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Correspond to 500MHz at freq_table */ /* Correspond to 500MHz at freq_table */
cooling-device = <&cpu0 5 5>; cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
}; };
map1 { map1 {
/* Correspond to 200MHz at freq_table */ /* Correspond to 200MHz at freq_table */
cooling-device = <&cpu0 8 8>; cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
}; };
}; };
}; };
......
...@@ -116,11 +116,13 @@ cpu_thermal: cpu-thermal { ...@@ -116,11 +116,13 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 500MHz */ /* Corresponds to 500MHz */
cooling-device = <&cpu0 5 5>; cooling-device = <&cpu0 5 5>,
<&cpu1 5 5>;
}; };
map1 { map1 {
/* Corresponds to 200MHz */ /* Corresponds to 200MHz */
cooling-device = <&cpu0 8 8>; cooling-device = <&cpu0 8 8>,
<&cpu1 8 8>;
}; };
}; };
}; };
......
...@@ -357,7 +357,7 @@ sysmmu_fimd0: sysmmu@11e20000 { ...@@ -357,7 +357,7 @@ sysmmu_fimd0: sysmmu@11e20000 {
}; };
hsotg: hsotg@12480000 { hsotg: hsotg@12480000 {
compatible = "snps,dwc2"; compatible = "samsung,s3c6400-hsotg", "snps,dwc2";
reg = <0x12480000 0x20000>; reg = <0x12480000 0x20000>;
interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&cmu CLK_USBOTG>; clocks = <&cmu CLK_USBOTG>;
......
...@@ -138,11 +138,11 @@ cpu_thermal: cpu-thermal { ...@@ -138,11 +138,11 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 800MHz at freq_table */ /* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 2 2>; cooling-device = <&cpu0 2 2>, <&cpu1 2 2>;
}; };
map1 { map1 {
/* Corresponds to 200MHz at freq_table */ /* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 4 4>; cooling-device = <&cpu0 4 4>, <&cpu1 4 4>;
}; };
}; };
}; };
......
...@@ -51,7 +51,7 @@ cpu0: cpu@900 { ...@@ -51,7 +51,7 @@ cpu0: cpu@900 {
#cooling-cells = <2>; /* min followed by max */ #cooling-cells = <2>; /* min followed by max */
}; };
cpu@901 { cpu1: cpu@901 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0x901>; reg = <0x901>;
...@@ -298,6 +298,7 @@ opp-267000000 { ...@@ -298,6 +298,7 @@ opp-267000000 {
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1150000>; opp-microvolt = <1150000>;
opp-suspend;
}; };
}; };
...@@ -367,6 +368,7 @@ opp-160000000 { ...@@ -367,6 +368,7 @@ opp-160000000 {
}; };
opp-200000000 { opp-200000000 {
opp-hz = /bits/ 64 <200000000>; opp-hz = /bits/ 64 <200000000>;
opp-suspend;
}; };
}; };
}; };
......
...@@ -45,11 +45,15 @@ cpu_thermal: cpu-thermal { ...@@ -45,11 +45,15 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 800MHz at freq_table */ /* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>; cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
}; };
map1 { map1 {
/* Corresponds to 200MHz at freq_table */ /* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>; cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
}; };
}; };
}; };
...@@ -446,6 +450,7 @@ buck9_reg: BUCK9 { ...@@ -446,6 +450,7 @@ buck9_reg: BUCK9 {
}; };
s5m8767_osc: clocks { s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "s5m8767_ap", clock-output-names = "s5m8767_ap",
"s5m8767_cp", "s5m8767_bt"; "s5m8767_cp", "s5m8767_bt";
......
...@@ -267,11 +267,15 @@ cpu_thermal: cpu-thermal { ...@@ -267,11 +267,15 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 800MHz at freq_table */ /* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>; cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
}; };
map1 { map1 {
/* Corresponds to 200MHz at freq_table */ /* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>; cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
}; };
}; };
}; };
......
...@@ -72,11 +72,15 @@ cpu_thermal: cpu-thermal { ...@@ -72,11 +72,15 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
cooling_map0: map0 { cooling_map0: map0 {
/* Corresponds to 800MHz at freq_table */ /* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 7 7>; cooling-device = <&cpu0 7 7>, <&cpu1 7 7>,
<&cpu2 7 7>, <&cpu3 7 7>;
}; };
cooling_map1: map1 { cooling_map1: map1 {
/* Corresponds to 200MHz at freq_table */ /* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 13 13>; cooling-device = <&cpu0 13 13>,
<&cpu1 13 13>,
<&cpu2 13 13>,
<&cpu3 13 13>;
}; };
}; };
}; };
......
...@@ -45,24 +45,22 @@ cpu_thermal: cpu-thermal { ...@@ -45,24 +45,22 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu_alert1>; trip = <&cpu_alert1>;
cooling-device = <&cpu0 9 9>; cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
<&cpu2 9 9>, <&cpu3 9 9>,
<&fan0 1 2>;
}; };
map1 { map1 {
trip = <&cpu_alert2>; trip = <&cpu_alert2>;
cooling-device = <&cpu0 15 15>; cooling-device = <&cpu0 15 15>,
<&cpu1 15 15>,
<&cpu2 15 15>,
<&cpu3 15 15>,
<&fan0 2 3>;
}; };
map2 { map2 {
trip = <&cpu_alert0>; trip = <&cpu_alert0>;
cooling-device = <&fan0 0 1>; cooling-device = <&fan0 0 1>;
}; };
map3 {
trip = <&cpu_alert1>;
cooling-device = <&fan0 1 2>;
};
map4 {
trip = <&cpu_alert2>;
cooling-device = <&fan0 2 3>;
};
}; };
}; };
}; };
......
...@@ -30,9 +30,11 @@ opp-1704000000 { ...@@ -30,9 +30,11 @@ opp-1704000000 {
}; };
&cooling_map0 { &cooling_map0 {
cooling-device = <&cpu0 9 9>; cooling-device = <&cpu0 9 9>, <&cpu1 9 9>,
<&cpu2 9 9>, <&cpu3 9 9>;
}; };
&cooling_map1 { &cooling_map1 {
cooling-device = <&cpu0 15 15>; cooling-device = <&cpu0 15 15>, <&cpu1 15 15>,
<&cpu2 15 15>, <&cpu3 15 15>;
}; };
...@@ -45,7 +45,7 @@ cpu0: cpu@a00 { ...@@ -45,7 +45,7 @@ cpu0: cpu@a00 {
#cooling-cells = <2>; /* min followed by max */ #cooling-cells = <2>; /* min followed by max */
}; };
cpu@a01 { cpu1: cpu@a01 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0xA01>; reg = <0xA01>;
...@@ -55,7 +55,7 @@ cpu@a01 { ...@@ -55,7 +55,7 @@ cpu@a01 {
#cooling-cells = <2>; /* min followed by max */ #cooling-cells = <2>; /* min followed by max */
}; };
cpu@a02 { cpu2: cpu@a02 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0xA02>; reg = <0xA02>;
...@@ -65,7 +65,7 @@ cpu@a02 { ...@@ -65,7 +65,7 @@ cpu@a02 {
#cooling-cells = <2>; /* min followed by max */ #cooling-cells = <2>; /* min followed by max */
}; };
cpu@a03 { cpu3: cpu@a03 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a9"; compatible = "arm,cortex-a9";
reg = <0xA03>; reg = <0xA03>;
...@@ -432,6 +432,7 @@ opp-267000000 { ...@@ -432,6 +432,7 @@ opp-267000000 {
opp-400000000 { opp-400000000 {
opp-hz = /bits/ 64 <400000000>; opp-hz = /bits/ 64 <400000000>;
opp-microvolt = <1050000>; opp-microvolt = <1050000>;
opp-suspend;
}; };
}; };
...@@ -520,6 +521,7 @@ opp-160000000 { ...@@ -520,6 +521,7 @@ opp-160000000 {
opp-200000000 { opp-200000000 {
opp-hz = /bits/ 64 <200000000>; opp-hz = /bits/ 64 <200000000>;
opp-microvolt = <1000000>; opp-microvolt = <1000000>;
opp-suspend;
}; };
}; };
......
...@@ -10,6 +10,7 @@ ...@@ -10,6 +10,7 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/irq.h> #include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/input/input.h> #include <dt-bindings/input/input.h>
#include <dt-bindings/clock/samsung,s2mps11.h>
#include "exynos5250.dtsi" #include "exynos5250.dtsi"
/ { / {
...@@ -180,31 +181,6 @@ bridge_out_ep: endpoint { ...@@ -180,31 +181,6 @@ bridge_out_ep: endpoint {
}; };
}; };
&dp {
status = "okay";
samsung,color-space = <0>;
samsung,color-depth = <1>;
samsung,link-rate = <0x0a>;
samsung,lane-count = <4>;
display-timings {
native-mode = <&timing0>;
timing0: timing {
/* 2560x1600 DP panel */
clock-frequency = <50000>;
hactive = <2560>;
vactive = <1600>;
hfront-porch = <48>;
hback-porch = <80>;
hsync-len = <32>;
vback-porch = <16>;
vfront-porch = <8>;
vsync-len = <6>;
};
};
};
&fimd { &fimd {
status = "okay"; status = "okay";
}; };
...@@ -264,6 +240,12 @@ s5m8767_pmic@66 { ...@@ -264,6 +240,12 @@ s5m8767_pmic@66 {
<&gpx2 4 GPIO_ACTIVE_HIGH>, <&gpx2 4 GPIO_ACTIVE_HIGH>,
<&gpx2 5 GPIO_ACTIVE_HIGH>; <&gpx2 5 GPIO_ACTIVE_HIGH>;
s5m8767_osc: clocks {
compatible = "samsung,s5m8767-clk";
#clock-cells = <1>;
clock-output-names = "s5m8767_ap", "unused1", "unused2";
};
regulators { regulators {
ldo1_reg: LDO1 { ldo1_reg: LDO1 {
regulator-name = "VDD_ALIVE_1.0V"; regulator-name = "VDD_ALIVE_1.0V";
...@@ -601,6 +583,8 @@ s5m8767_irq: s5m8767-irq { ...@@ -601,6 +583,8 @@ s5m8767_irq: s5m8767-irq {
}; };
&rtc { &rtc {
clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
clock-names = "rtc", "rtc_src";
status = "okay"; status = "okay";
}; };
......
...@@ -59,7 +59,7 @@ cpu0: cpu@0 { ...@@ -59,7 +59,7 @@ cpu0: cpu@0 {
operating-points-v2 = <&cpu0_opp_table>; operating-points-v2 = <&cpu0_opp_table>;
#cooling-cells = <2>; /* min followed by max */ #cooling-cells = <2>; /* min followed by max */
}; };
cpu@1 { cpu1: cpu@1 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a15"; compatible = "arm,cortex-a15";
reg = <1>; reg = <1>;
...@@ -1087,11 +1087,12 @@ cpu_thermal: cpu-thermal { ...@@ -1087,11 +1087,12 @@ cpu_thermal: cpu-thermal {
cooling-maps { cooling-maps {
map0 { map0 {
/* Corresponds to 800MHz at freq_table */ /* Corresponds to 800MHz at freq_table */
cooling-device = <&cpu0 9 9>; cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
}; };
map1 { map1 {
/* Corresponds to 200MHz at freq_table */ /* Corresponds to 200MHz at freq_table */
cooling-device = <&cpu0 15 15>; cooling-device = <&cpu0 15 15>,
<&cpu1 15 15>;
}; };
}; };
}; };
......
...@@ -89,6 +89,7 @@ s2mps11_pmic@66 { ...@@ -89,6 +89,7 @@ s2mps11_pmic@66 {
pinctrl-0 = <&s2mps11_irq>; pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks { s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "s2mps11_ap", clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt"; "s2mps11_cp", "s2mps11_bt";
......
...@@ -289,6 +289,13 @@ sd2_bus4: sd2-bus-width4 { ...@@ -289,6 +289,13 @@ sd2_bus4: sd2-bus-width4 {
samsung,pin-pud = <EXYNOS_PIN_PULL_UP>; samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>; samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
}; };
sd2_wp: sd2-wp {
samsung,pins = "gpc4-0";
samsung,pin-function = <EXYNOS_PIN_FUNC_2>;
samsung,pin-pud = <EXYNOS_PIN_PULL_DOWN>;
samsung,pin-drv = <EXYNOS5420_PIN_DRV_LV4>;
};
}; };
&pinctrl_2 { &pinctrl_2 {
......
...@@ -141,6 +141,7 @@ s2mps11_pmic@66 { ...@@ -141,6 +141,7 @@ s2mps11_pmic@66 {
reg = <0x66>; reg = <0x66>;
s2mps11_osc: clocks { s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "s2mps11_ap", clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt"; "s2mps11_cp", "s2mps11_bt";
......
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Hardkernel Odroid XU3/XU4/HC1 boards core device tree source * Hardkernel Odroid XU3/XU3-Lite/XU4/HC1 boards core device tree source
* *
* Copyright (c) 2017 Marek Szyprowski * Copyright (c) 2017 Marek Szyprowski
* Copyright (c) 2013-2017 Samsung Electronics Co., Ltd. * Copyright (c) 2013-2017 Samsung Electronics Co., Ltd.
...@@ -141,6 +141,7 @@ s2mps11_pmic@66 { ...@@ -141,6 +141,7 @@ s2mps11_pmic@66 {
pinctrl-0 = <&s2mps11_irq>; pinctrl-0 = <&s2mps11_irq>;
s2mps11_osc: clocks { s2mps11_osc: clocks {
compatible = "samsung,s2mps11-clk";
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "s2mps11_ap", clock-output-names = "s2mps11_ap",
"s2mps11_cp", "s2mps11_bt"; "s2mps11_cp", "s2mps11_bt";
...@@ -231,7 +232,7 @@ ldo12_reg: LDO12 { ...@@ -231,7 +232,7 @@ ldo12_reg: LDO12 {
ldo13_reg: LDO13 { ldo13_reg: LDO13 {
regulator-name = "vddq_mmc2"; regulator-name = "vddq_mmc2";
regulator-min-microvolt = <2800000>; regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <2800000>; regulator-max-microvolt = <2800000>;
}; };
...@@ -498,11 +499,15 @@ &mmc_2 { ...@@ -498,11 +499,15 @@ &mmc_2 {
samsung,dw-mshc-sdr-timing = <0 4>; samsung,dw-mshc-sdr-timing = <0 4>;
samsung,dw-mshc-ddr-timing = <0 2>; samsung,dw-mshc-ddr-timing = <0 2>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_bus1 &sd2_bus4>; pinctrl-0 = <&sd2_clk &sd2_cmd &sd2_cd &sd2_wp &sd2_bus1 &sd2_bus4>;
bus-width = <4>; bus-width = <4>;
cap-sd-highspeed; cap-sd-highspeed;
max-frequency = <200000000>;
vmmc-supply = <&ldo19_reg>; vmmc-supply = <&ldo19_reg>;
vqmmc-supply = <&ldo13_reg>; vqmmc-supply = <&ldo13_reg>;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
}; };
&nocp_mem0_0 { &nocp_mem0_0 {
......
...@@ -56,24 +56,30 @@ cooling-maps { ...@@ -56,24 +56,30 @@ cooling-maps {
*/ */
map0 { map0 {
trip = <&cpu0_alert0>; trip = <&cpu0_alert0>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
}; <&cpu1 0 2>,
map1 { <&cpu2 0 2>,
trip = <&cpu0_alert0>; <&cpu3 0 2>,
cooling-device = <&cpu4 0 2>; <&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
/* /*
* When reaching cpu0_alert1, reduce CPU * When reaching cpu0_alert1, reduce CPU
* further, down to 600 MHz (12 steps for big, * further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE). * 7 steps for LITTLE).
*/ */
map2 { map1 {
trip = <&cpu0_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu0_alert1>; trip = <&cpu0_alert1>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -99,19 +105,25 @@ cpu1_crit0: cpu-crit-0 { ...@@ -99,19 +105,25 @@ cpu1_crit0: cpu-crit-0 {
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu1_alert0>; trip = <&cpu1_alert0>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map1 { map1 {
trip = <&cpu1_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu1_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu1_alert1>; trip = <&cpu1_alert1>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -137,19 +149,25 @@ cpu2_crit0: cpu-crit-0 { ...@@ -137,19 +149,25 @@ cpu2_crit0: cpu-crit-0 {
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu2_alert0>; trip = <&cpu2_alert0>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map1 { map1 {
trip = <&cpu2_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu2_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu2_alert1>; trip = <&cpu2_alert1>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -175,19 +193,25 @@ cpu3_crit0: cpu-crit-0 { ...@@ -175,19 +193,25 @@ cpu3_crit0: cpu-crit-0 {
cooling-maps { cooling-maps {
map0 { map0 {
trip = <&cpu3_alert0>; trip = <&cpu3_alert0>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map1 { map1 {
trip = <&cpu3_alert0>;
cooling-device = <&cpu4 0 2>;
};
map2 {
trip = <&cpu3_alert1>;
cooling-device = <&cpu0 3 7>;
};
map3 {
trip = <&cpu3_alert1>; trip = <&cpu3_alert1>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
......
...@@ -26,8 +26,7 @@ sound: sound { ...@@ -26,8 +26,7 @@ sound: sound {
"Speakers", "SPKL", "Speakers", "SPKL",
"Speakers", "SPKR"; "Speakers", "SPKR";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_AUDSS>,
...@@ -36,8 +35,7 @@ sound: sound { ...@@ -36,8 +35,7 @@ sound: sound {
<&clock_audss EXYNOS_DOUT_AUD_BUS>, <&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>; <&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>, <&clock CLK_MAU_EPLL>,
...@@ -48,7 +46,6 @@ sound: sound { ...@@ -48,7 +46,6 @@ sound: sound {
<0>, <0>,
<0>, <0>,
<0>, <0>,
<0>,
<196608001>, <196608001>,
<(196608002 / 2)>, <(196608002 / 2)>,
<196608000>; <196608000>;
...@@ -84,4 +81,6 @@ max98090: max98090@10 { ...@@ -84,4 +81,6 @@ max98090: max98090@10 {
&i2s0 { &i2s0 {
status = "okay"; status = "okay";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
}; };
// SPDX-License-Identifier: GPL-2.0 // SPDX-License-Identifier: GPL-2.0
/* /*
* Hardkernel Odroid XU3 board device tree source * Hardkernel Odroid XU3/XU3-Lite/XU4 boards common device tree source
* *
* Copyright (c) 2013 Samsung Electronics Co., Ltd. * Copyright (c) 2013 Samsung Electronics Co., Ltd.
* http://www.samsung.com * http://www.samsung.com
...@@ -113,24 +113,30 @@ map2 { ...@@ -113,24 +113,30 @@ map2 {
*/ */
map3 { map3 {
trip = <&cpu0_alert3>; trip = <&cpu0_alert3>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
}; <&cpu1 0 2>,
map4 { <&cpu2 0 2>,
trip = <&cpu0_alert3>; <&cpu3 0 2>,
cooling-device = <&cpu4 0 2>; <&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
/* /*
* When reaching cpu0_alert4, reduce CPU * When reaching cpu0_alert4, reduce CPU
* further, down to 600 MHz (12 steps for big, * further, down to 600 MHz (12 steps for big,
* 7 steps for LITTLE). * 7 steps for LITTLE).
*/ */
map5 { map4 {
trip = <&cpu0_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu0_alert4>; trip = <&cpu0_alert4>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -185,19 +191,25 @@ map2 { ...@@ -185,19 +191,25 @@ map2 {
}; };
map3 { map3 {
trip = <&cpu1_alert3>; trip = <&cpu1_alert3>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map4 { map4 {
trip = <&cpu1_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu1_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu1_alert4>; trip = <&cpu1_alert4>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -252,19 +264,25 @@ map2 { ...@@ -252,19 +264,25 @@ map2 {
}; };
map3 { map3 {
trip = <&cpu2_alert3>; trip = <&cpu2_alert3>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map4 { map4 {
trip = <&cpu2_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu2_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu2_alert4>; trip = <&cpu2_alert4>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -319,19 +337,25 @@ map2 { ...@@ -319,19 +337,25 @@ map2 {
}; };
map3 { map3 {
trip = <&cpu3_alert3>; trip = <&cpu3_alert3>;
cooling-device = <&cpu0 0 2>; cooling-device = <&cpu0 0 2>,
<&cpu1 0 2>,
<&cpu2 0 2>,
<&cpu3 0 2>,
<&cpu4 0 2>,
<&cpu5 0 2>,
<&cpu6 0 2>,
<&cpu7 0 2>;
}; };
map4 { map4 {
trip = <&cpu3_alert3>;
cooling-device = <&cpu4 0 2>;
};
map5 {
trip = <&cpu3_alert4>;
cooling-device = <&cpu0 3 7>;
};
map6 {
trip = <&cpu3_alert4>; trip = <&cpu3_alert4>;
cooling-device = <&cpu4 3 12>; cooling-device = <&cpu0 3 7>,
<&cpu1 3 7>,
<&cpu2 3 7>,
<&cpu3 3 7>,
<&cpu4 3 12>,
<&cpu5 3 12>,
<&cpu6 3 12>,
<&cpu7 3 12>;
}; };
}; };
}; };
...@@ -392,6 +416,7 @@ &mmc_0 { ...@@ -392,6 +416,7 @@ &mmc_0 {
cap-mmc-highspeed; cap-mmc-highspeed;
mmc-hs200-1_8v; mmc-hs200-1_8v;
mmc-hs400-1_8v; mmc-hs400-1_8v;
max-frequency = <200000000>;
vmmc-supply = <&ldo18_reg>; vmmc-supply = <&ldo18_reg>;
vqmmc-supply = <&ldo3_reg>; vqmmc-supply = <&ldo3_reg>;
}; };
......
...@@ -33,8 +33,7 @@ sound: sound { ...@@ -33,8 +33,7 @@ sound: sound {
compatible = "samsung,odroid-xu3-audio"; compatible = "samsung,odroid-xu3-audio";
model = "Odroid-XU4"; model = "Odroid-XU4";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>, assigned-clocks = <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MOUT_USER_MAU_EPLL>, <&clock CLK_MOUT_USER_MAU_EPLL>,
<&clock_audss EXYNOS_MOUT_AUDSS>, <&clock_audss EXYNOS_MOUT_AUDSS>,
...@@ -43,8 +42,7 @@ sound: sound { ...@@ -43,8 +42,7 @@ sound: sound {
<&clock_audss EXYNOS_DOUT_AUD_BUS>, <&clock_audss EXYNOS_DOUT_AUD_BUS>,
<&clock_audss EXYNOS_DOUT_I2S>; <&clock_audss EXYNOS_DOUT_I2S>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>, assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
<&clock CLK_FOUT_EPLL>,
<&clock CLK_MOUT_EPLL>, <&clock CLK_MOUT_EPLL>,
<&clock CLK_MOUT_MAU_EPLL>, <&clock CLK_MOUT_MAU_EPLL>,
<&clock CLK_MAU_EPLL>, <&clock CLK_MAU_EPLL>,
...@@ -55,7 +53,6 @@ sound: sound { ...@@ -55,7 +53,6 @@ sound: sound {
<0>, <0>,
<0>, <0>,
<0>, <0>,
<0>,
<196608001>, <196608001>,
<(196608002 / 2)>, <(196608002 / 2)>,
<196608000>; <196608000>;
...@@ -79,6 +76,8 @@ &clock_audss { ...@@ -79,6 +76,8 @@ &clock_audss {
&i2s0 { &i2s0 {
status = "okay"; status = "okay";
assigned-clocks = <&i2s0 CLK_I2S_RCLK_SRC>;
assigned-clock-parents = <&clock_audss EXYNOS_SCLK_I2S>;
}; };
&pwm { &pwm {
......
...@@ -627,6 +627,15 @@ fimc2: fimc@fb400000 { ...@@ -627,6 +627,15 @@ fimc2: fimc@fb400000 {
samsung,lcd-wb; samsung,lcd-wb;
}; };
}; };
jpeg_codec: jpeg-codec@fb600000 {
compatible = "samsung,s5pv210-jpeg";
reg = <0xfb600000 0x1000>;
interrupt-parent = <&vic2>;
interrupts = <8>;
clocks = <&clocks CLK_JPEG>;
clock-names = "jpeg";
};
}; };
}; };
......
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