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b477dfba
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体验新版 GitCode,发现更多精彩内容 >>
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b477dfba
编写于
5月 16, 2009
作者:
R
Russell King
提交者:
Russell King
5月 16, 2009
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差异文件
Merge branch 'fixes-rc5' of
git://aeryn.fluff.org.uk/bjdooks/linux
上级
1406de8e
3ac19bb4
变更
8
隐藏空白更改
内联
并排
Showing
8 changed file
with
19 addition
and
20 deletion
+19
-20
arch/arm/mach-s3c2410/mach-bast.c
arch/arm/mach-s3c2410/mach-bast.c
+1
-2
arch/arm/nwfpe/fpa11.h
arch/arm/nwfpe/fpa11.h
+4
-0
arch/arm/nwfpe/fpa11_cprt.c
arch/arm/nwfpe/fpa11_cprt.c
+0
-4
arch/arm/nwfpe/softfloat.h
arch/arm/nwfpe/softfloat.h
+2
-0
arch/arm/plat-s3c/clock.c
arch/arm/plat-s3c/clock.c
+0
-2
arch/arm/plat-s3c24xx/dma.c
arch/arm/plat-s3c24xx/dma.c
+1
-1
arch/arm/plat-s3c64xx/gpiolib.c
arch/arm/plat-s3c64xx/gpiolib.c
+1
-1
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
+10
-10
未找到文件。
arch/arm/mach-s3c2410/mach-bast.c
浏览文件 @
b477dfba
...
...
@@ -588,8 +588,6 @@ static void __init bast_map_io(void)
s3c_device_nand
.
dev
.
platform_data
=
&
bast_nand_info
;
s3c_i2c0_set_platdata
(
&
bast_i2c_info
);
s3c24xx_init_io
(
bast_iodesc
,
ARRAY_SIZE
(
bast_iodesc
));
s3c24xx_init_clocks
(
0
);
s3c24xx_init_uarts
(
bast_uartcfgs
,
ARRAY_SIZE
(
bast_uartcfgs
));
...
...
@@ -602,6 +600,7 @@ static void __init bast_init(void)
sysdev_class_register
(
&
bast_pm_sysclass
);
sysdev_register
(
&
bast_pm_sysdev
);
s3c_i2c0_set_platdata
(
&
bast_i2c_info
);
s3c24xx_fb_set_platdata
(
&
bast_fb_info
);
platform_add_devices
(
bast_devices
,
ARRAY_SIZE
(
bast_devices
));
...
...
arch/arm/nwfpe/fpa11.h
浏览文件 @
b477dfba
...
...
@@ -114,4 +114,8 @@ extern unsigned int SingleCPDO(struct roundingData *roundData,
extern
unsigned
int
DoubleCPDO
(
struct
roundingData
*
roundData
,
const
unsigned
int
opcode
,
FPREG
*
rFd
);
/* extneded_cpdo.c */
extern
unsigned
int
ExtendedCPDO
(
struct
roundingData
*
roundData
,
const
unsigned
int
opcode
,
FPREG
*
rFd
);
#endif
arch/arm/nwfpe/fpa11_cprt.c
浏览文件 @
b477dfba
...
...
@@ -27,10 +27,6 @@
#include "fpmodule.inl"
#include "softfloat.h"
#ifdef CONFIG_FPE_NWFPE_XP
extern
flag
floatx80_is_nan
(
floatx80
);
#endif
unsigned
int
PerformFLT
(
const
unsigned
int
opcode
);
unsigned
int
PerformFIX
(
const
unsigned
int
opcode
);
...
...
arch/arm/nwfpe/softfloat.h
浏览文件 @
b477dfba
...
...
@@ -226,6 +226,8 @@ char floatx80_le_quiet( floatx80, floatx80 );
char
floatx80_lt_quiet
(
floatx80
,
floatx80
);
char
floatx80_is_signaling_nan
(
floatx80
);
extern
flag
floatx80_is_nan
(
floatx80
);
#endif
static
inline
flag
extractFloat32Sign
(
float32
a
)
...
...
arch/arm/plat-s3c/clock.c
浏览文件 @
b477dfba
...
...
@@ -306,8 +306,6 @@ struct clk s3c24xx_uclk = {
int
s3c24xx_register_clock
(
struct
clk
*
clk
)
{
clk
->
owner
=
THIS_MODULE
;
if
(
clk
->
enable
==
NULL
)
clk
->
enable
=
clk_null_enable
;
...
...
arch/arm/plat-s3c24xx/dma.c
浏览文件 @
b477dfba
...
...
@@ -1235,7 +1235,7 @@ int s3c2410_dma_getposition(unsigned int channel, dma_addr_t *src, dma_addr_t *d
EXPORT_SYMBOL
(
s3c2410_dma_getposition
);
static
struct
s3c2410_dma_chan
*
to_dma_chan
(
struct
sys_device
*
dev
)
static
inline
struct
s3c2410_dma_chan
*
to_dma_chan
(
struct
sys_device
*
dev
)
{
return
container_of
(
dev
,
struct
s3c2410_dma_chan
,
dev
);
}
...
...
arch/arm/plat-s3c64xx/gpiolib.c
浏览文件 @
b477dfba
...
...
@@ -57,7 +57,7 @@
#if 1
#define gpio_dbg(x...) do { } while(0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG
##
x)
#define gpio_dbg(x...) printk(KERN_DEBUG x)
#endif
/* The s3c64xx_gpiolib_4bit routines are to control the gpio banks where
...
...
arch/arm/plat-s3c64xx/include/plat/gpio-bank-h.h
浏览文件 @
b477dfba
...
...
@@ -61,14 +61,14 @@
#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)
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