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af6cb4c1
编写于
5月 20, 2015
作者:
R
Rob Clark
浏览文件
操作
浏览文件
下载
电子邮件补丁
差异文件
drm/msm: update generated headers
Signed-off-by:
N
Rob Clark
<
robdclark@gmail.com
>
上级
a5436e1d
变更
17
展开全部
隐藏空白更改
内联
并排
Showing
17 changed file
with
1359 addition
and
143 deletion
+1359
-143
drivers/gpu/drm/msm/adreno/a2xx.xml.h
drivers/gpu/drm/msm/adreno/a2xx.xml.h
+3
-3
drivers/gpu/drm/msm/adreno/a3xx.xml.h
drivers/gpu/drm/msm/adreno/a3xx.xml.h
+156
-12
drivers/gpu/drm/msm/adreno/a4xx.xml.h
drivers/gpu/drm/msm/adreno/a4xx.xml.h
+394
-26
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
+3
-3
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
+17
-14
drivers/gpu/drm/msm/dsi/dsi.xml.h
drivers/gpu/drm/msm/dsi/dsi.xml.h
+161
-2
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
+6
-6
drivers/gpu/drm/msm/dsi/sfpb.xml.h
drivers/gpu/drm/msm/dsi/sfpb.xml.h
+6
-6
drivers/gpu/drm/msm/edp/edp.xml.h
drivers/gpu/drm/msm/edp/edp.xml.h
+94
-7
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
+93
-6
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
+6
-6
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
+16
-16
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
+383
-15
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
+7
-7
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
+5
-5
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
+8
-8
drivers/gpu/drm/msm/mdp/mdp_kms.h
drivers/gpu/drm/msm/mdp/mdp_kms.h
+1
-1
未找到文件。
drivers/gpu/drm/msm/adreno/a2xx.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
5085 bytes, from 2014-12-20 21:49:41
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
4344 bytes, from 2014-12-12 20:22:26
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
51069 bytes, from 2014-12-21 15:51:54
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
4895 bytes, from 2015-04-19 15:23:28
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
6709 bytes, from 2015-04-12 18:16:35
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
60633 bytes, from 2015-05-20 14:48:19
)
Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
drivers/gpu/drm/msm/adreno/a3xx.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
5085 bytes, from 2014-12-20 21:49:41
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
4344 bytes, from 2014-12-12 20:22:26
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
51069 bytes, from 2014-12-21 15:51:54
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
4895 bytes, from 2015-04-19 15:23:28
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
6709 bytes, from 2015-04-12 18:16:35
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
60633 bytes, from 2015-05-20 14:48:19
)
Copyright (C) 2013-201
4
by the following authors:
Copyright (C) 2013-201
5
by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
...
...
@@ -130,6 +130,10 @@ enum a3xx_tex_fmt {
TFMT_I420_Y
=
24
,
TFMT_I420_U
=
26
,
TFMT_I420_V
=
27
,
TFMT_ATC_RGB
=
32
,
TFMT_ATC_RGBA_EXPLICIT
=
33
,
TFMT_ETC1
=
34
,
TFMT_ATC_RGBA_INTERPOLATED
=
35
,
TFMT_DXT1
=
36
,
TFMT_DXT3
=
37
,
TFMT_DXT5
=
38
,
...
...
@@ -178,10 +182,13 @@ enum a3xx_tex_fmt {
TFMT_32_SINT
=
92
,
TFMT_32_32_SINT
=
93
,
TFMT_32_32_32_32_SINT
=
95
,
TFMT_RGTC2_SNORM
=
112
,
TFMT_RGTC2_UNORM
=
113
,
TFMT_RGTC1_SNORM
=
114
,
TFMT_RGTC1_UNORM
=
115
,
TFMT_ETC2_RG11_SNORM
=
112
,
TFMT_ETC2_RG11_UNORM
=
113
,
TFMT_ETC2_R11_SNORM
=
114
,
TFMT_ETC2_R11_UNORM
=
115
,
TFMT_ETC2_RGBA8
=
116
,
TFMT_ETC2_RGB8A1
=
117
,
TFMT_ETC2_RGB8
=
118
,
};
enum
a3xx_tex_fetchsize
{
...
...
@@ -209,14 +216,24 @@ enum a3xx_color_fmt {
RB_R10G10B10A2_UNORM
=
16
,
RB_A8_UNORM
=
20
,
RB_R8_UNORM
=
21
,
RB_R16_FLOAT
=
24
,
RB_R16G16_FLOAT
=
25
,
RB_R16G16B16A16_FLOAT
=
27
,
RB_R11G11B10_FLOAT
=
28
,
RB_R16_SNORM
=
32
,
RB_R16G16_SNORM
=
33
,
RB_R16G16B16A16_SNORM
=
35
,
RB_R16_UNORM
=
36
,
RB_R16G16_UNORM
=
37
,
RB_R16G16B16A16_UNORM
=
39
,
RB_R16_SINT
=
40
,
RB_R16G16_SINT
=
41
,
RB_R16G16B16A16_SINT
=
43
,
RB_R16_UINT
=
44
,
RB_R16G16_UINT
=
45
,
RB_R16G16B16A16_UINT
=
47
,
RB_R32_FLOAT
=
48
,
RB_R32G32_FLOAT
=
49
,
RB_R32G32B32A32_FLOAT
=
51
,
RB_R32_SINT
=
52
,
RB_R32G32_SINT
=
53
,
...
...
@@ -265,6 +282,12 @@ enum a3xx_intp_mode {
FLAT
=
1
,
};
enum
a3xx_repl_mode
{
S
=
1
,
T
=
2
,
ONE_T
=
3
,
};
enum
a3xx_tex_filter
{
A3XX_TEX_NEAREST
=
0
,
A3XX_TEX_LINEAR
=
1
,
...
...
@@ -751,7 +774,7 @@ static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
#define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
static
inline
uint32_t
A3XX_GRAS_SU_POLY_OFFSET_OFFSET
(
float
val
)
{
return
((((
int32_t
)(
val
*
1638
4
.
0
)))
<<
A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
)
&
A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
return
((((
int32_t
)(
val
*
6
4
.
0
)))
<<
A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT
)
&
A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK
;
}
#define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
...
...
@@ -854,6 +877,12 @@ static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode va
{
return
((
val
)
<<
A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT
)
&
A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK
;
}
#define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000
#define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12
static
inline
uint32_t
A3XX_RB_MODE_CONTROL_MRT
(
uint32_t
val
)
{
return
((
val
)
<<
A3XX_RB_MODE_CONTROL_MRT__SHIFT
)
&
A3XX_RB_MODE_CONTROL_MRT__MASK
;
}
#define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
#define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
...
...
@@ -1246,9 +1275,21 @@ static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op v
#define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
#define REG_A3XX_RB_STENCIL_BUF_INFO 0x00002106
#define REG_A3XX_RB_STENCIL_INFO 0x00002106
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800
#define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
static
inline
uint32_t
A3XX_RB_STENCIL_INFO_STENCIL_BASE
(
uint32_t
val
)
{
return
((
val
>>
12
)
<<
A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT
)
&
A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK
;
}
#define REG_A3XX_RB_STENCIL_BUF_PITCH 0x00002107
#define REG_A3XX_RB_STENCIL_PITCH 0x00002107
#define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff
#define A3XX_RB_STENCIL_PITCH__SHIFT 0
static
inline
uint32_t
A3XX_RB_STENCIL_PITCH
(
uint32_t
val
)
{
return
((
val
>>
3
)
<<
A3XX_RB_STENCIL_PITCH__SHIFT
)
&
A3XX_RB_STENCIL_PITCH__MASK
;
}
#define REG_A3XX_RB_STENCILREFMASK 0x00002108
#define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
...
...
@@ -1356,6 +1397,7 @@ static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_
{
return
((
val
)
<<
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT
)
&
A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK
;
}
#define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
#define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
#define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
#define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
...
...
@@ -1805,6 +1847,102 @@ static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
static
inline
uint32_t
REG_A3XX_VPC_VARYING_PS_REPL
(
uint32_t
i0
)
{
return
0x00002286
+
0x1
*
i0
;
}
static
inline
uint32_t
REG_A3XX_VPC_VARYING_PS_REPL_MODE
(
uint32_t
i0
)
{
return
0x00002286
+
0x1
*
i0
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
#define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C0
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c
#define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C1
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030
#define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C2
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0
#define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C3
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300
#define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C4
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00
#define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C5
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C6
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C7
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C8
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000
#define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_C9
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CA
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CB
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CC
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CD
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CE
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK
;
}
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000
#define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30
static
inline
uint32_t
A3XX_VPC_VARYING_PS_REPL_MODE_CF
(
enum
a3xx_repl_mode
val
)
{
return
((
val
)
<<
A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT
)
&
A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK
;
}
#define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
...
...
@@ -2107,6 +2245,12 @@ static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
#define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
#define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
#define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003
#define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
static
inline
uint32_t
A3XX_SP_FS_OUTPUT_REG_MRT
(
uint32_t
val
)
{
return
((
val
)
<<
A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT
)
&
A3XX_SP_FS_OUTPUT_REG_MRT__MASK
;
}
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
#define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
...
...
@@ -2661,7 +2805,7 @@ static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
}
#define REG_A3XX_TEX_CONST_3 0x00000003
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000
000
f
#define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0000
7ff
f
#define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
static
inline
uint32_t
A3XX_TEX_CONST_3_LAYERSZ1
(
uint32_t
val
)
{
...
...
drivers/gpu/drm/msm/adreno/a4xx.xml.h
浏览文件 @
af6cb4c1
此差异已折叠。
点击以展开。
drivers/gpu/drm/msm/adreno/adreno_common.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -12,9 +12,9 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
5085 bytes, from 2014-12-20 21:49:41
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
4344 bytes, from 2014-12-12 20:22:26
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
51069 bytes, from 2014-12-21 15:51:54
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
4895 bytes, from 2015-04-19 15:23:28
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
6709 bytes, from 2015-04-12 18:16:35
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
60633 bytes, from 2015-05-20 14:48:19
)
Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
drivers/gpu/drm/msm/adreno/adreno_pm4.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -12,11 +12,11 @@ The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a2xx.xml ( 32901 bytes, from 2014-06-02 15:21:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_common.xml ( 10551 bytes, from 2014-11-13 22:44:30)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
5085 bytes, from 2014-12-20 21:49:41
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
4344 bytes, from 2014-12-12 20:22:26
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
51069 bytes, from 2014-12-21 15:51:54
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/adreno_pm4.xml ( 1
4895 bytes, from 2015-04-19 15:23:28
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a3xx.xml ( 6
6709 bytes, from 2015-04-12 18:16:35
)
- /home/robclark/src/freedreno/envytools/rnndb/adreno/a4xx.xml (
60633 bytes, from 2015-05-20 14:48:19
)
Copyright (C) 2013-201
4
by the following authors:
Copyright (C) 2013-201
5
by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
...
...
@@ -76,16 +76,11 @@ enum pc_di_primtype {
DI_PT_LINELOOP
=
7
,
DI_PT_RECTLIST
=
8
,
DI_PT_POINTLIST_A3XX
=
9
,
DI_PT_QUADLIST
=
13
,
DI_PT_QUADSTRIP
=
14
,
DI_PT_POLYGON
=
15
,
DI_PT_2D_COPY_RECT_LIST_V0
=
16
,
DI_PT_2D_COPY_RECT_LIST_V1
=
17
,
DI_PT_2D_COPY_RECT_LIST_V2
=
18
,
DI_PT_2D_COPY_RECT_LIST_V3
=
19
,
DI_PT_2D_FILL_RECT_LIST
=
20
,
DI_PT_2D_LINE_STRIP
=
21
,
DI_PT_2D_TRI_STRIP
=
22
,
DI_PT_LINE_ADJ
=
10
,
DI_PT_LINESTRIP_ADJ
=
11
,
DI_PT_TRI_ADJ
=
12
,
DI_PT_TRISTRIP_ADJ
=
13
,
DI_PT_PATCHES
=
34
,
};
enum
pc_di_src_sel
{
...
...
@@ -192,6 +187,7 @@ enum adreno_state_block {
SB_FRAG_TEX
=
2
,
SB_FRAG_MIPADDR
=
3
,
SB_VERT_SHADER
=
4
,
SB_GEOM_SHADER
=
5
,
SB_FRAG_SHADER
=
6
,
};
...
...
@@ -382,12 +378,19 @@ static inline uint32_t CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(enum pc_di_src_sel va
{
return
((
val
)
<<
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__SHIFT
)
&
CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT__MASK
;
}
#define CP_DRAW_INDX_OFFSET_0_TESSELLATE 0x00000100
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK 0x00000c00
#define CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT 10
static
inline
uint32_t
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE
(
enum
a4xx_index_size
val
)
{
return
((
val
)
<<
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__SHIFT
)
&
CP_DRAW_INDX_OFFSET_0_INDEX_SIZE__MASK
;
}
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK 0x01f00000
#define CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT 20
static
inline
uint32_t
CP_DRAW_INDX_OFFSET_0_TESS_MODE
(
uint32_t
val
)
{
return
((
val
)
<<
CP_DRAW_INDX_OFFSET_0_TESS_MODE__SHIFT
)
&
CP_DRAW_INDX_OFFSET_0_TESS_MODE__MASK
;
}
#define REG_CP_DRAW_INDX_OFFSET_1 0x00000001
#define CP_DRAW_INDX_OFFSET_1_NUM_INSTANCES__MASK 0xffffffff
...
...
drivers/gpu/drm/msm/dsi/dsi.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -8,8 +8,17 @@ This file was generated by the rules-ng-ng headergen tool in this git repository
git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /usr2/hali/local/envytools/envytools/rnndb/dsi/dsi.xml ( 18681 bytes, from 2015-03-04 23:08:31)
- /usr2/hali/local/envytools/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2015-01-28 21:43:22)
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 20915 bytes, from 2015-03-24 22:05:22)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 2352 bytes, from 2015-04-12 15:02:42)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml ( 35083 bytes, from 2015-04-12 15:04:03)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml ( 22094 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 29012 bytes, from 2015-05-12 12:45:23)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml ( 10416 bytes, from 2015-05-12 12:45:23)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
@@ -394,6 +403,9 @@ static inline uint32_t DSI_CLKOUT_TIMING_CTRL_T_CLK_POST(uint32_t val)
#define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
#define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
#define REG_DSI_LANE_CTRL 0x000000a8
#define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
#define REG_DSI_LANE_SWAP_CTRL 0x000000ac
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
#define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
...
...
@@ -835,5 +847,152 @@ static inline uint32_t DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD(uint32_t val)
#define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
#define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
#define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
#define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
static
inline
uint32_t
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV
(
uint32_t
val
)
{
return
((
val
)
<<
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT
)
&
DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK
;
}
#define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
#define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
#define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
static
inline
uint32_t
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET
(
uint32_t
val
)
{
return
((
val
)
<<
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT
)
&
DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK
;
}
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT 6
static
inline
uint32_t
DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN
(
uint32_t
val
)
{
return
((
val
)
<<
DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__SHIFT
)
&
DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK
;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
static
inline
uint32_t
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0
(
uint32_t
val
)
{
return
((
val
)
<<
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT
)
&
DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK
;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
#define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
static
inline
uint32_t
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8
(
uint32_t
val
)
{
return
((
val
)
<<
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT
)
&
DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK
;
}
#define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
#define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
#define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
#define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
#define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
#define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
#define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
#define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
#define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
#define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
#define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
#define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
#endif
/* DSI_XML */
drivers/gpu/drm/msm/dsi/mmss_cc.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013-2014 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
drivers/gpu/drm/msm/dsi/sfpb.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
drivers/gpu/drm/msm/edp/edp.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013-201
4
by the following authors:
Copyright (C) 2013-201
5
by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
...
...
@@ -288,5 +288,92 @@ static inline uint32_t REG_EDP_PHY_LN_PD_CTL(uint32_t i0) { return 0x00000404 +
#define REG_EDP_PHY_GLB_PHY_STATUS 0x00000598
#define REG_EDP_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define REG_EDP_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_EDP_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_EDP_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_EDP_28nm_PHY_PLL_VREG_CFG 0x00000010
#define REG_EDP_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_EDP_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_EDP_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_EDP_28nm_PHY_PLL_GLB_CFG 0x00000020
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define EDP_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_EDP_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_EDP_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_EDP_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_EDP_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_EDP_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_EDP_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define REG_EDP_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define REG_EDP_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define REG_EDP_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define REG_EDP_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_EDP_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_EDP_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_EDP_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_EDP_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_EDP_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_EDP_28nm_PHY_PLL_TEST_CFG 0x00000068
#define EDP_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_EDP_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_EDP_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_EDP_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_EDP_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_EDP_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_EDP_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_EDP_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_EDP_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_EDP_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_EDP_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_EDP_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_EDP_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#endif
/* EDP_XML */
drivers/gpu/drm/msm/hdmi/hdmi.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013-2015 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
@@ -750,5 +750,92 @@ static inline uint32_t HDMI_8x60_PHY_REG1_OUTVOL_SWING_CTRL(uint32_t val)
#define REG_HDMI_8x74_BIST_PATN3 0x00000048
#define REG_HDMI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
#define REG_HDMI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
#define REG_HDMI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
#define REG_HDMI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
#define REG_HDMI_28nm_PHY_PLL_VREG_CFG 0x00000010
#define REG_HDMI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
#define REG_HDMI_28nm_PHY_PLL_DMUX_CFG 0x00000018
#define REG_HDMI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
#define REG_HDMI_28nm_PHY_PLL_GLB_CFG 0x00000020
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
#define HDMI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
#define REG_HDMI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
#define REG_HDMI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
#define REG_HDMI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
#define REG_HDMI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
#define REG_HDMI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG0 0x00000038
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG2 0x00000040
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG3 0x00000044
#define REG_HDMI_28nm_PHY_PLL_SDM_CFG4 0x00000048
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG1 0x00000050
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG2 0x00000054
#define REG_HDMI_28nm_PHY_PLL_SSC_CFG3 0x00000058
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
#define REG_HDMI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
#define REG_HDMI_28nm_PHY_PLL_TEST_CFG 0x00000068
#define HDMI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG1 0x00000070
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG2 0x00000074
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG3 0x00000078
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG5 0x00000080
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG6 0x00000084
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG7 0x00000088
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG9 0x00000090
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG10 0x00000094
#define REG_HDMI_28nm_PHY_PLL_CAL_CFG11 0x00000098
#define REG_HDMI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
#define REG_HDMI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
#endif
/* HDMI_XML */
drivers/gpu/drm/msm/hdmi/qfprom.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,15 +10,15 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013 by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
...
...
drivers/gpu/drm/msm/mdp/mdp4/mdp4.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013-201
4
by the following authors:
Copyright (C) 2013-201
5
by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
...
...
@@ -680,18 +680,18 @@ static inline uint32_t MDP4_PIPE_SRC_STRIDE_B_P3(uint32_t val)
return
((
val
)
<<
MDP4_PIPE_SRC_STRIDE_B_P3__SHIFT
)
&
MDP4_PIPE_SRC_STRIDE_B_P3__MASK
;
}
static
inline
uint32_t
REG_MDP4_PIPE_FRAME_SIZE
(
enum
mdp4_pipe
i0
)
{
return
0x00020048
+
0x10000
*
i0
;
}
#define MDP4_PIPE_
FRAME_SIZE_HEIGHT__MASK
0xffff0000
#define MDP4_PIPE_
FRAME_SIZE_HEIGHT__SHIFT
16
static
inline
uint32_t
MDP4_PIPE_FRAME_SIZE_HEIGHT
(
uint32_t
val
)
static
inline
uint32_t
REG_MDP4_PIPE_
SSTILE_
FRAME_SIZE
(
enum
mdp4_pipe
i0
)
{
return
0x00020048
+
0x10000
*
i0
;
}
#define MDP4_PIPE_
SSTILE_FRAME_SIZE_HEIGHT__MASK
0xffff0000
#define MDP4_PIPE_
SSTILE_FRAME_SIZE_HEIGHT__SHIFT
16
static
inline
uint32_t
MDP4_PIPE_
SSTILE_
FRAME_SIZE_HEIGHT
(
uint32_t
val
)
{
return
((
val
)
<<
MDP4_PIPE_
FRAME_SIZE_HEIGHT__SHIFT
)
&
MDP4_PIP
E_FRAME_SIZE_HEIGHT__MASK
;
return
((
val
)
<<
MDP4_PIPE_
SSTILE_FRAME_SIZE_HEIGHT__SHIFT
)
&
MDP4_PIPE_SSTIL
E_FRAME_SIZE_HEIGHT__MASK
;
}
#define MDP4_PIPE_FRAME_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_
FRAME_SIZE_WIDTH__SHIFT
0
static
inline
uint32_t
MDP4_PIPE_FRAME_SIZE_WIDTH
(
uint32_t
val
)
#define MDP4_PIPE_
SSTILE_
FRAME_SIZE_WIDTH__MASK 0x0000ffff
#define MDP4_PIPE_
SSTILE_FRAME_SIZE_WIDTH__SHIFT
0
static
inline
uint32_t
MDP4_PIPE_
SSTILE_
FRAME_SIZE_WIDTH
(
uint32_t
val
)
{
return
((
val
)
<<
MDP4_PIPE_
FRAME_SIZE_WIDTH__SHIFT
)
&
MDP4_PIP
E_FRAME_SIZE_WIDTH__MASK
;
return
((
val
)
<<
MDP4_PIPE_
SSTILE_FRAME_SIZE_WIDTH__SHIFT
)
&
MDP4_PIPE_SSTIL
E_FRAME_SIZE_WIDTH__MASK
;
}
static
inline
uint32_t
REG_MDP4_PIPE_SRC_FORMAT
(
enum
mdp4_pipe
i0
)
{
return
0x00020050
+
0x10000
*
i0
;
}
...
...
drivers/gpu/drm/msm/mdp/mdp5/mdp5.xml.h
浏览文件 @
af6cb4c1
此差异已折叠。
点击以展开。
drivers/gpu/drm/msm/mdp/mdp5/mdp5_cmd_encoder.c
浏览文件 @
af6cb4c1
...
...
@@ -281,22 +281,22 @@ int mdp5_cmd_encoder_set_split_display(struct drm_encoder *encoder,
* start signal for the slave encoder
*/
if
(
intf_num
==
1
)
data
|=
MDP5_SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX
;
data
|=
MDP5_
MDP_
SPLIT_DPL_UPPER_INTF2_SW_TRG_MUX
;
else
if
(
intf_num
==
2
)
data
|=
MDP5_SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX
;
data
|=
MDP5_
MDP_
SPLIT_DPL_UPPER_INTF1_SW_TRG_MUX
;
else
return
-
EINVAL
;
/* Smart Panel, Sync mode */
data
|=
MDP5_SPLIT_DPL_UPPER_SMART_PANEL
;
data
|=
MDP5_
MDP_
SPLIT_DPL_UPPER_SMART_PANEL
;
/* Make sure clocks are on when connectors calling this function. */
mdp5_enable
(
mdp5_kms
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_UPPER
,
data
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_UPPER
(
0
)
,
data
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_LOWER
,
MDP5_SPLIT_DPL_LOWER_SMART_PANEL
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_EN
,
1
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_LOWER
(
0
)
,
MDP5_
MDP_
SPLIT_DPL_LOWER_SMART_PANEL
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_EN
(
0
)
,
1
);
mdp5_disable
(
mdp5_kms
);
return
0
;
...
...
drivers/gpu/drm/msm/mdp/mdp5/mdp5_encoder.c
浏览文件 @
af6cb4c1
...
...
@@ -304,9 +304,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
* to use the master's enable signal for the slave encoder.
*/
if
(
intf_num
==
1
)
data
|=
MDP5_SPLIT_DPL_LOWER_INTF2_TG_SYNC
;
data
|=
MDP5_
MDP_
SPLIT_DPL_LOWER_INTF2_TG_SYNC
;
else
if
(
intf_num
==
2
)
data
|=
MDP5_SPLIT_DPL_LOWER_INTF1_TG_SYNC
;
data
|=
MDP5_
MDP_
SPLIT_DPL_LOWER_INTF1_TG_SYNC
;
else
return
-
EINVAL
;
...
...
@@ -315,9 +315,9 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
mdp5_write
(
mdp5_kms
,
REG_MDP5_MDP_SPARE_0
(
0
),
MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN
);
/* Dumb Panel, Sync mode */
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_UPPER
,
0
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_LOWER
,
data
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
SPLIT_DPL_EN
,
1
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_UPPER
(
0
)
,
0
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_LOWER
(
0
)
,
data
);
mdp5_write
(
mdp5_kms
,
REG_MDP5_
MDP_SPLIT_DPL_EN
(
0
)
,
1
);
mdp5_disable
(
mdp5_kms
);
return
0
;
...
...
drivers/gpu/drm/msm/mdp/mdp_common.xml.h
浏览文件 @
af6cb4c1
...
...
@@ -10,17 +10,17 @@ git clone https://github.com/freedreno/envytools.git
The rules-ng-ng source files this header was generated from are:
- /home/robclark/src/freedreno/envytools/rnndb/msm.xml ( 676 bytes, from 2014-12-05 15:34:49)
- /home/robclark/src/freedreno/envytools/rnndb/freedreno_copyright.xml ( 1453 bytes, from 2013-03-31 16:51:27)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
08 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
7 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
27208 bytes, from 2015-01-13 23:56:11
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
11712 bytes, from 2013-08-17 17:13:4
3)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp4.xml ( 209
15 bytes, from 2015-03-24 22:05:22
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp_common.xml ( 235
2 bytes, from 2015-04-12 15:02:42
)
- /home/robclark/src/freedreno/envytools/rnndb/mdp/mdp5.xml (
35083 bytes, from 2015-04-12 15:04:03
)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/dsi.xml (
22094 bytes, from 2015-05-12 12:45:2
3)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/sfpb.xml ( 344 bytes, from 2013-08-11 19:26:32)
- /home/robclark/src/freedreno/envytools/rnndb/dsi/mmss_cc.xml ( 1686 bytes, from 2014-10-31 16:48:57)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/qfprom.xml ( 600 bytes, from 2013-07-05 19:21:12)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
6848 bytes, from 2015-01-13 23:55:57
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
8253 bytes, from 2014-12-08 16:13:00
)
- /home/robclark/src/freedreno/envytools/rnndb/hdmi/hdmi.xml ( 2
9012 bytes, from 2015-05-12 12:45:23
)
- /home/robclark/src/freedreno/envytools/rnndb/edp/edp.xml (
10416 bytes, from 2015-05-12 12:45:23
)
Copyright (C) 2013-201
4
by the following authors:
Copyright (C) 2013-201
5
by the following authors:
- Rob Clark <robdclark@gmail.com> (robclark)
Permission is hereby granted, free of charge, to any person obtaining
...
...
@@ -52,7 +52,7 @@ enum mdp_chroma_samp_type {
CHROMA_420
=
3
,
};
enum
mdp_
sspp_
fetch_type
{
enum
mdp_fetch_type
{
MDP_PLANE_INTERLEAVED
=
0
,
MDP_PLANE_PLANAR
=
1
,
MDP_PLANE_PSEUDO_PLANAR
=
2
,
...
...
drivers/gpu/drm/msm/mdp/mdp_kms.h
浏览文件 @
af6cb4c1
...
...
@@ -88,7 +88,7 @@ struct mdp_format {
uint8_t
unpack
[
4
];
bool
alpha_enable
,
unpack_tight
;
uint8_t
cpp
,
unpack_count
;
enum
mdp_
sspp_
fetch_type
fetch_type
;
enum
mdp_fetch_type
fetch_type
;
enum
mdp_chroma_samp_type
chroma_sample
;
};
#define to_mdp_format(x) container_of(x, struct mdp_format, base)
...
...
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