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体验新版 GitCode,发现更多精彩内容 >>
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a12e4537
编写于
8月 09, 2013
作者:
B
Benjamin Herrenschmidt
浏览文件
操作
浏览文件
下载
差异文件
Merge remote-tracking branch 'scott/next' into next
Merge some Freescale updates from Scott Wood
上级
b7bc9e7d
c8db32c8
变更
38
隐藏空白更改
内联
并排
Showing
38 changed file
with
1088 addition
and
155 deletion
+1088
-155
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
+41
-12
arch/powerpc/Makefile
arch/powerpc/Makefile
+16
-2
arch/powerpc/boot/dts/b4420qds.dts
arch/powerpc/boot/dts/b4420qds.dts
+1
-1
arch/powerpc/boot/dts/b4860qds.dts
arch/powerpc/boot/dts/b4860qds.dts
+1
-1
arch/powerpc/boot/dts/b4qds.dtsi
arch/powerpc/boot/dts/b4qds.dtsi
+0
-0
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
+1
-1
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
+149
-0
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
+1
-1
arch/powerpc/boot/dts/p1020rdb-pd.dts
arch/powerpc/boot/dts/p1020rdb-pd.dts
+280
-0
arch/powerpc/configs/85xx/p1023rds_defconfig
arch/powerpc/configs/85xx/p1023rds_defconfig
+1
-0
arch/powerpc/configs/corenet32_smp_defconfig
arch/powerpc/configs/corenet32_smp_defconfig
+1
-0
arch/powerpc/configs/corenet64_smp_defconfig
arch/powerpc/configs/corenet64_smp_defconfig
+1
-0
arch/powerpc/configs/mpc83xx_defconfig
arch/powerpc/configs/mpc83xx_defconfig
+1
-0
arch/powerpc/configs/mpc85xx_defconfig
arch/powerpc/configs/mpc85xx_defconfig
+1
-0
arch/powerpc/configs/mpc85xx_smp_defconfig
arch/powerpc/configs/mpc85xx_smp_defconfig
+1
-0
arch/powerpc/include/asm/epapr_hcalls.h
arch/powerpc/include/asm/epapr_hcalls.h
+6
-0
arch/powerpc/include/asm/mpic.h
arch/powerpc/include/asm/mpic.h
+7
-0
arch/powerpc/include/asm/perf_event_fsl_emb.h
arch/powerpc/include/asm/perf_event_fsl_emb.h
+1
-1
arch/powerpc/include/asm/ppc-opcode.h
arch/powerpc/include/asm/ppc-opcode.h
+47
-0
arch/powerpc/include/asm/reg_fsl_emb.h
arch/powerpc/include/asm/reg_fsl_emb.h
+19
-5
arch/powerpc/kernel/cpu_setup_fsl_booke.S
arch/powerpc/kernel/cpu_setup_fsl_booke.S
+1
-1
arch/powerpc/kernel/cputable.c
arch/powerpc/kernel/cputable.c
+1
-1
arch/powerpc/kernel/epapr_paravirt.c
arch/powerpc/kernel/epapr_paravirt.c
+16
-12
arch/powerpc/kernel/setup_32.c
arch/powerpc/kernel/setup_32.c
+3
-1
arch/powerpc/kernel/setup_64.c
arch/powerpc/kernel/setup_64.c
+3
-0
arch/powerpc/kernel/swsusp_booke.S
arch/powerpc/kernel/swsusp_booke.S
+8
-0
arch/powerpc/kernel/traps.c
arch/powerpc/kernel/traps.c
+3
-0
arch/powerpc/kvm/emulate.c
arch/powerpc/kvm/emulate.c
+1
-44
arch/powerpc/oprofile/op_model_fsl_emb.c
arch/powerpc/oprofile/op_model_fsl_emb.c
+30
-0
arch/powerpc/perf/Makefile
arch/powerpc/perf/Makefile
+1
-1
arch/powerpc/perf/core-fsl-emb.c
arch/powerpc/perf/core-fsl-emb.c
+30
-0
arch/powerpc/perf/e6500-pmu.c
arch/powerpc/perf/e6500-pmu.c
+121
-0
arch/powerpc/platforms/85xx/corenet_ds.c
arch/powerpc/platforms/85xx/corenet_ds.c
+0
-6
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+22
-0
arch/powerpc/sysdev/fsl_msi.c
arch/powerpc/sysdev/fsl_msi.c
+96
-41
arch/powerpc/sysdev/fsl_msi.h
arch/powerpc/sysdev/fsl_msi.h
+7
-3
arch/powerpc/sysdev/fsl_pci.c
arch/powerpc/sysdev/fsl_pci.c
+163
-21
arch/powerpc/sysdev/fsl_pci.h
arch/powerpc/sysdev/fsl_pci.h
+6
-0
未找到文件。
Documentation/devicetree/bindings/powerpc/fsl/msi-pic.txt
浏览文件 @
a12e4537
* Freescale MSI interrupt controller
Required properties:
- compatible : compatible list, contains 2 entries,
first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" depending on
the parent type.
- compatible : compatible list, may contain one or two entries
The first is "fsl,CHIP-msi", where CHIP is the processor(mpc8610, mpc8572,
etc.) and the second is "fsl,mpic-msi" or "fsl,ipic-msi" or
"fsl,mpic-msi-v4.3" depending on the parent type and version. If mpic
version is 4.3, the number of MSI registers is increased to 16, MSIIR1 is
provided to access these 16 registers, and compatible "fsl,mpic-msi-v4.3"
should be used. The first entry is optional; the second entry is
required.
- reg : It may contain one or two regions. The first region should contain
the address and the length of the shared message interrupt register set.
The second region should contain the address of aliased MSIIR register for
platforms that have such an alias.
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
optional, without this, all the 256 MSI interrupts can be used.
Each available range must begin and end on a multiple of 32 (i.e.
no splitting an individual MSI register or the associated PIC interrupt).
The second region should contain the address of aliased MSIIR or MSIIR1
register for platforms that have such an alias, if using MSIIR1, the second
region must be added because different MSI group has different MSIIR1 offset.
- interrupts : each one of the interrupts here is one entry per 32 MSIs,
and routed to the host interrupt controller. the interrupts should
...
...
@@ -28,6 +27,14 @@ Required properties:
to MPIC.
Optional properties:
- msi-available-ranges: use <start count> style section to define which
msi interrupt can be used in the 256 msi interrupts. This property is
optional, without this, all the MSI interrupts can be used.
Each available range must begin and end on a multiple of 32 (i.e.
no splitting an individual MSI register or the associated PIC interrupt).
MPIC v4.3 does not support this property because the 32 interrupts of an
individual register are not continuous when using MSIIR1.
- msi-address-64: 64-bit PCI address of the MSIIR register. The MSIIR register
is used for MSI messaging. The address of MSIIR in PCI address space is
the MSI message address.
...
...
@@ -54,6 +61,28 @@ Example:
interrupt-parent = <&mpic>;
};
msi@41600 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41600 0x200 0x44148 4>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0
0x100 0 0 0
0x101 0 0 0
0x102 0 0 0
0x103 0 0 0
0x104 0 0 0
0x105 0 0 0
0x106 0 0 0
0x107 0 0 0>;
};
The Freescale hypervisor and msi-address-64
-------------------------------------------
Normally, PCI devices have access to all of CCSR via an ATMU mapping. The
...
...
arch/powerpc/Makefile
浏览文件 @
a12e4537
...
...
@@ -98,7 +98,7 @@ CFLAGS-$(CONFIG_POWER7_CPU) += $(call cc-option,-mcpu=power7)
CFLAGS-$(CONFIG_TUNE_CELL)
+=
$(
call
cc-option,-mtune
=
cell
)
KBUILD_CPPFLAGS
+=
-Iarch
/
$(ARCH)
KBUILD_AFLAGS
+=
-Iarch
/
$(ARCH)
KBUILD_AFLAGS
+=
-
msoft-float
-
Iarch
/
$(ARCH)
KBUILD_CFLAGS
+=
-msoft-float
-pipe
-Iarch
/
$(ARCH)
$
(
CFLAGS-y
)
CPP
=
$(CC)
-E
$(KBUILD_CFLAGS)
...
...
@@ -132,6 +132,21 @@ ifeq ($(CONFIG_6xx),y)
KBUILD_CFLAGS
+=
-mcpu
=
powerpc
endif
ifeq
($(CONFIG_E500),y)
ifeq
($(CONFIG_64BIT),y)
KBUILD_CFLAGS
+=
-mcpu
=
e5500
KBUILD_AFLAGS
+=
-mcpu
=
e5500
else
ifeq
($(CONFIG_PPC_E500MC),y)
KBUILD_CFLAGS
+=
-mcpu
=
e500mc
KBUILD_AFLAGS
+=
-mcpu
=
e500mc
else
KBUILD_CFLAGS
+=
-mcpu
=
8540
KBUILD_AFLAGS
+=
-mcpu
=
8540
endif
endif
endif
# Work around a gcc code-gen bug with -fno-omit-frame-pointer.
ifeq
($(CONFIG_FUNCTION_TRACER),y)
KBUILD_CFLAGS
+=
-mno-sched-epilog
...
...
@@ -139,7 +154,6 @@ endif
cpu-as-$(CONFIG_4xx)
+=
-Wa
,-m405
cpu-as-$(CONFIG_ALTIVEC)
+=
-Wa
,-maltivec
cpu-as-$(CONFIG_E500)
+=
-Wa
,-me500
cpu-as-$(CONFIG_E200)
+=
-Wa
,-me200
KBUILD_AFLAGS
+=
$
(
cpu-as-y
)
...
...
arch/powerpc/boot/dts/b4420qds.dts
浏览文件 @
a12e4537
...
...
@@ -33,7 +33,7 @@
*/
/
include
/
"fsl/b4420si-pre.dtsi"
/
include
/
"b4qds.dts"
/
include
/
"b4qds.dts
i
"
/
{
model
=
"fsl,B4420QDS"
;
...
...
arch/powerpc/boot/dts/b4860qds.dts
浏览文件 @
a12e4537
...
...
@@ -33,7 +33,7 @@
*/
/
include
/
"fsl/b4860si-pre.dtsi"
/
include
/
"b4qds.dts"
/
include
/
"b4qds.dts
i
"
/
{
model
=
"fsl,B4860QDS"
;
...
...
arch/powerpc/boot/dts/b4qds.dts
→
arch/powerpc/boot/dts/b4qds.dts
i
浏览文件 @
a12e4537
文件已移动
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
浏览文件 @
a12e4537
...
...
@@ -204,7 +204,7 @@ pamu3: pamu@3000 {
};
};
/include/ "qoriq-mpic.dtsi"
/include/ "qoriq-mpic
4.3
.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,b4-device-config";
...
...
arch/powerpc/boot/dts/fsl/qoriq-mpic4.3.dtsi
0 → 100644
浏览文件 @
a12e4537
/*
* QorIQ MPIC device tree stub [ controller @ offset 0x40000 ]
*
* Copyright 2013 Freescale Semiconductor Inc.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Freescale Semiconductor nor the
* names of its contributors may be used to endorse or promote products
* derived from this software without specific prior written permission.
*
*
* ALTERNATIVELY, this software may be distributed under the terms of the
* GNU General Public License ("GPL") as published by the Free Software
* Foundation, either version 2 of that License or (at your option) any
* later version.
*
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*/
mpic: pic@40000 {
interrupt-controller;
#address-cells = <0>;
#interrupt-cells = <4>;
reg = <0x40000 0x40000>;
compatible = "fsl,mpic";
device_type = "open-pic";
clock-frequency = <0x0>;
};
timer@41100 {
compatible = "fsl,mpic-global-timer";
reg = <0x41100 0x100 0x41300 4>;
interrupts = <0 0 3 0
1 0 3 0
2 0 3 0
3 0 3 0>;
};
msi0: msi@41600 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41600 0x200 0x44148 4>;
interrupts = <
0xe0 0 0 0
0xe1 0 0 0
0xe2 0 0 0
0xe3 0 0 0
0xe4 0 0 0
0xe5 0 0 0
0xe6 0 0 0
0xe7 0 0 0
0x100 0 0 0
0x101 0 0 0
0x102 0 0 0
0x103 0 0 0
0x104 0 0 0
0x105 0 0 0
0x106 0 0 0
0x107 0 0 0>;
};
msi1: msi@41800 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41800 0x200 0x45148 4>;
interrupts = <
0xe8 0 0 0
0xe9 0 0 0
0xea 0 0 0
0xeb 0 0 0
0xec 0 0 0
0xed 0 0 0
0xee 0 0 0
0xef 0 0 0
0x108 0 0 0
0x109 0 0 0
0x10a 0 0 0
0x10b 0 0 0
0x10c 0 0 0
0x10d 0 0 0
0x10e 0 0 0
0x10f 0 0 0>;
};
msi2: msi@41a00 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41a00 0x200 0x46148 4>;
interrupts = <
0xf0 0 0 0
0xf1 0 0 0
0xf2 0 0 0
0xf3 0 0 0
0xf4 0 0 0
0xf5 0 0 0
0xf6 0 0 0
0xf7 0 0 0
0x110 0 0 0
0x111 0 0 0
0x112 0 0 0
0x113 0 0 0
0x114 0 0 0
0x115 0 0 0
0x116 0 0 0
0x117 0 0 0>;
};
msi3: msi@41c00 {
compatible = "fsl,mpic-msi-v4.3";
reg = <0x41c00 0x200 0x47148 4>;
interrupts = <
0xf8 0 0 0
0xf9 0 0 0
0xfa 0 0 0
0xfb 0 0 0
0xfc 0 0 0
0xfd 0 0 0
0xfe 0 0 0
0xff 0 0 0
0x118 0 0 0
0x119 0 0 0
0x11a 0 0 0
0x11b 0 0 0
0x11c 0 0 0
0x11d 0 0 0
0x11e 0 0 0
0x11f 0 0 0>;
};
timer@42100 {
compatible = "fsl,mpic-global-timer";
reg = <0x42100 0x100 0x42300 4>;
interrupts = <4 0 3 0
5 0 3 0
6 0 3 0
7 0 3 0>;
};
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
浏览文件 @
a12e4537
...
...
@@ -358,7 +358,7 @@ iommu@20000 {
16 2 1 30>;
};
/include/ "qoriq-mpic.dtsi"
/include/ "qoriq-mpic
4.3
.dtsi"
guts: global-utilities@e0000 {
compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
...
...
arch/powerpc/boot/dts/p1020rdb-pd.dts
0 → 100644
浏览文件 @
a12e4537
/*
*
P1020
RDB
-
PD
Device
Tree
Source
(
32
-
bit
address
map
)
*
*
Copyright
2013
Freescale
Semiconductor
Inc
.
*
*
Redistribution
and
use
in
source
and
binary
forms
,
with
or
without
*
modification
,
are
permitted
provided
that
the
following
conditions
are
met
:
*
*
Redistributions
of
source
code
must
retain
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
.
*
*
Redistributions
in
binary
form
must
reproduce
the
above
copyright
*
notice
,
this
list
of
conditions
and
the
following
disclaimer
in
the
*
documentation
and
/
or
other
materials
provided
with
the
distribution
.
*
*
Neither
the
name
of
Freescale
Semiconductor
nor
the
*
names
of
its
contributors
may
be
used
to
endorse
or
promote
products
*
derived
from
this
software
without
specific
prior
written
permission
.
*
*
*
ALTERNATIVELY
,
this
software
may
be
distributed
under
the
terms
of
the
*
GNU
General
Public
License
(
"GPL"
)
as
published
by
the
Free
Software
*
Foundation
,
either
version
2
of
that
License
or
(
at
your
option
)
any
*
later
version
.
*
*
THIS
SOFTWARE
IS
PROVIDED
BY
Freescale
Semiconductor
``
AS
IS
''
AND
ANY
*
EXPRESS
OR
IMPLIED
WARRANTIES
,
INCLUDING
,
BUT
NOT
LIMITED
TO
,
THE
IMPLIED
*
WARRANTIES
OF
MERCHANTABILITY
AND
FITNESS
FOR
A
PARTICULAR
PURPOSE
ARE
*
DISCLAIMED
.
IN
NO
EVENT
SHALL
Freescale
Semiconductor
BE
LIABLE
FOR
ANY
*
DIRECT
,
INDIRECT
,
INCIDENTAL
,
SPECIAL
,
EXEMPLARY
,
OR
CONSEQUENTIAL
DAMAGES
*
(
INCLUDING
,
BUT
NOT
LIMITED
TO
,
PROCUREMENT
OF
SUBSTITUTE
GOODS
OR
SERVICES
;
*
LOSS
OF
USE
,
DATA
,
OR
PROFITS
;
OR
BUSINESS
INTERRUPTION
)
HOWEVER
CAUSED
AND
*
ON
ANY
THEORY
OF
LIABILITY
,
WHETHER
IN
CONTRACT
,
STRICT
LIABILITY
,
OR
TORT
*
(
INCLUDING
NEGLIGENCE
OR
OTHERWISE
)
ARISING
IN
ANY
WAY
OUT
OF
THE
USE
OF
THIS
*
SOFTWARE
,
EVEN
IF
ADVISED
OF
THE
POSSIBILITY
OF
SUCH
DAMAGE
.
*/
/
include
/
"fsl/p1020si-pre.dtsi"
/
{
model
=
"fsl,P1020RDB-PD"
;
compatible
=
"fsl,P1020RDB-PD"
;
memory
{
device_type
=
"memory"
;
};
lbc
:
localbus
@
ffe05000
{
reg
=
<
0x0
0xffe05000
0x0
0x1000
>;
/*
NOR
,
NAND
flash
,
L2
switch
and
CPLD
*/
ranges
=
<
0x0
0x0
0x0
0xec000000
0x04000000
0x1
0x0
0x0
0xff800000
0x00040000
0x2
0x0
0x0
0xffa00000
0x00020000
0x3
0x0
0x0
0xffb00000
0x00020000
>;
nor
@
0
,
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"cfi-flash"
;
reg
=
<
0x0
0x0
0x4000000
>;
bank
-
width
=
<
2
>;
device
-
width
=
<
1
>;
partition
@
0
{
/*
128
KB
for
DTB
Image
*/
reg
=
<
0x0
0x00020000
>;
label
=
"NOR DTB Image"
;
};
partition
@
20000
{
/*
3.875
MB
for
Linux
Kernel
Image
*/
reg
=
<
0x00020000
0x003e0000
>;
label
=
"NOR Linux Kernel Image"
;
};
partition
@
400000
{
/*
58
MB
for
Root
file
System
*/
reg
=
<
0x00400000
0x03a00000
>;
label
=
"NOR Root File System"
;
};
partition
@
3e00000
{
/*
This
location
must
not
be
altered
*/
/*
1
M
for
Vitesse
7385
Switch
firmware
*/
reg
=
<
0x3e00000
0x00100000
>;
label
=
"NOR Vitesse-7385 Firmware"
;
read
-
only
;
};
partition
@
3f00000
{
/*
This
location
must
not
be
altered
*/
/*
512
KB
for
u
-
boot
Bootloader
Image
*/
/*
512
KB
for
u
-
boot
Environment
Variables
*/
reg
=
<
0x03f00000
0x00100000
>;
label
=
"NOR U-Boot Image"
;
read
-
only
;
};
};
nand
@
1
,
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"fsl,p1020-fcm-nand"
,
"fsl,elbc-fcm-nand"
;
reg
=
<
0x1
0x0
0x40000
>;
partition
@
0
{
/*
This
location
must
not
be
altered
*/
/*
1
MB
for
u
-
boot
Bootloader
Image
*/
reg
=
<
0x0
0x00100000
>;
label
=
"NAND U-Boot Image"
;
read
-
only
;
};
partition
@
100000
{
/*
1
MB
for
DTB
Image
*/
reg
=
<
0x00100000
0x00100000
>;
label
=
"NAND DTB Image"
;
};
partition
@
200000
{
/*
4
MB
for
Linux
Kernel
Image
*/
reg
=
<
0x00200000
0x00400000
>;
label
=
"NAND Linux Kernel Image"
;
};
partition
@
600000
{
/*
122
MB
for
File
System
Image
*/
reg
=
<
0x00600000
0x07a00000
>;
label
=
"NAND File System Image"
;
};
};
cpld
@
2
,
0
{
compatible
=
"fsl,p1020rdb-pd-cpld"
;
reg
=
<
0x2
0x0
0x20000
>;
};
L2switch
@
3
,
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"vitesse-7385"
;
reg
=
<
0x3
0x0
0x20000
>;
};
};
soc
:
soc
@
ffe00000
{
ranges
=
<
0x0
0x0
0xffe00000
0x100000
>;
i2c
@
3000
{
rtc
@
68
{
compatible
=
"dallas,ds1339"
;
reg
=
<
0x68
>;
};
};
spi
@
7000
{
flash
@
0
{
#
address
-
cells
=
<
1
>;
#
size
-
cells
=
<
1
>;
compatible
=
"spansion,s25sl12801"
;
reg
=
<
0
>;
/*
input
clock
*/
spi
-
max
-
frequency
=
<
40000000
>;
partition
@
0
{
/*
512
KB
for
u
-
boot
Bootloader
Image
*/
reg
=
<
0x0
0x00080000
>;
label
=
"SPI U-Boot Image"
;
read
-
only
;
};
partition
@
80000
{
/*
512
KB
for
DTB
Image
*/
reg
=
<
0x00080000
0x00080000
>;
label
=
"SPI DTB Image"
;
};
partition
@
100000
{
/*
4
MB
for
Linux
Kernel
Image
*/
reg
=
<
0x00100000
0x00400000
>;
label
=
"SPI Linux Kernel Image"
;
};
partition
@
500000
{
/*
11
MB
for
FS
System
Image
*/
reg
=
<
0x00500000
0x00b00000
>;
label
=
"SPI File System Image"
;
};
};
slic
@
0
{
compatible
=
"zarlink,le88266"
;
reg
=
<
1
>;
spi
-
max
-
frequency
=
<
8000000
>;
};
slic
@
1
{
compatible
=
"zarlink,le88266"
;
reg
=
<
2
>;
spi
-
max
-
frequency
=
<
8000000
>;
};
};
mdio
@
24000
{
phy0
:
ethernet
-
phy
@
0
{
interrupts
=
<
3
1
0
0
>;
reg
=
<
0x0
>;
};
phy1
:
ethernet
-
phy
@
1
{
interrupts
=
<
2
1
0
0
>;
reg
=
<
0x1
>;
};
};
mdio
@
25000
{
tbi1
:
tbi
-
phy
@
11
{
reg
=
<
0x11
>;
device_type
=
"tbi-phy"
;
};
};
mdio
@
26000
{
tbi2
:
tbi
-
phy
@
11
{
reg
=
<
0x11
>;
device_type
=
"tbi-phy"
;
};
};
enet0
:
ethernet
@
b0000
{
fixed
-
link
=
<
1
1
1000
0
0
>;
phy
-
connection
-
type
=
"rgmii-id"
;
};
enet1
:
ethernet
@
b1000
{
phy
-
handle
=
<&
phy0
>;
tbi
-
handle
=
<&
tbi1
>;
phy
-
connection
-
type
=
"sgmii"
;
};
enet2
:
ethernet
@
b2000
{
phy
-
handle
=
<&
phy1
>;
phy
-
connection
-
type
=
"rgmii-id"
;
};
usb
@
22000
{
phy_type
=
"ulpi"
;
};
};
pci0
:
pcie
@
ffe09000
{
reg
=
<
0x0
0xffe09000
0x0
0x1000
>;
ranges
=
<
0x2000000
0x0
0xa0000000
0x0
0xa0000000
0x0
0x20000000
0x1000000
0x0
0x00000000
0x0
0xffc10000
0x0
0x10000
>;
pcie
@
0
{
ranges
=
<
0x2000000
0x0
0xa0000000
0x2000000
0x0
0xa0000000
0x0
0x20000000
0x1000000
0x0
0x0
0x1000000
0x0
0x0
0x0
0x100000
>;
};
};
pci1
:
pcie
@
ffe0a000
{
reg
=
<
0x0
0xffe0a000
0x0
0x1000
>;
ranges
=
<
0x2000000
0x0
0x80000000
0x0
0x80000000
0x0
0x20000000
0x1000000
0x0
0x00000000
0x0
0xffc00000
0x0
0x10000
>;
pcie
@
0
{
ranges
=
<
0x2000000
0x0
0x80000000
0x2000000
0x0
0x80000000
0x0
0x20000000
0x1000000
0x0
0x0
0x1000000
0x0
0x0
0x0
0x100000
>;
};
};
};
/
include
/
"fsl/p1020si-post.dtsi"
arch/powerpc/configs/85xx/p1023rds_defconfig
浏览文件 @
a12e4537
...
...
@@ -63,6 +63,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_PROC_DEVICETREE=y
CONFIG_BLK_DEV_LOOP=y
CONFIG_BLK_DEV_RAM=y
...
...
arch/powerpc/configs/corenet32_smp_defconfig
浏览文件 @
a12e4537
...
...
@@ -70,6 +70,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_CMDLINE_PARTS=y
CONFIG_MTD_CHAR=y
...
...
arch/powerpc/configs/corenet64_smp_defconfig
浏览文件 @
a12e4537
...
...
@@ -59,6 +59,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
...
...
arch/powerpc/configs/mpc83xx_defconfig
浏览文件 @
a12e4537
...
...
@@ -42,6 +42,7 @@ CONFIG_INET_ESP=y
# CONFIG_IPV6 is not set
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
# CONFIG_FW_LOADER is not set
CONFIG_MTD=y
CONFIG_MTD_CHAR=y
...
...
arch/powerpc/configs/mpc85xx_defconfig
浏览文件 @
a12e4537
...
...
@@ -78,6 +78,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
...
...
arch/powerpc/configs/mpc85xx_smp_defconfig
浏览文件 @
a12e4537
...
...
@@ -81,6 +81,7 @@ CONFIG_IPV6=y
CONFIG_IP_SCTP=m
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
CONFIG_DEVTMPFS=y
CONFIG_DEVTMPFS_MOUNT=y
CONFIG_MTD=y
CONFIG_MTD_PARTITIONS=y
CONFIG_MTD_OF_PARTS=y
...
...
arch/powerpc/include/asm/epapr_hcalls.h
浏览文件 @
a12e4537
...
...
@@ -105,6 +105,12 @@
extern
bool
epapr_paravirt_enabled
;
extern
u32
epapr_hypercall_start
[];
#ifdef CONFIG_EPAPR_PARAVIRT
int
__init
epapr_paravirt_early_init
(
void
);
#else
static
inline
int
epapr_paravirt_early_init
(
void
)
{
return
0
;
}
#endif
/*
* We use "uintptr_t" to define a register because it's guaranteed to be a
* 32-bit integer on a 32-bit platform, and a 64-bit integer on a 64-bit
...
...
arch/powerpc/include/asm/mpic.h
浏览文件 @
a12e4537
...
...
@@ -396,7 +396,14 @@ extern struct bus_type mpic_subsys;
#define MPIC_REGSET_TSI108 MPIC_REGSET(1)
/* Tsi108/109 PIC */
/* Get the version of primary MPIC */
#ifdef CONFIG_MPIC
extern
u32
fsl_mpic_primary_get_version
(
void
);
#else
static
inline
u32
fsl_mpic_primary_get_version
(
void
)
{
return
0
;
}
#endif
/* Allocate the controller structure and setup the linux irq descs
* for the range if interrupts passed in. No HW initialization is
...
...
arch/powerpc/include/asm/perf_event_fsl_emb.h
浏览文件 @
a12e4537
...
...
@@ -13,7 +13,7 @@
#include <linux/types.h>
#include <asm/hw_irq.h>
#define MAX_HWEVENTS
4
#define MAX_HWEVENTS
6
/* event flags */
#define FSL_EMB_EVENT_VALID 1
...
...
arch/powerpc/include/asm/ppc-opcode.h
浏览文件 @
a12e4537
...
...
@@ -81,6 +81,53 @@
#define __REGA0_R30 30
#define __REGA0_R31 31
/* opcode and xopcode for instructions */
#define OP_TRAP 3
#define OP_TRAP_64 2
#define OP_31_XOP_TRAP 4
#define OP_31_XOP_LWZX 23
#define OP_31_XOP_DCBST 54
#define OP_31_XOP_LWZUX 55
#define OP_31_XOP_TRAP_64 68
#define OP_31_XOP_DCBF 86
#define OP_31_XOP_LBZX 87
#define OP_31_XOP_STWX 151
#define OP_31_XOP_STBX 215
#define OP_31_XOP_LBZUX 119
#define OP_31_XOP_STBUX 247
#define OP_31_XOP_LHZX 279
#define OP_31_XOP_LHZUX 311
#define OP_31_XOP_MFSPR 339
#define OP_31_XOP_LHAX 343
#define OP_31_XOP_LHAUX 375
#define OP_31_XOP_STHX 407
#define OP_31_XOP_STHUX 439
#define OP_31_XOP_MTSPR 467
#define OP_31_XOP_DCBI 470
#define OP_31_XOP_LWBRX 534
#define OP_31_XOP_TLBSYNC 566
#define OP_31_XOP_STWBRX 662
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_STHBRX 918
#define OP_LWZ 32
#define OP_LD 58
#define OP_LWZU 33
#define OP_LBZ 34
#define OP_LBZU 35
#define OP_STW 36
#define OP_STWU 37
#define OP_STD 62
#define OP_STB 38
#define OP_STBU 39
#define OP_LHZ 40
#define OP_LHZU 41
#define OP_LHA 42
#define OP_LHAU 43
#define OP_STH 44
#define OP_STHU 45
/* sorted alphabetically */
#define PPC_INST_BHRBE 0x7c00025c
#define PPC_INST_CLRBHRB 0x7c00035c
...
...
arch/powerpc/include/asm/reg_fsl_emb.h
浏览文件 @
a12e4537
...
...
@@ -17,12 +17,16 @@
/* Freescale Book E Performance Monitor APU Registers */
#define PMRN_PMC0 0x010
/* Performance Monitor Counter 0 */
#define PMRN_PMC1 0x011
/* Performance Monitor Counter 1 */
#define PMRN_PMC2 0x012
/* Performance Monitor Counter 1 */
#define PMRN_PMC3 0x013
/* Performance Monitor Counter 1 */
#define PMRN_PMC2 0x012
/* Performance Monitor Counter 2 */
#define PMRN_PMC3 0x013
/* Performance Monitor Counter 3 */
#define PMRN_PMC4 0x014
/* Performance Monitor Counter 4 */
#define PMRN_PMC5 0x015
/* Performance Monitor Counter 5 */
#define PMRN_PMLCA0 0x090
/* PM Local Control A0 */
#define PMRN_PMLCA1 0x091
/* PM Local Control A1 */
#define PMRN_PMLCA2 0x092
/* PM Local Control A2 */
#define PMRN_PMLCA3 0x093
/* PM Local Control A3 */
#define PMRN_PMLCA4 0x094
/* PM Local Control A4 */
#define PMRN_PMLCA5 0x095
/* PM Local Control A5 */
#define PMLCA_FC 0x80000000
/* Freeze Counter */
#define PMLCA_FCS 0x40000000
/* Freeze in Supervisor */
...
...
@@ -30,14 +34,18 @@
#define PMLCA_FCM1 0x10000000
/* Freeze when PMM==1 */
#define PMLCA_FCM0 0x08000000
/* Freeze when PMM==0 */
#define PMLCA_CE 0x04000000
/* Condition Enable */
#define PMLCA_FGCS1 0x00000002
/* Freeze in guest state */
#define PMLCA_FGCS0 0x00000001
/* Freeze in hypervisor state */
#define PMLCA_EVENT_MASK 0x0
0
ff0000
/* Event field */
#define PMLCA_EVENT_MASK 0x0
1
ff0000
/* Event field */
#define PMLCA_EVENT_SHIFT 16
#define PMRN_PMLCB0 0x110
/* PM Local Control B0 */
#define PMRN_PMLCB1 0x111
/* PM Local Control B1 */
#define PMRN_PMLCB2 0x112
/* PM Local Control B2 */
#define PMRN_PMLCB3 0x113
/* PM Local Control B3 */
#define PMRN_PMLCB4 0x114
/* PM Local Control B4 */
#define PMRN_PMLCB5 0x115
/* PM Local Control B5 */
#define PMLCB_THRESHMUL_MASK 0x0700
/* Threshold Multiple Field */
#define PMLCB_THRESHMUL_SHIFT 8
...
...
@@ -55,16 +63,22 @@
#define PMRN_UPMC0 0x000
/* User Performance Monitor Counter 0 */
#define PMRN_UPMC1 0x001
/* User Performance Monitor Counter 1 */
#define PMRN_UPMC2 0x002
/* User Performance Monitor Counter 1 */
#define PMRN_UPMC3 0x003
/* User Performance Monitor Counter 1 */
#define PMRN_UPMC2 0x002
/* User Performance Monitor Counter 2 */
#define PMRN_UPMC3 0x003
/* User Performance Monitor Counter 3 */
#define PMRN_UPMC4 0x004
/* User Performance Monitor Counter 4 */
#define PMRN_UPMC5 0x005
/* User Performance Monitor Counter 5 */
#define PMRN_UPMLCA0 0x080
/* User PM Local Control A0 */
#define PMRN_UPMLCA1 0x081
/* User PM Local Control A1 */
#define PMRN_UPMLCA2 0x082
/* User PM Local Control A2 */
#define PMRN_UPMLCA3 0x083
/* User PM Local Control A3 */
#define PMRN_UPMLCA4 0x084
/* User PM Local Control A4 */
#define PMRN_UPMLCA5 0x085
/* User PM Local Control A5 */
#define PMRN_UPMLCB0 0x100
/* User PM Local Control B0 */
#define PMRN_UPMLCB1 0x101
/* User PM Local Control B1 */
#define PMRN_UPMLCB2 0x102
/* User PM Local Control B2 */
#define PMRN_UPMLCB3 0x103
/* User PM Local Control B3 */
#define PMRN_UPMLCB4 0x104
/* User PM Local Control B4 */
#define PMRN_UPMLCB5 0x105
/* User PM Local Control B5 */
#define PMRN_UPMGC0 0x180
/* User PM Global Control 0 */
...
...
arch/powerpc/kernel/cpu_setup_fsl_booke.S
浏览文件 @
a12e4537
...
...
@@ -75,7 +75,7 @@ _GLOBAL(__setup_cpu_e500v2)
bl
__e500_icache_setup
bl
__e500_dcache_setup
bl
__setup_e500_ivors
#if
def CONFIG_FSL_RIO
#if
defined(CONFIG_FSL_RIO) || defined(CONFIG_FSL_PCI)
/
*
Ensure
that
RFXE
is
set
*/
mfspr
r3
,
SPRN_HID1
oris
r3
,
r3
,
HID1_RFXE
@
h
...
...
arch/powerpc/kernel/cputable.c
浏览文件 @
a12e4537
...
...
@@ -2105,7 +2105,7 @@ static struct cpu_spec __initdata cpu_specs[] = {
MMU_FTR_USE_TLBILX
,
.
icache_bsize
=
64
,
.
dcache_bsize
=
64
,
.
num_pmcs
=
4
,
.
num_pmcs
=
6
,
.
oprofile_cpu_type
=
"ppc/e6500"
,
.
oprofile_type
=
PPC_OPROFILE_FSL_EMB
,
.
cpu_setup
=
__setup_cpu_e6500
,
...
...
arch/powerpc/kernel/epapr_paravirt.c
浏览文件 @
a12e4537
...
...
@@ -30,22 +30,20 @@ extern u32 epapr_ev_idle_start[];
bool
epapr_paravirt_enabled
;
static
int
__init
epapr_paravirt_init
(
void
)
static
int
__init
early_init_dt_scan_epapr
(
unsigned
long
node
,
const
char
*
uname
,
int
depth
,
void
*
data
)
{
struct
device_node
*
hyper_node
;
const
u32
*
insts
;
int
len
,
i
;
unsigned
long
len
;
int
i
;
hyper_node
=
of_find_node_by_path
(
"/hypervisor"
);
if
(
!
hyper_node
)
return
-
ENODEV
;
insts
=
of_get_property
(
hyper_node
,
"hcall-instructions"
,
&
len
);
insts
=
of_get_flat_dt_prop
(
node
,
"hcall-instructions"
,
&
len
);
if
(
!
insts
)
return
-
ENODEV
;
return
0
;
if
(
len
%
4
||
len
>
(
4
*
4
))
return
-
ENODEV
;
return
-
1
;
for
(
i
=
0
;
i
<
(
len
/
4
);
i
++
)
{
patch_instruction
(
epapr_hypercall_start
+
i
,
insts
[
i
]);
...
...
@@ -55,13 +53,19 @@ static int __init epapr_paravirt_init(void)
}
#if !defined(CONFIG_64BIT) || defined(CONFIG_PPC_BOOK3E_64)
if
(
of_get_
property
(
hyper_
node
,
"has-idle"
,
NULL
))
if
(
of_get_
flat_dt_prop
(
node
,
"has-idle"
,
NULL
))
ppc_md
.
power_save
=
epapr_ev_idle
;
#endif
epapr_paravirt_enabled
=
true
;
return
1
;
}
int
__init
epapr_paravirt_early_init
(
void
)
{
of_scan_flat_dt
(
early_init_dt_scan_epapr
,
NULL
);
return
0
;
}
early_initcall
(
epapr_paravirt_init
);
arch/powerpc/kernel/setup_32.c
浏览文件 @
a12e4537
...
...
@@ -38,6 +38,7 @@
#include <asm/serial.h>
#include <asm/udbg.h>
#include <asm/mmu_context.h>
#include <asm/epapr_hcalls.h>
#include "setup.h"
...
...
@@ -128,6 +129,8 @@ notrace void __init machine_init(u64 dt_ptr)
/* Do some early initialization based on the flat device tree */
early_init_devtree
(
__va
(
dt_ptr
));
epapr_paravirt_early_init
();
early_init_mmu
();
probe_machine
();
...
...
@@ -326,5 +329,4 @@ void __init setup_arch(char **cmdline_p)
/* Initialize the MMU context management stuff */
mmu_context_init
();
}
arch/powerpc/kernel/setup_64.c
浏览文件 @
a12e4537
...
...
@@ -66,6 +66,7 @@
#include <asm/code-patching.h>
#include <asm/kvm_ppc.h>
#include <asm/hugetlb.h>
#include <asm/epapr_hcalls.h>
#include "setup.h"
...
...
@@ -215,6 +216,8 @@ void __init early_setup(unsigned long dt_ptr)
*/
early_init_devtree
(
__va
(
dt_ptr
));
epapr_paravirt_early_init
();
/* Now we know the logical id of our boot cpu, setup the paca. */
setup_paca
(
&
paca
[
boot_cpuid
]);
fixup_boot_paca
();
...
...
arch/powerpc/kernel/swsusp_booke.S
浏览文件 @
a12e4537
...
...
@@ -141,6 +141,14 @@ _GLOBAL(swsusp_arch_resume)
lis
r11
,
swsusp_save_area
@
h
ori
r11
,
r11
,
swsusp_save_area
@
l
/
*
*
Mappings
from
virtual
addresses
to
physical
addresses
may
be
*
different
than
they
were
prior
to
restoring
hibernation
state
.
*
Invalidate
the
TLB
so
that
the
boot
CPU
is
using
the
new
*
mappings
.
*/
bl
_tlbil_all
lwz
r4
,
SL_SPRG0
(
r11
)
mtsprg
0
,
r4
lwz
r4
,
SL_SPRG1
(
r11
)
...
...
arch/powerpc/kernel/traps.c
浏览文件 @
a12e4537
...
...
@@ -62,6 +62,7 @@
#include <asm/switch_to.h>
#include <asm/tm.h>
#include <asm/debug.h>
#include <sysdev/fsl_pci.h>
#if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
int
(
*
__debugger
)(
struct
pt_regs
*
regs
)
__read_mostly
;
...
...
@@ -567,6 +568,8 @@ int machine_check_e500(struct pt_regs *regs)
if
(
reason
&
MCSR_BUS_RBERR
)
{
if
(
fsl_rio_mcheck_exception
(
regs
))
return
1
;
if
(
fsl_pci_mcheck_exception
(
regs
))
return
1
;
}
printk
(
"Machine check in kernel mode.
\n
"
);
...
...
arch/powerpc/kvm/emulate.c
浏览文件 @
a12e4537
...
...
@@ -30,53 +30,10 @@
#include <asm/byteorder.h>
#include <asm/kvm_ppc.h>
#include <asm/disassemble.h>
#include <asm/ppc-opcode.h>
#include "timing.h"
#include "trace.h"
#define OP_TRAP 3
#define OP_TRAP_64 2
#define OP_31_XOP_TRAP 4
#define OP_31_XOP_LWZX 23
#define OP_31_XOP_DCBST 54
#define OP_31_XOP_TRAP_64 68
#define OP_31_XOP_DCBF 86
#define OP_31_XOP_LBZX 87
#define OP_31_XOP_STWX 151
#define OP_31_XOP_STBX 215
#define OP_31_XOP_LBZUX 119
#define OP_31_XOP_STBUX 247
#define OP_31_XOP_LHZX 279
#define OP_31_XOP_LHZUX 311
#define OP_31_XOP_MFSPR 339
#define OP_31_XOP_LHAX 343
#define OP_31_XOP_STHX 407
#define OP_31_XOP_STHUX 439
#define OP_31_XOP_MTSPR 467
#define OP_31_XOP_DCBI 470
#define OP_31_XOP_LWBRX 534
#define OP_31_XOP_TLBSYNC 566
#define OP_31_XOP_STWBRX 662
#define OP_31_XOP_LHBRX 790
#define OP_31_XOP_STHBRX 918
#define OP_LWZ 32
#define OP_LD 58
#define OP_LWZU 33
#define OP_LBZ 34
#define OP_LBZU 35
#define OP_STW 36
#define OP_STWU 37
#define OP_STD 62
#define OP_STB 38
#define OP_STBU 39
#define OP_LHZ 40
#define OP_LHZU 41
#define OP_LHA 42
#define OP_LHAU 43
#define OP_STH 44
#define OP_STHU 45
void
kvmppc_emulate_dec
(
struct
kvm_vcpu
*
vcpu
)
{
unsigned
long
dec_nsec
;
...
...
arch/powerpc/oprofile/op_model_fsl_emb.c
浏览文件 @
a12e4537
...
...
@@ -46,6 +46,12 @@ static inline u32 get_pmlca(int ctr)
case
3
:
pmlca
=
mfpmr
(
PMRN_PMLCA3
);
break
;
case
4
:
pmlca
=
mfpmr
(
PMRN_PMLCA4
);
break
;
case
5
:
pmlca
=
mfpmr
(
PMRN_PMLCA5
);
break
;
default:
panic
(
"Bad ctr number
\n
"
);
}
...
...
@@ -68,6 +74,12 @@ static inline void set_pmlca(int ctr, u32 pmlca)
case
3
:
mtpmr
(
PMRN_PMLCA3
,
pmlca
);
break
;
case
4
:
mtpmr
(
PMRN_PMLCA4
,
pmlca
);
break
;
case
5
:
mtpmr
(
PMRN_PMLCA5
,
pmlca
);
break
;
default:
panic
(
"Bad ctr number
\n
"
);
}
...
...
@@ -84,6 +96,10 @@ static inline unsigned int ctr_read(unsigned int i)
return
mfpmr
(
PMRN_PMC2
);
case
3
:
return
mfpmr
(
PMRN_PMC3
);
case
4
:
return
mfpmr
(
PMRN_PMC4
);
case
5
:
return
mfpmr
(
PMRN_PMC5
);
default:
return
0
;
}
...
...
@@ -104,6 +120,12 @@ static inline void ctr_write(unsigned int i, unsigned int val)
case
3
:
mtpmr
(
PMRN_PMC3
,
val
);
break
;
case
4
:
mtpmr
(
PMRN_PMC4
,
val
);
break
;
case
5
:
mtpmr
(
PMRN_PMC5
,
val
);
break
;
default:
break
;
}
...
...
@@ -133,6 +155,14 @@ static void init_pmc_stop(int ctr)
mtpmr
(
PMRN_PMLCA3
,
pmlca
);
mtpmr
(
PMRN_PMLCB3
,
pmlcb
);
break
;
case
4
:
mtpmr
(
PMRN_PMLCA4
,
pmlca
);
mtpmr
(
PMRN_PMLCB4
,
pmlcb
);
break
;
case
5
:
mtpmr
(
PMRN_PMLCA5
,
pmlca
);
mtpmr
(
PMRN_PMLCB5
,
pmlcb
);
break
;
default:
panic
(
"Bad ctr number!
\n
"
);
}
...
...
arch/powerpc/perf/Makefile
浏览文件 @
a12e4537
...
...
@@ -9,7 +9,7 @@ obj64-$(CONFIG_PPC_PERF_CTRS) += power4-pmu.o ppc970-pmu.o power5-pmu.o \
obj32-$(CONFIG_PPC_PERF_CTRS)
+=
mpc7450-pmu.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT)
+=
core-fsl-emb.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500)
+=
e500-pmu.o
obj-$(CONFIG_FSL_EMB_PERF_EVENT_E500)
+=
e500-pmu.o
e6500-pmu.o
obj-$(CONFIG_PPC64)
+=
$
(
obj64-y
)
obj-$(CONFIG_PPC32)
+=
$
(
obj32-y
)
arch/powerpc/perf/core-fsl-emb.c
浏览文件 @
a12e4537
...
...
@@ -70,6 +70,12 @@ static unsigned long read_pmc(int idx)
case
3
:
val
=
mfpmr
(
PMRN_PMC3
);
break
;
case
4
:
val
=
mfpmr
(
PMRN_PMC4
);
break
;
case
5
:
val
=
mfpmr
(
PMRN_PMC5
);
break
;
default:
printk
(
KERN_ERR
"oops trying to read PMC%d
\n
"
,
idx
);
val
=
0
;
...
...
@@ -95,6 +101,12 @@ static void write_pmc(int idx, unsigned long val)
case
3
:
mtpmr
(
PMRN_PMC3
,
val
);
break
;
case
4
:
mtpmr
(
PMRN_PMC4
,
val
);
break
;
case
5
:
mtpmr
(
PMRN_PMC5
,
val
);
break
;
default:
printk
(
KERN_ERR
"oops trying to write PMC%d
\n
"
,
idx
);
}
...
...
@@ -120,6 +132,12 @@ static void write_pmlca(int idx, unsigned long val)
case
3
:
mtpmr
(
PMRN_PMLCA3
,
val
);
break
;
case
4
:
mtpmr
(
PMRN_PMLCA4
,
val
);
break
;
case
5
:
mtpmr
(
PMRN_PMLCA5
,
val
);
break
;
default:
printk
(
KERN_ERR
"oops trying to write PMLCA%d
\n
"
,
idx
);
}
...
...
@@ -145,6 +163,12 @@ static void write_pmlcb(int idx, unsigned long val)
case
3
:
mtpmr
(
PMRN_PMLCB3
,
val
);
break
;
case
4
:
mtpmr
(
PMRN_PMLCB4
,
val
);
break
;
case
5
:
mtpmr
(
PMRN_PMLCB5
,
val
);
break
;
default:
printk
(
KERN_ERR
"oops trying to write PMLCB%d
\n
"
,
idx
);
}
...
...
@@ -462,6 +486,12 @@ static int fsl_emb_pmu_event_init(struct perf_event *event)
int
num_restricted
;
int
i
;
if
(
ppmu
->
n_counter
>
MAX_HWEVENTS
)
{
WARN
(
1
,
"No. of perf counters (%d) is higher than max array size(%d)
\n
"
,
ppmu
->
n_counter
,
MAX_HWEVENTS
);
ppmu
->
n_counter
=
MAX_HWEVENTS
;
}
switch
(
event
->
attr
.
type
)
{
case
PERF_TYPE_HARDWARE
:
ev
=
event
->
attr
.
config
;
...
...
arch/powerpc/perf/e6500-pmu.c
0 → 100644
浏览文件 @
a12e4537
/*
* Performance counter support for e6500 family processors.
*
* Author: Priyanka Jain, Priyanka.Jain@freescale.com
* Based on e500-pmu.c
* Copyright 2013 Freescale Semiconductor, Inc.
* Copyright 2008-2009 Paul Mackerras, IBM Corporation.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; either version
* 2 of the License, or (at your option) any later version.
*/
#include <linux/string.h>
#include <linux/perf_event.h>
#include <asm/reg.h>
#include <asm/cputable.h>
/*
* Map of generic hardware event types to hardware events
* Zero if unsupported
*/
static
int
e6500_generic_events
[]
=
{
[
PERF_COUNT_HW_CPU_CYCLES
]
=
1
,
[
PERF_COUNT_HW_INSTRUCTIONS
]
=
2
,
[
PERF_COUNT_HW_CACHE_MISSES
]
=
221
,
[
PERF_COUNT_HW_BRANCH_INSTRUCTIONS
]
=
12
,
[
PERF_COUNT_HW_BRANCH_MISSES
]
=
15
,
};
#define C(x) PERF_COUNT_HW_CACHE_##x
/*
* Table of generalized cache-related events.
* 0 means not supported, -1 means nonsensical, other values
* are event codes.
*/
static
int
e6500_cache_events
[
C
(
MAX
)][
C
(
OP_MAX
)][
C
(
RESULT_MAX
)]
=
{
[
C
(
L1D
)]
=
{
/*RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
27
,
222
},
[
C
(
OP_WRITE
)]
=
{
28
,
223
},
[
C
(
OP_PREFETCH
)]
=
{
29
,
0
},
},
[
C
(
L1I
)]
=
{
/*RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
2
,
254
},
[
C
(
OP_WRITE
)]
=
{
-
1
,
-
1
},
[
C
(
OP_PREFETCH
)]
=
{
37
,
0
},
},
/*
* Assuming LL means L2, it's not a good match for this model.
* It does not have separate read/write events (but it does have
* separate instruction/data events).
*/
[
C
(
LL
)]
=
{
/*RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
0
,
0
},
[
C
(
OP_WRITE
)]
=
{
0
,
0
},
[
C
(
OP_PREFETCH
)]
=
{
0
,
0
},
},
/*
* There are data/instruction MMU misses, but that's a miss on
* the chip's internal level-one TLB which is probably not
* what the user wants. Instead, unified level-two TLB misses
* are reported here.
*/
[
C
(
DTLB
)]
=
{
/*RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
26
,
66
},
[
C
(
OP_WRITE
)]
=
{
-
1
,
-
1
},
[
C
(
OP_PREFETCH
)]
=
{
-
1
,
-
1
},
},
[
C
(
BPU
)]
=
{
/*RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
12
,
15
},
[
C
(
OP_WRITE
)]
=
{
-
1
,
-
1
},
[
C
(
OP_PREFETCH
)]
=
{
-
1
,
-
1
},
},
[
C
(
NODE
)]
=
{
/* RESULT_ACCESS RESULT_MISS */
[
C
(
OP_READ
)]
=
{
-
1
,
-
1
},
[
C
(
OP_WRITE
)]
=
{
-
1
,
-
1
},
[
C
(
OP_PREFETCH
)]
=
{
-
1
,
-
1
},
},
};
static
int
num_events
=
512
;
/* Upper half of event id is PMLCb, for threshold events */
static
u64
e6500_xlate_event
(
u64
event_id
)
{
u32
event_low
=
(
u32
)
event_id
;
if
(
event_low
>=
num_events
||
(
event_id
&
(
FSL_EMB_EVENT_THRESHMUL
|
FSL_EMB_EVENT_THRESH
)))
return
0
;
return
FSL_EMB_EVENT_VALID
;
}
static
struct
fsl_emb_pmu
e6500_pmu
=
{
.
name
=
"e6500 family"
,
.
n_counter
=
6
,
.
n_restricted
=
0
,
.
xlate_event
=
e6500_xlate_event
,
.
n_generic
=
ARRAY_SIZE
(
e6500_generic_events
),
.
generic_events
=
e6500_generic_events
,
.
cache_events
=
&
e6500_cache_events
,
};
static
int
init_e6500_pmu
(
void
)
{
if
(
!
cur_cpu_spec
->
oprofile_cpu_type
||
strcmp
(
cur_cpu_spec
->
oprofile_cpu_type
,
"ppc/e6500"
))
return
-
ENODEV
;
return
register_fsl_emb_pmu
(
&
e6500_pmu
);
}
early_initcall
(
init_e6500_pmu
);
arch/powerpc/platforms/85xx/corenet_ds.c
浏览文件 @
a12e4537
...
...
@@ -53,12 +53,6 @@ void __init corenet_ds_setup_arch(void)
{
mpc85xx_smp_init
();
#if defined(CONFIG_PCI) && defined(CONFIG_PPC64)
pci_devs_phb_init
();
#endif
fsl_pci_assign_primary
();
swiotlb_detect_4g
();
pr_info
(
"%s board from Freescale Semiconductor
\n
"
,
ppc_md
.
name
);
...
...
arch/powerpc/platforms/85xx/mpc85xx_rdb.c
浏览文件 @
a12e4537
...
...
@@ -160,6 +160,7 @@ machine_arch_initcall(p2020_rdb_pc, mpc85xx_common_publish_devices);
machine_arch_initcall
(
p1020_mbg_pc
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1020_rdb
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1020_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1020_rdb_pd
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1020_utm_pc
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1021_rdb_pc
,
mpc85xx_common_publish_devices
);
machine_arch_initcall
(
p1025_rdb
,
mpc85xx_common_publish_devices
);
...
...
@@ -193,6 +194,13 @@ static int __init p1020_rdb_pc_probe(void)
return
of_flat_dt_is_compatible
(
root
,
"fsl,P1020RDB-PC"
);
}
static
int
__init
p1020_rdb_pd_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
return
of_flat_dt_is_compatible
(
root
,
"fsl,P1020RDB-PD"
);
}
static
int
__init
p1021_rdb_pc_probe
(
void
)
{
unsigned
long
root
=
of_get_flat_dt_root
();
...
...
@@ -351,6 +359,20 @@ define_machine(p1020_rdb_pc) {
.
progress
=
udbg_progress
,
};
define_machine
(
p1020_rdb_pd
)
{
.
name
=
"P1020RDB-PD"
,
.
probe
=
p1020_rdb_pd_probe
,
.
setup_arch
=
mpc85xx_rdb_setup_arch
,
.
init_IRQ
=
mpc85xx_rdb_pic_init
,
#ifdef CONFIG_PCI
.
pcibios_fixup_bus
=
fsl_pcibios_fixup_bus
,
#endif
.
get_irq
=
mpic_get_irq
,
.
restart
=
fsl_rstcr_restart
,
.
calibrate_decr
=
generic_calibrate_decr
,
.
progress
=
udbg_progress
,
};
define_machine
(
p1024_rdb
)
{
.
name
=
"P1024 RDB"
,
.
probe
=
p1024_rdb_probe
,
...
...
arch/powerpc/sysdev/fsl_msi.c
浏览文件 @
a12e4537
...
...
@@ -28,6 +28,18 @@
#include "fsl_msi.h"
#include "fsl_pci.h"
#define MSIIR_OFFSET_MASK 0xfffff
#define MSIIR_IBS_SHIFT 0
#define MSIIR_SRS_SHIFT 5
#define MSIIR1_IBS_SHIFT 4
#define MSIIR1_SRS_SHIFT 0
#define MSI_SRS_MASK 0xf
#define MSI_IBS_MASK 0x1f
#define msi_hwirq(msi, msir_index, intr_index) \
((msir_index) << (msi)->srs_shift | \
((intr_index) << (msi)->ibs_shift))
static
LIST_HEAD
(
msi_head
);
struct
fsl_msi_feature
{
...
...
@@ -80,18 +92,19 @@ static const struct irq_domain_ops fsl_msi_host_ops = {
static
int
fsl_msi_init_allocator
(
struct
fsl_msi
*
msi_data
)
{
int
rc
;
int
rc
,
hwirq
;
rc
=
msi_bitmap_alloc
(
&
msi_data
->
bitmap
,
NR_MSI_IRQS
,
rc
=
msi_bitmap_alloc
(
&
msi_data
->
bitmap
,
NR_MSI_IRQS
_MAX
,
msi_data
->
irqhost
->
of_node
);
if
(
rc
)
return
rc
;
rc
=
msi_bitmap_reserve_dt_hwirqs
(
&
msi_data
->
bitmap
);
if
(
rc
<
0
)
{
msi_bitmap_free
(
&
msi_data
->
bitmap
);
return
rc
;
}
/*
* Reserve all the hwirqs
* The available hwirqs will be released in fsl_msi_setup_hwirq()
*/
for
(
hwirq
=
0
;
hwirq
<
NR_MSI_IRQS_MAX
;
hwirq
++
)
msi_bitmap_reserve_hwirq
(
&
msi_data
->
bitmap
,
hwirq
);
return
0
;
}
...
...
@@ -144,8 +157,9 @@ static void fsl_compose_msi_msg(struct pci_dev *pdev, int hwirq,
msg
->
data
=
hwirq
;
pr_debug
(
"%s: allocated srs: %d, ibs: %d
\n
"
,
__func__
,
hwirq
/
IRQS_PER_MSI_REG
,
hwirq
%
IRQS_PER_MSI_REG
);
pr_debug
(
"%s: allocated srs: %d, ibs: %d
\n
"
,
__func__
,
(
hwirq
>>
msi_data
->
srs_shift
)
&
MSI_SRS_MASK
,
(
hwirq
>>
msi_data
->
ibs_shift
)
&
MSI_IBS_MASK
);
}
static
int
fsl_setup_msi_irqs
(
struct
pci_dev
*
pdev
,
int
nvec
,
int
type
)
...
...
@@ -255,7 +269,7 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
msir_index
=
cascade_data
->
index
;
if
(
msir_index
>=
NR_MSI_REG
)
if
(
msir_index
>=
NR_MSI_REG
_MAX
)
cascade_irq
=
NO_IRQ
;
irqd_set_chained_irq_inprogress
(
idata
);
...
...
@@ -285,8 +299,8 @@ static void fsl_msi_cascade(unsigned int irq, struct irq_desc *desc)
intr_index
=
ffs
(
msir_value
)
-
1
;
cascade_irq
=
irq_linear_revmap
(
msi_data
->
irqhost
,
msi
r_index
*
IRQS_PER_MSI_REG
+
intr_index
+
have_shift
);
msi
_hwirq
(
msi_data
,
msir_index
,
intr_index
+
have_shift
)
);
if
(
cascade_irq
!=
NO_IRQ
)
generic_handle_irq
(
cascade_irq
);
have_shift
+=
intr_index
+
1
;
...
...
@@ -316,7 +330,7 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
if
(
msi
->
list
.
prev
!=
NULL
)
list_del
(
&
msi
->
list
);
for
(
i
=
0
;
i
<
NR_MSI_REG
;
i
++
)
{
for
(
i
=
0
;
i
<
NR_MSI_REG
_MAX
;
i
++
)
{
virq
=
msi
->
msi_virqs
[
i
];
if
(
virq
!=
NO_IRQ
)
{
cascade_data
=
irq_get_handler_data
(
virq
);
...
...
@@ -339,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
int
offset
,
int
irq_index
)
{
struct
fsl_msi_cascade_data
*
cascade_data
=
NULL
;
int
virt_msir
;
int
virt_msir
,
i
;
virt_msir
=
irq_of_parse_and_map
(
dev
->
dev
.
of_node
,
irq_index
);
if
(
virt_msir
==
NO_IRQ
)
{
...
...
@@ -360,6 +374,11 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
irq_set_handler_data
(
virt_msir
,
cascade_data
);
irq_set_chained_handler
(
virt_msir
,
fsl_msi_cascade
);
/* Release the hwirqs corresponding to this MSI register */
for
(
i
=
0
;
i
<
IRQS_PER_MSI_REG
;
i
++
)
msi_bitmap_free_hwirqs
(
&
msi
->
bitmap
,
msi_hwirq
(
msi
,
offset
,
i
),
1
);
return
0
;
}
...
...
@@ -368,14 +387,12 @@ static int fsl_of_msi_probe(struct platform_device *dev)
{
const
struct
of_device_id
*
match
;
struct
fsl_msi
*
msi
;
struct
resource
res
;
struct
resource
res
,
msiir
;
int
err
,
i
,
j
,
irq_index
,
count
;
int
rc
;
const
u32
*
p
;
const
struct
fsl_msi_feature
*
features
;
int
len
;
u32
offset
;
static
const
u32
all_avail
[]
=
{
0
,
NR_MSI_IRQS
};
match
=
of_match_device
(
fsl_of_msi_ids
,
&
dev
->
dev
);
if
(
!
match
)
...
...
@@ -392,7 +409,7 @@ static int fsl_of_msi_probe(struct platform_device *dev)
platform_set_drvdata
(
dev
,
msi
);
msi
->
irqhost
=
irq_domain_add_linear
(
dev
->
dev
.
of_node
,
NR_MSI_IRQS
,
&
fsl_msi_host_ops
,
msi
);
NR_MSI_IRQS
_MAX
,
&
fsl_msi_host_ops
,
msi
);
if
(
msi
->
irqhost
==
NULL
)
{
dev_err
(
&
dev
->
dev
,
"No memory for MSI irqhost
\n
"
);
...
...
@@ -421,6 +438,16 @@ static int fsl_of_msi_probe(struct platform_device *dev)
}
msi
->
msiir_offset
=
features
->
msiir_offset
+
(
res
.
start
&
0xfffff
);
/*
* First read the MSIIR/MSIIR1 offset from dts
* On failure use the hardcode MSIIR offset
*/
if
(
of_address_to_resource
(
dev
->
dev
.
of_node
,
1
,
&
msiir
))
msi
->
msiir_offset
=
features
->
msiir_offset
+
(
res
.
start
&
MSIIR_OFFSET_MASK
);
else
msi
->
msiir_offset
=
msiir
.
start
&
MSIIR_OFFSET_MASK
;
}
msi
->
feature
=
features
->
fsl_pic_ip
;
...
...
@@ -431,42 +458,66 @@ static int fsl_of_msi_probe(struct platform_device *dev)
*/
msi
->
phandle
=
dev
->
dev
.
of_node
->
phandle
;
rc
=
fsl_msi_init_allocator
(
msi
);
if
(
rc
)
{
err
=
fsl_msi_init_allocator
(
msi
);
if
(
err
)
{
dev_err
(
&
dev
->
dev
,
"Error allocating MSI bitmap
\n
"
);
goto
error_out
;
}
p
=
of_get_property
(
dev
->
dev
.
of_node
,
"msi-available-ranges"
,
&
len
);
if
(
p
&&
len
%
(
2
*
sizeof
(
u32
))
!=
0
)
{
dev_err
(
&
dev
->
dev
,
"%s: Malformed msi-available-ranges property
\n
"
,
__func__
);
err
=
-
EINVAL
;
goto
error_out
;
}
if
(
!
p
)
{
p
=
all_avail
;
len
=
sizeof
(
all_avail
);
}
if
(
of_device_is_compatible
(
dev
->
dev
.
of_node
,
"fsl,mpic-msi-v4.3"
))
{
msi
->
srs_shift
=
MSIIR1_SRS_SHIFT
;
msi
->
ibs_shift
=
MSIIR1_IBS_SHIFT
;
if
(
p
)
dev_warn
(
&
dev
->
dev
,
"%s: dose not support msi-available-ranges property
\n
"
,
__func__
);
for
(
irq_index
=
0
;
irq_index
<
NR_MSI_REG_MSIIR1
;
irq_index
++
)
{
err
=
fsl_msi_setup_hwirq
(
msi
,
dev
,
irq_index
,
irq_index
);
if
(
err
)
goto
error_out
;
}
}
else
{
static
const
u32
all_avail
[]
=
{
0
,
NR_MSI_REG_MSIIR
*
IRQS_PER_MSI_REG
};
for
(
irq_index
=
0
,
i
=
0
;
i
<
len
/
(
2
*
sizeof
(
u32
));
i
++
)
{
if
(
p
[
i
*
2
]
%
IRQS_PER_MSI_REG
||
p
[
i
*
2
+
1
]
%
IRQS_PER_MSI_REG
)
{
printk
(
KERN_WARNING
"%s: %s: msi available range of %u at %u is not IRQ-aligned
\n
"
,
__func__
,
dev
->
dev
.
of_node
->
full_name
,
p
[
i
*
2
+
1
],
p
[
i
*
2
]
);
msi
->
srs_shift
=
MSIIR_SRS_SHIFT
;
msi
->
ibs_shift
=
MSIIR_IBS_SHIFT
;
if
(
p
&&
len
%
(
2
*
sizeof
(
u32
))
!=
0
)
{
dev_err
(
&
dev
->
dev
,
"%s: Malformed msi-available-ranges property
\n
"
,
__func__
);
err
=
-
EINVAL
;
goto
error_out
;
}
offset
=
p
[
i
*
2
]
/
IRQS_PER_MSI_REG
;
count
=
p
[
i
*
2
+
1
]
/
IRQS_PER_MSI_REG
;
if
(
!
p
)
{
p
=
all_avail
;
len
=
sizeof
(
all_avail
);
}
for
(
j
=
0
;
j
<
count
;
j
++
,
irq_index
++
)
{
err
=
fsl_msi_setup_hwirq
(
msi
,
dev
,
offset
+
j
,
irq_index
);
if
(
err
)
for
(
irq_index
=
0
,
i
=
0
;
i
<
len
/
(
2
*
sizeof
(
u32
));
i
++
)
{
if
(
p
[
i
*
2
]
%
IRQS_PER_MSI_REG
||
p
[
i
*
2
+
1
]
%
IRQS_PER_MSI_REG
)
{
pr_warn
(
"%s: %s: msi available range of %u at %u is not IRQ-aligned
\n
"
,
__func__
,
dev
->
dev
.
of_node
->
full_name
,
p
[
i
*
2
+
1
],
p
[
i
*
2
]);
err
=
-
EINVAL
;
goto
error_out
;
}
offset
=
p
[
i
*
2
]
/
IRQS_PER_MSI_REG
;
count
=
p
[
i
*
2
+
1
]
/
IRQS_PER_MSI_REG
;
for
(
j
=
0
;
j
<
count
;
j
++
,
irq_index
++
)
{
err
=
fsl_msi_setup_hwirq
(
msi
,
dev
,
offset
+
j
,
irq_index
);
if
(
err
)
goto
error_out
;
}
}
}
...
...
@@ -508,6 +559,10 @@ static const struct of_device_id fsl_of_msi_ids[] = {
.
compatible
=
"fsl,mpic-msi"
,
.
data
=
&
mpic_msi_feature
,
},
{
.
compatible
=
"fsl,mpic-msi-v4.3"
,
.
data
=
&
mpic_msi_feature
,
},
{
.
compatible
=
"fsl,ipic-msi"
,
.
data
=
&
ipic_msi_feature
,
...
...
arch/powerpc/sysdev/fsl_msi.h
浏览文件 @
a12e4537
...
...
@@ -16,9 +16,11 @@
#include <linux/of.h>
#include <asm/msi_bitmap.h>
#define NR_MSI_REG 8
#define NR_MSI_REG_MSIIR 8
/* MSIIR can index 8 MSI registers */
#define NR_MSI_REG_MSIIR1 16
/* MSIIR1 can index 16 MSI registers */
#define NR_MSI_REG_MAX NR_MSI_REG_MSIIR1
#define IRQS_PER_MSI_REG 32
#define NR_MSI_IRQS
(NR_MSI_REG
* IRQS_PER_MSI_REG)
#define NR_MSI_IRQS
_MAX (NR_MSI_REG_MAX
* IRQS_PER_MSI_REG)
#define FSL_PIC_IP_MASK 0x0000000F
#define FSL_PIC_IP_MPIC 0x00000001
...
...
@@ -31,9 +33,11 @@ struct fsl_msi {
unsigned
long
cascade_irq
;
u32
msiir_offset
;
/* Offset of MSIIR, relative to start of CCSR */
u32
ibs_shift
;
/* Shift of interrupt bit select */
u32
srs_shift
;
/* Shift of the shared interrupt register select */
void
__iomem
*
msi_regs
;
u32
feature
;
int
msi_virqs
[
NR_MSI_REG
];
int
msi_virqs
[
NR_MSI_REG
_MAX
];
struct
msi_bitmap
bitmap
;
...
...
arch/powerpc/sysdev/fsl_pci.c
浏览文件 @
a12e4537
...
...
@@ -26,11 +26,15 @@
#include <linux/memblock.h>
#include <linux/log2.h>
#include <linux/slab.h>
#include <linux/uaccess.h>
#include <asm/io.h>
#include <asm/prom.h>
#include <asm/pci-bridge.h>
#include <asm/ppc-pci.h>
#include <asm/machdep.h>
#include <asm/disassemble.h>
#include <asm/ppc-opcode.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
...
...
@@ -64,7 +68,7 @@ static int fsl_pcie_check_link(struct pci_controller *hose)
if
(
hose
->
indirect_type
&
PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK
)
{
if
(
hose
->
ops
->
read
==
fsl_indirect_read_config
)
{
struct
pci_bus
bus
;
bus
.
number
=
0
;
bus
.
number
=
hose
->
first_busno
;
bus
.
sysdata
=
hose
;
bus
.
ops
=
hose
->
ops
;
indirect_read_config
(
&
bus
,
0
,
PCIE_LTSSM
,
4
,
&
val
);
...
...
@@ -297,10 +301,10 @@ static void setup_pci_atmu(struct pci_controller *hose)
if
(
early_find_capability
(
hose
,
0
,
0
,
PCI_CAP_ID_EXP
))
{
/* Size window to exact size if power-of-two or one size up */
if
((
1ull
<<
mem_log
)
!=
mem
)
{
mem_log
++
;
if
((
1ull
<<
mem_log
)
>
mem
)
pr_info
(
"%s: Setting PCI inbound window "
"greater than memory size
\n
"
,
name
);
mem_log
++
;
}
piwar
|=
((
mem_log
-
1
)
&
PIWAR_SZ_MASK
);
...
...
@@ -373,7 +377,9 @@ static void setup_pci_atmu(struct pci_controller *hose)
}
if
(
hose
->
dma_window_size
<
mem
)
{
#ifndef CONFIG_SWIOTLB
#ifdef CONFIG_SWIOTLB
ppc_swiotlb_enable
=
1
;
#else
pr_err
(
"%s: ERROR: Memory size exceeds PCI ATMU ability to "
"map - enable CONFIG_SWIOTLB to avoid dma errors.
\n
"
,
name
);
...
...
@@ -868,6 +874,160 @@ u64 fsl_pci_immrbar_base(struct pci_controller *hose)
return
0
;
}
#ifdef CONFIG_E500
static
int
mcheck_handle_load
(
struct
pt_regs
*
regs
,
u32
inst
)
{
unsigned
int
rd
,
ra
,
rb
,
d
;
rd
=
get_rt
(
inst
);
ra
=
get_ra
(
inst
);
rb
=
get_rb
(
inst
);
d
=
get_d
(
inst
);
switch
(
get_op
(
inst
))
{
case
31
:
switch
(
get_xop
(
inst
))
{
case
OP_31_XOP_LWZX
:
case
OP_31_XOP_LWBRX
:
regs
->
gpr
[
rd
]
=
0xffffffff
;
break
;
case
OP_31_XOP_LWZUX
:
regs
->
gpr
[
rd
]
=
0xffffffff
;
regs
->
gpr
[
ra
]
+=
regs
->
gpr
[
rb
];
break
;
case
OP_31_XOP_LBZX
:
regs
->
gpr
[
rd
]
=
0xff
;
break
;
case
OP_31_XOP_LBZUX
:
regs
->
gpr
[
rd
]
=
0xff
;
regs
->
gpr
[
ra
]
+=
regs
->
gpr
[
rb
];
break
;
case
OP_31_XOP_LHZX
:
case
OP_31_XOP_LHBRX
:
regs
->
gpr
[
rd
]
=
0xffff
;
break
;
case
OP_31_XOP_LHZUX
:
regs
->
gpr
[
rd
]
=
0xffff
;
regs
->
gpr
[
ra
]
+=
regs
->
gpr
[
rb
];
break
;
case
OP_31_XOP_LHAX
:
regs
->
gpr
[
rd
]
=
~
0UL
;
break
;
case
OP_31_XOP_LHAUX
:
regs
->
gpr
[
rd
]
=
~
0UL
;
regs
->
gpr
[
ra
]
+=
regs
->
gpr
[
rb
];
break
;
default:
return
0
;
}
break
;
case
OP_LWZ
:
regs
->
gpr
[
rd
]
=
0xffffffff
;
break
;
case
OP_LWZU
:
regs
->
gpr
[
rd
]
=
0xffffffff
;
regs
->
gpr
[
ra
]
+=
(
s16
)
d
;
break
;
case
OP_LBZ
:
regs
->
gpr
[
rd
]
=
0xff
;
break
;
case
OP_LBZU
:
regs
->
gpr
[
rd
]
=
0xff
;
regs
->
gpr
[
ra
]
+=
(
s16
)
d
;
break
;
case
OP_LHZ
:
regs
->
gpr
[
rd
]
=
0xffff
;
break
;
case
OP_LHZU
:
regs
->
gpr
[
rd
]
=
0xffff
;
regs
->
gpr
[
ra
]
+=
(
s16
)
d
;
break
;
case
OP_LHA
:
regs
->
gpr
[
rd
]
=
~
0UL
;
break
;
case
OP_LHAU
:
regs
->
gpr
[
rd
]
=
~
0UL
;
regs
->
gpr
[
ra
]
+=
(
s16
)
d
;
break
;
default:
return
0
;
}
return
1
;
}
static
int
is_in_pci_mem_space
(
phys_addr_t
addr
)
{
struct
pci_controller
*
hose
;
struct
resource
*
res
;
int
i
;
list_for_each_entry
(
hose
,
&
hose_list
,
list_node
)
{
if
(
!
(
hose
->
indirect_type
&
PPC_INDIRECT_TYPE_EXT_REG
))
continue
;
for
(
i
=
0
;
i
<
3
;
i
++
)
{
res
=
&
hose
->
mem_resources
[
i
];
if
((
res
->
flags
&
IORESOURCE_MEM
)
&&
addr
>=
res
->
start
&&
addr
<=
res
->
end
)
return
1
;
}
}
return
0
;
}
int
fsl_pci_mcheck_exception
(
struct
pt_regs
*
regs
)
{
u32
inst
;
int
ret
;
phys_addr_t
addr
=
0
;
/* Let KVM/QEMU deal with the exception */
if
(
regs
->
msr
&
MSR_GS
)
return
0
;
#ifdef CONFIG_PHYS_64BIT
addr
=
mfspr
(
SPRN_MCARU
);
addr
<<=
32
;
#endif
addr
+=
mfspr
(
SPRN_MCAR
);
if
(
is_in_pci_mem_space
(
addr
))
{
if
(
user_mode
(
regs
))
{
pagefault_disable
();
ret
=
get_user
(
regs
->
nip
,
&
inst
);
pagefault_enable
();
}
else
{
ret
=
probe_kernel_address
(
regs
->
nip
,
inst
);
}
if
(
mcheck_handle_load
(
regs
,
inst
))
{
regs
->
nip
+=
4
;
return
1
;
}
}
return
0
;
}
#endif
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
static
const
struct
of_device_id
pci_ids
[]
=
{
{
.
compatible
=
"fsl,mpc8540-pci"
,
},
...
...
@@ -928,28 +1088,10 @@ static int fsl_pci_probe(struct platform_device *pdev)
{
int
ret
;
struct
device_node
*
node
;
#ifdef CONFIG_SWIOTLB
struct
pci_controller
*
hose
;
#endif
node
=
pdev
->
dev
.
of_node
;
ret
=
fsl_add_bridge
(
pdev
,
fsl_pci_primary
==
node
);
#ifdef CONFIG_SWIOTLB
if
(
ret
==
0
)
{
hose
=
pci_find_hose_for_OF_device
(
pdev
->
dev
.
of_node
);
/*
* if we couldn't map all of DRAM via the dma windows
* we need SWIOTLB to handle buffers located outside of
* dma capable memory region
*/
if
(
memblock_end_of_DRAM
()
-
1
>
hose
->
dma_window_base_cur
+
hose
->
dma_window_size
)
ppc_swiotlb_enable
=
1
;
}
#endif
mpc85xx_pci_err_probe
(
pdev
);
return
0
;
...
...
arch/powerpc/sysdev/fsl_pci.h
浏览文件 @
a12e4537
...
...
@@ -126,5 +126,11 @@ static inline int mpc85xx_pci_err_probe(struct platform_device *op)
}
#endif
#ifdef CONFIG_FSL_PCI
extern
int
fsl_pci_mcheck_exception
(
struct
pt_regs
*
);
#else
static
inline
int
fsl_pci_mcheck_exception
(
struct
pt_regs
*
regs
)
{
return
0
;
}
#endif
#endif
/* __POWERPC_FSL_PCI_H */
#endif
/* __KERNEL__ */
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