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提交 8b3c8ba3 编写于 作者: L Linus Torvalds
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc 

Pull ARM SoC late changes from Olof Johansson:
 "We were expecting to sit on this branch through most of the merge
  window since the contents was merged into our tree late, but we ended
  up sitting on all of our contents so it can go in with the rest.

  The contents here is:

   - a large branch of cleanups of the CM/PRM blocks on OMAP.

   - a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.

   - a branch with DT updates for Freescale i.MX.  including some
     shuffling from .dts to .dtsi (include) files that causes a little
     churn"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
  ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
  ARM: OMAP4+: control: add support for initializing control module via DT
  ARM: dts: dra7: add minimal l4 bus layout with control module support
  ARM: dts: omap5: add minimal l4 bus layout with control module support
  ARM: OMAP4+: control: remove support for legacy pad read/write
  ARM: OMAP4: display: convert display to use syscon for dsi muxing
  ARM: dts: omap4: add minimal l4 bus layout with control module support
  ARM: dts: am4372: add minimal l4 bus layout with control module support
  ARM: dts: am43xx-epos-evm: fix pinmux node layout
  ARM: dts: am33xx: add minimal l4 bus layout with control module support
  ARM: dts: omap3: add minimal l4 bus layout with control module support
  ARM: dts: omap24xx: add minimal l4 bus layout with control module support
  ARM: OMAP2+: control: add syscon support for register accesses
  ARM: OMAP2+: id: cache omap_type value
  ARM: OMAP2+: control: remove API for getting control module base address
  ARM: OMAP2+: clock: add low-level support for regmap
  ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
  ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
  ARM: OMAP2+: CM: move SoC specific init calls within a generic API
  ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
  ...
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Documentation/devicetree/bindings/arm/omap/ctrl.txt 0 → 100644
浏览文件 @ 8b3c8ba3
OMAP Control Module bindings
Control Module contains miscellaneous features under it based on SoC type.
Pincontrol is one common feature, and it has a specialized support
described in [1]. Typically some clock nodes are also under control module.
Syscon is used to share register level access to drivers external to
control module driver itself.
See [2] for documentation about clock/clockdomain nodes.
[1] Documentation/devicetree/bindings/pinctrl/pinctrl-single.txt
[2] Documentation/devicetree/bindings/clock/ti/*
Required properties:
- compatible: Must be one of:
"ti,am3-scm"
"ti,am4-scm"
"ti,dm814-scrm"
"ti,dm816-scrm"
"ti,omap2-scm"
"ti,omap3-scm"
"ti,omap4-scm-core"
"ti,omap4-scm-padconf-core"
"ti,omap5-scm-core"
"ti,omap5-scm-padconf-core"
"ti,dra7-scm-core"
- reg: Contains Control Module register address range
(base address and length)
Optional properties:
- clocks: clocks for this module
- clockdomains: clockdomains for this module
Examples:
scm: scm@2000 {
compatible = "ti,omap3-scm", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
omap3_pmx_core: pinmux@30 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0x30 0x230>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x330>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
}
&scm_clocks {
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
};
};
Documentation/devicetree/bindings/arm/omap/l4.txt 0 → 100644
浏览文件 @ 8b3c8ba3
L4 interconnect bindings
These bindings describe the OMAP SoCs L4 interconnect bus.
Required properties:
- compatible : Should be "ti,omap2-l4" for OMAP2 family l4 core bus
Should be "ti,omap2-l4-wkup" for OMAP2 family l4 wkup bus
Should be "ti,omap3-l4-core" for OMAP3 family l4 core bus
Should be "ti,omap4-l4-cfg" for OMAP4 family l4 cfg bus
Should be "ti,omap4-l4-wkup" for OMAP4 family l4 wkup bus
Should be "ti,omap5-l4-cfg" for OMAP5 family l4 cfg bus
Should be "ti,omap5-l4-wkup" for OMAP5 family l4 wkup bus
Should be "ti,dra7-l4-cfg" for DRA7 family l4 cfg bus
Should be "ti,dra7-l4-wkup" for DRA7 family l4 wkup bus
Should be "ti,am3-l4-wkup" for AM33xx family l4 wkup bus
Should be "ti,am4-l4-wkup" for AM43xx family l4 wkup bus
- ranges : contains the IO map range for the bus
Examples:
l4: l4@48000000 {
compatible "ti,omap2-l4", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
};
Documentation/devicetree/bindings/arm/omap/prcm.txt
浏览文件 @ 8b3c8ba3
......@@ -10,14 +10,10 @@ documentation about the individual clock/clockdomain nodes.
Required properties:
- compatible: Must be one of:
"ti,am3-prcm"
"ti,am3-scrm"
"ti,am4-prcm"
"ti,am4-scrm"
"ti,omap2-prcm"
"ti,omap2-scrm"
"ti,omap3-prm"
"ti,omap3-cm"
"ti,omap3-scrm"
"ti,omap4-cm1"
"ti,omap4-prm"
"ti,omap4-cm2"
......@@ -29,6 +25,8 @@ Required properties:
"ti,dra7-prm"
"ti,dra7-cm-core-aon"
"ti,dra7-cm-core"
"ti,dm814-prcm"
"ti,dm816-prcm"
- reg: Contains PRCM module register address range
(base address and length)
- clocks: clocks for this module
......
arch/arm/boot/dts/Makefile
浏览文件 @ 8b3c8ba3
......@@ -307,9 +307,11 @@ dtb-$(CONFIG_SOC_IMX6Q) += \
imx6q-wandboard.dtb \
imx6q-wandboard-revb1.dtb
dtb-$(CONFIG_SOC_IMX6SL) += \
imx6sl-evk.dtb
imx6sl-evk.dtb \
imx6sl-warp.dtb
dtb-$(CONFIG_SOC_IMX6SX) += \
imx6sx-sabreauto.dtb \
imx6sx-sdb-reva.dtb \
imx6sx-sdb.dtb
dtb-$(CONFIG_SOC_LS1021A) += \
ls1021a-qds.dtb \
......
arch/arm/boot/dts/am33xx-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
......
arch/arm/boot/dts/am33xx.dtsi
浏览文件 @ 8b3c8ba3
......@@ -83,20 +83,6 @@ mpu {
};
};
am33xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7fc>;
};
am33xx_pinmux: pinmux@44e10800 {
compatible = "pinctrl-single";
reg = <0x44e10800 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
/*
* XXX: Use a flat representation of the AM33XX interconnect.
* The real AM33XX interconnect network is quite complex. Since
......@@ -111,37 +97,58 @@ ocp {
ranges;
ti,hwmods = "l3_main";
prcm: prcm@44e00000 {
compatible = "ti,am3-prcm";
reg = <0x44e00000 0x4000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am3-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x280000>;
prcm_clockdomains: clockdomains {
};
};
prcm: prcm@200000 {
compatible = "ti,am3-prcm";
reg = <0x200000 0x4000>;
scrm: scrm@44e10000 {
compatible = "ti,am3-scrm";
reg = <0x44e10000 0x2000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
prcm_clockdomains: clockdomains {
};
};
scrm_clockdomains: clockdomains {
scm: scm@210000 {
compatible = "ti,am3-scm", "simple-bus";
reg = <0x210000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x2000>;
am33xx_pinmux: pinmux@800 {
compatible = "pinctrl-single";
reg = <0x800 0x238>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x7f>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
};
cm: syscon@44e10000 {
compatible = "ti,am33xx-controlmodule", "syscon";
reg = <0x44e10000 0x800>;
};
intc: interrupt-controller@48200000 {
compatible = "ti,am33xx-intc";
interrupt-controller;
......@@ -350,7 +357,7 @@ dcan0: can@481cc000 {
reg = <0x481cc000 0x2000>;
clocks = <&dcan0_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <52>;
status = "disabled";
};
......@@ -361,7 +368,7 @@ dcan1: can@481d0000 {
reg = <0x481d0000 0x2000>;
clocks = <&dcan1_fck>;
clock-names = "fck";
syscon-raminit = <&am33xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <55>;
status = "disabled";
};
......@@ -720,7 +727,7 @@ mac: ethernet@4a100000 {
*/
interrupts = <40 41 42 43>;
ranges;
syscon = <&cm>;
syscon = <&scm_conf>;
status = "disabled";
davinci_mdio: mdio@4a101000 {
......
arch/arm/boot/dts/am3517.dtsi
浏览文件 @ 8b3c8ba3
......@@ -31,7 +31,7 @@ davinci_emac: ethernet@0x5c000000 {
status = "disabled";
reg = <0x5c000000 0x30000>;
interrupts = <67 68 69 70>;
syscon = <&omap3_scm_general>;
syscon = <&scm_conf>;
ti,davinci-ctrl-reg-offset = <0x10000>;
ti,davinci-ctrl-mod-reg-offset = <0>;
ti,davinci-ctrl-ram-offset = <0x20000>;
......
arch/arm/boot/dts/am35xx-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
emac_ick: emac_ick {
#clock-cells = <0>;
compatible = "ti,am35xx-gate-clock";
......
arch/arm/boot/dts/am4372.dtsi
浏览文件 @ 8b3c8ba3
......@@ -66,22 +66,6 @@ l2-cache-controller@48242000 {
cache-level = <2>;
};
am43xx_control_module: control_module@4a002000 {
compatible = "syscon";
reg = <0x44e10000 0x7f4>;
};
am43xx_pinmux: pinmux@44e10800 {
compatible = "ti,am437-padconf", "pinctrl-single";
reg = <0x44e10800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
ocp {
compatible = "ti,am4372-l3-noc", "simple-bus";
#address-cells = <1>;
......@@ -93,29 +77,58 @@ ocp {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prcm: prcm@44df0000 {
compatible = "ti,am4-prcm";
reg = <0x44df0000 0x11000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
l4_wkup: l4_wkup@44c00000 {
compatible = "ti,am4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x44c00000 0x287000>;
prcm_clockdomains: clockdomains {
};
};
prcm: prcm@1f0000 {
compatible = "ti,am4-prcm";
reg = <0x1f0000 0x11000>;
scrm: scrm@44e10000 {
compatible = "ti,am4-scrm";
reg = <0x44e10000 0x2000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
prcm_clockdomains: clockdomains {
};
};
scrm_clockdomains: clockdomains {
scm: scm@210000 {
compatible = "ti,am4-scm", "simple-bus";
reg = <0x210000 0x4000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x210000 0x4000>;
am43xx_pinmux: pinmux@800 {
compatible = "ti,am437-padconf",
"pinctrl-single";
reg = <0x800 0x31c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0xffffffff>;
};
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
};
......@@ -942,7 +955,7 @@ dcan0: can@481cc000 {
clocks = <&dcan0_fck>;
clock-names = "fck";
reg = <0x481cc000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 0>;
syscon-raminit = <&scm_conf 0x644 0>;
interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......@@ -953,7 +966,7 @@ dcan1: can@481d0000 {
clocks = <&dcan1_fck>;
clock-names = "fck";
reg = <0x481d0000 0x2000>;
syscon-raminit = <&am43xx_control_module 0x644 1>;
syscon-raminit = <&scm_conf 0x644 1>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
......
arch/arm/boot/dts/am43x-epos-evm.dts
浏览文件 @ 8b3c8ba3
......@@ -69,7 +69,48 @@ lcd_in: endpoint {
};
};
am43xx_pinmux: pinmux@44e10800 {
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
linux,keymap = <0x00000201 /* P1 */
0x01000204 /* P4 */
0x02000207 /* P7 */
0x0300020a /* NUMERIC_STAR */
0x00010202 /* P2 */
0x01010205 /* P5 */
0x02010208 /* P8 */
0x03010200 /* P0 */
0x00020203 /* P3 */
0x01020206 /* P6 */
0x02020209 /* P9 */
0x0302020b /* NUMERIC_POUND */
0x00030067 /* UP */
0x0103006a /* RIGHT */
0x0203006c /* DOWN */
0x03030069>; /* LEFT */
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
};
&am43xx_pinmux {
cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
......@@ -279,47 +320,6 @@ vpfe1_pins_sleep: vpfe1_pins_sleep {
0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7)
>;
};
};
matrix_keypad: matrix_keypad@0 {
compatible = "gpio-matrix-keypad";
debounce-delay-ms = <5>;
col-scan-delay-us = <2>;
row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */
&gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */
&gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */
&gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */
col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */
&gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */
&gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */
&gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */
linux,keymap = <0x00000201 /* P1 */
0x01000204 /* P4 */
0x02000207 /* P7 */
0x0300020a /* NUMERIC_STAR */
0x00010202 /* P2 */
0x01010205 /* P5 */
0x02010208 /* P8 */
0x03010200 /* P0 */
0x00020203 /* P3 */
0x01020206 /* P6 */
0x02020209 /* P9 */
0x0302020b /* NUMERIC_POUND */
0x00030067 /* UP */
0x0103006a /* RIGHT */
0x0203006c /* DOWN */
0x03030069>; /* LEFT */
};
backlight {
compatible = "pwm-backlight";
pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>;
brightness-levels = <0 51 53 56 62 75 101 152 255>;
default-brightness-level = <8>;
};
};
&mmc1 {
......
arch/arm/boot/dts/am43xx-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -7,7 +7,7 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
sys_clkin_ck: sys_clkin_ck {
#clock-cells = <0>;
compatible = "ti,mux-clock";
......
arch/arm/boot/dts/dra7.dtsi
浏览文件 @ 8b3c8ba3
......@@ -102,17 +102,101 @@ ocp {
interrupts-extended = <&crossbar_mpu GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<&wakeupgen GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,dra7-prm";
reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
l4_cfg: l4@4a000000 {
compatible = "ti,dra7-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22c000>;
prm_clocks: clocks {
scm: scm@2000 {
compatible = "ti,dra7-scm-core", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x1400>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0xe00 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
dra7_pmx_core: pinmux@1400 {
compatible = "ti,dra7-padconf",
"pinctrl-single";
reg = <0x1400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
};
cm_core_aon: cm_core_aon@5000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x5000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
prm_clockdomains: clockdomains {
cm_core: cm_core@8000 {
compatible = "ti,dra7-cm-core";
reg = <0x8000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
};
l4_wkup: l4@4ae00000 {
compatible = "ti,dra7-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4ae00000 0x3f000>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,dra7-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
};
......@@ -197,38 +281,6 @@ bandgap: bandgap@4a0021e0 {
#thermal-sensor-cells = <1>;
};
cm_core_aon: cm_core_aon@4a005000 {
compatible = "ti,dra7-cm-core-aon";
reg = <0x4a005000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,dra7-cm-core";
reg = <0x4a008000 0x3000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clockdomains: clockdomains {
};
};
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
};
dra7_ctrl_core: ctrl_core@4a002000 {
compatible = "syscon";
reg = <0x4a002000 0x6d0>;
......@@ -239,28 +291,6 @@ dra7_ctrl_general: tisyscon@4a002e00 {
reg = <0x4a002e00 0x7c>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0 0x4>;
syscon = <&dra7_ctrl_general>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
dra7_pmx_core: pinmux@4a003400 {
compatible = "ti,dra7-padconf", "pinctrl-single";
reg = <0x4a003400 0x0464>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <32>;
pinctrl-single,function-mask = <0x3fffffff>;
};
sdma: dma-controller@4a056000 {
compatible = "ti,omap4430-sdma";
reg = <0x4a056000 0x1000>;
......@@ -1424,7 +1454,7 @@ dcan1: can@481cc000 {
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan1";
reg = <0x4ae3c000 0x2000>;
syscon-raminit = <&dra7_ctrl_core 0x558 0>;
syscon-raminit = <&scm_conf 0x558 0>;
interrupts = <GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&dcan1_sys_clk_mux>;
status = "disabled";
......@@ -1434,7 +1464,7 @@ dcan2: can@481d0000 {
compatible = "ti,dra7-d_can";
ti,hwmods = "dcan2";
reg = <0x48480000 0x2000>;
syscon-raminit = <&dra7_ctrl_core 0x558 1>;
syscon-raminit = <&scm_conf 0x558 1>;
interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&sys_clkin1>;
status = "disabled";
......
arch/arm/boot/dts/imx25-pdk.dts
浏览文件 @ 8b3c8ba3
......@@ -75,6 +75,27 @@ sound {
mux-int-port = <1>;
mux-ext-port = <4>;
};
wvga: display {
model = "CLAA057VC01CW";
bits-per-pixel = <16>;
fsl,pcr = <0xfa208b80>;
bus-width = <18>;
native-mode = <&wvga_timings>;
display-timings {
wvga_timings: 640x480 {
hactive = <640>;
vactive = <480>;
hback-porch = <45>;
hfront-porch = <114>;
hsync-len = <1>;
vback-porch = <33>;
vfront-porch = <11>;
vsync-len = <1>;
clock-frequency = <25200000>;
};
};
};
};
&audmux {
......@@ -190,6 +211,33 @@ MX25_PAD_KPP_COL3__KPP_COL3 0x80000000
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX25_PAD_LD0__LD0 0xe0
MX25_PAD_LD1__LD1 0xe0
MX25_PAD_LD2__LD2 0xe0
MX25_PAD_LD3__LD3 0xe0
MX25_PAD_LD4__LD4 0xe0
MX25_PAD_LD5__LD5 0xe0
MX25_PAD_LD6__LD6 0xe0
MX25_PAD_LD7__LD7 0xe0
MX25_PAD_LD8__LD8 0xe0
MX25_PAD_LD9__LD9 0xe0
MX25_PAD_LD10__LD10 0xe0
MX25_PAD_LD11__LD11 0xe0
MX25_PAD_LD12__LD12 0xe0
MX25_PAD_LD13__LD13 0xe0
MX25_PAD_LD14__LD14 0xe0
MX25_PAD_LD15__LD15 0xe0
MX25_PAD_GPIO_E__LD16 0xe0
MX25_PAD_GPIO_F__LD17 0xe0
MX25_PAD_HSYNC__HSYNC 0xe0
MX25_PAD_VSYNC__VSYNC 0xe0
MX25_PAD_LSCLK__LSCLK 0xe0
MX25_PAD_OE_ACD__OE_ACD 0xe0
MX25_PAD_CONTRAST__CONTRAST 0xe0
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
......@@ -202,6 +250,16 @@ MX25_PAD_UART1_RXD__UART1_RXD 0xc0
};
};
&lcdc {
display = <&wvga>;
fsl,lpccr = <0x00a903ff>;
fsl,lscr1 = <0x00120300>;
fsl,dmacr = <0x00020010>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
status = "okay";
};
&nfc {
nand-on-flash-bbt;
status = "okay";
......
arch/arm/boot/dts/imx25-pinfunc.h
浏览文件 @ 8b3c8ba3
......@@ -17,48 +17,69 @@
* <mux_reg conf_reg input_reg mux_mode input_val>
*/
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_A10__A10 0x008 0x000 0x000 0x00 0x000
#define MX25_PAD_A10__GPIO_4_0 0x008 0x000 0x000 0x05 0x000
#define MX25_PAD_A13__A13 0x00c 0x22C 0x000 0x00 0x000
#define MX25_PAD_A13__GPIO_4_1 0x00c 0x22C 0x000 0x05 0x000
#define MX25_PAD_A13__LCDC_CLS 0x00c 0x22C 0x000 0x07 0x000
#define MX25_PAD_A14__A14 0x010 0x230 0x000 0x10 0x000
#define MX25_PAD_A14__GPIO_2_0 0x010 0x230 0x000 0x15 0x000
#define MX25_PAD_A14__SIM1_CLK1 0x010 0x230 0x000 0x16 0x000
#define MX25_PAD_A14__LCDC_SPL 0x010 0x230 0x000 0x17 0x000
#define MX25_PAD_A15__A15 0x014 0x234 0x000 0x10 0x000
#define MX25_PAD_A15__GPIO_2_1 0x014 0x234 0x000 0x15 0x000
#define MX25_PAD_A15__SIM1_RST1 0x014 0x234 0x000 0x16 0x000
#define MX25_PAD_A15__LCDC_PS 0x014 0x234 0x000 0x17 0x000
#define MX25_PAD_A16__A16 0x018 0x000 0x000 0x10 0x000
#define MX25_PAD_A16__GPIO_2_2 0x018 0x000 0x000 0x15 0x000
#define MX25_PAD_A16__SIM1_VEN1 0x018 0x000 0x000 0x16 0x000
#define MX25_PAD_A16__LCDC_REV 0x018 0x000 0x000 0x17 0x000
#define MX25_PAD_A17__A17 0x01c 0x238 0x000 0x10 0x000
#define MX25_PAD_A17__GPIO_2_3 0x01c 0x238 0x000 0x15 0x000
#define MX25_PAD_A17__SIM1_TX 0x01c 0x238 0x554 0x16 0x000
#define MX25_PAD_A17__FEC_TX_ERR 0x01c 0x238 0x000 0x17 0x000
#define MX25_PAD_A18__A18 0x020 0x23c 0x000 0x10 0x000
#define MX25_PAD_A18__GPIO_2_4 0x020 0x23c 0x000 0x15 0x000
#define MX25_PAD_A18__SIM1_PD1 0x020 0x23c 0x550 0x16 0x000
#define MX25_PAD_A18__FEC_COL 0x020 0x23c 0x504 0x17 0x000
#define MX25_PAD_A19__A19 0x024 0x240 0x000 0x10 0x000
#define MX25_PAD_A19__FEC_RX_ER 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A19__GPIO_2_5 0x024 0x240 0x000 0x15 0x000
#define MX25_PAD_A19__SIM1_RX1 0x024 0x240 0x54c 0x16 0x000
#define MX25_PAD_A19__FEC_RX_ERR 0x024 0x240 0x518 0x17 0x000
#define MX25_PAD_A20__A20 0x028 0x244 0x000 0x10 0x000
#define MX25_PAD_A20__GPIO_2_6 0x028 0x244 0x000 0x15 0x000
#define MX25_PAD_A20__SIM2_CLK1 0x028 0x244 0x000 0x16 0x000
#define MX25_PAD_A20__FEC_RDATA2 0x028 0x244 0x50c 0x17 0x000
#define MX25_PAD_A21__A21 0x02c 0x248 0x000 0x10 0x000
#define MX25_PAD_A21__GPIO_2_7 0x02c 0x248 0x000 0x15 0x000
#define MX25_PAD_A21__SIM2_RST1 0x02c 0x248 0x000 0x16 0x000
#define MX25_PAD_A21__FEC_RDATA3 0x02c 0x248 0x510 0x17 0x000
#define MX25_PAD_A22__A22 0x030 0x000 0x000 0x10 0x000
#define MX25_PAD_A22__GPIO_2_8 0x030 0x000 0x000 0x15 0x000
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
#define MX25_PAD_A22__SIM2_VEN1 0x030 0x000 0x000 0x16 0x000
#define MX25_PAD_A22__FEC_TDATA2 0x030 0x000 0x000 0x17 0x000
#define MX25_PAD_A23__A23 0x034 0x24c 0x000 0x10 0x000
#define MX25_PAD_A23__GPIO_2_9 0x034 0x24c 0x000 0x15 0x000
#define MX25_PAD_A23__SIM2_TX1 0x034 0x24c 0x560 0x16 0x000
#define MX25_PAD_A23__FEC_TDATA3 0x034 0x24c 0x000 0x17 0x000
#define MX25_PAD_A24__A24 0x038 0x250 0x000 0x10 0x000
#define MX25_PAD_A24__GPIO_2_10 0x038 0x250 0x000 0x15 0x000
#define MX25_PAD_A24__SIM2_PD1 0x038 0x250 0x55c 0x16 0x000
#define MX25_PAD_A24__FEC_RX_CLK 0x038 0x250 0x514 0x17 0x000
#define MX25_PAD_A25__A25 0x03c 0x254 0x000 0x10 0x000
......@@ -133,20 +154,25 @@
#define MX25_PAD_D15__D15 0x088 0x280 0x000 0x00 0x000
#define MX25_PAD_D15__LD16 0x088 0x280 0x000 0x01 0x000
#define MX25_PAD_D15__GPIO_4_5 0x088 0x280 0x000 0x05 0x000
#define MX25_PAD_D15__SDHC1_DAT7 0x088 0x280 0x4d8 0x06 0x000
#define MX25_PAD_D14__D14 0x08c 0x284 0x000 0x00 0x000
#define MX25_PAD_D14__LD17 0x08c 0x284 0x000 0x01 0x000
#define MX25_PAD_D14__GPIO_4_6 0x08c 0x284 0x000 0x05 0x000
#define MX25_PAD_D14__SDHC1_DAT6 0x08c 0x284 0x4d4 0x06 0x000
#define MX25_PAD_D13__D13 0x090 0x288 0x000 0x00 0x000
#define MX25_PAD_D13__LD18 0x090 0x288 0x000 0x01 0x000
#define MX25_PAD_D13__GPIO_4_7 0x090 0x288 0x000 0x05 0x000
#define MX25_PAD_D13__SDHC1_DAT5 0x090 0x288 0x4d0 0x06 0x000
#define MX25_PAD_D12__D12 0x094 0x28c 0x000 0x00 0x000
#define MX25_PAD_D12__GPIO_4_8 0x094 0x28c 0x000 0x05 0x000
#define MX25_PAD_D12__SDHC1_DAT4 0x094 0x28c 0x4cc 0x06 0x000
#define MX25_PAD_D11__D11 0x098 0x290 0x000 0x00 0x000
#define MX25_PAD_D11__GPIO_4_9 0x098 0x290 0x000 0x05 0x000
#define MX25_PAD_D11__USBOTG_PWR 0x098 0x290 0x000 0x06 0x000
#define MX25_PAD_D10__D10 0x09c 0x294 0x000 0x00 0x000
#define MX25_PAD_D10__GPIO_4_10 0x09c 0x294 0x000 0x05 0x000
......@@ -212,26 +238,33 @@
#define MX25_PAD_LD8__LD8 0x0e8 0x2e0 0x000 0x10 0x000
#define MX25_PAD_LD8__FEC_TX_ERR 0x0e8 0x2e0 0x000 0x15 0x000
#define MX25_PAD_LD8__SDHC2_CMD 0x0e8 0x2e0 0x4e0 0x06 0x000
#define MX25_PAD_LD9__LD9 0x0ec 0x2e4 0x000 0x10 0x000
#define MX25_PAD_LD9__FEC_COL 0x0ec 0x2e4 0x504 0x15 0x001
#define MX25_PAD_LD9__SDHC2_CLK 0x0ec 0x2e4 0x4dc 0x06 0x000
#define MX25_PAD_LD10__LD10 0x0f0 0x2e8 0x000 0x10 0x000
#define MX25_PAD_LD10__FEC_RX_ER 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD10__FEC_RX_ERR 0x0f0 0x2e8 0x518 0x15 0x001
#define MX25_PAD_LD11__LD11 0x0f4 0x2ec 0x000 0x10 0x000
#define MX25_PAD_LD11__FEC_RDATA2 0x0f4 0x2ec 0x50c 0x15 0x001
#define MX25_PAD_LD11__SDHC2_DAT1 0x0f4 0x2ec 0x4e8 0x06 0x000
#define MX25_PAD_LD12__LD12 0x0f8 0x2f0 0x000 0x10 0x000
#define MX25_PAD_LD12__CSPI2_MOSI 0x0f8 0x2f0 0x4a0 0x02 0x000
#define MX25_PAD_LD12__FEC_RDATA3 0x0f8 0x2f0 0x510 0x15 0x001
#define MX25_PAD_LD13__LD13 0x0fc 0x2f4 0x000 0x10 0x000
#define MX25_PAD_LD13__CSPI2_MISO 0x0fc 0x2f4 0x49c 0x02 0x000
#define MX25_PAD_LD13__FEC_TDATA2 0x0fc 0x2f4 0x000 0x15 0x000
#define MX25_PAD_LD14__LD14 0x100 0x2f8 0x000 0x10 0x000
#define MX25_PAD_LD14__CSPI2_SCLK 0x100 0x2f8 0x494 0x02 0x000
#define MX25_PAD_LD14__FEC_TDATA3 0x100 0x2f8 0x000 0x15 0x000
#define MX25_PAD_LD15__LD15 0x104 0x2fc 0x000 0x10 0x000
#define MX25_PAD_LD15__CSPI2_RDY 0x104 0x2fc 0x498 0x02 0x000
#define MX25_PAD_LD15__FEC_RX_CLK 0x104 0x2fc 0x514 0x15 0x001
#define MX25_PAD_HSYNC__HSYNC 0x108 0x300 0x000 0x10 0x000
......@@ -244,6 +277,7 @@
#define MX25_PAD_LSCLK__GPIO_1_24 0x110 0x308 0x000 0x15 0x000
#define MX25_PAD_OE_ACD__OE_ACD 0x114 0x30c 0x000 0x10 0x000
#define MX25_PAD_OE_ACD__CSPI2_SS0 0x114 0x30c 0x4a4 0x02 0x000
#define MX25_PAD_OE_ACD__GPIO_1_25 0x114 0x30c 0x000 0x15 0x000
#define MX25_PAD_CONTRAST__CONTRAST 0x118 0x310 0x000 0x10 0x000
......@@ -257,26 +291,31 @@
#define MX25_PAD_CSI_D2__CSI_D2 0x120 0x318 0x000 0x10 0x000
#define MX25_PAD_CSI_D2__UART5_RXD_MUX 0x120 0x318 0x578 0x11 0x001
#define MX25_PAD_CSI_D2__SIM1_CLK0 0x120 0x318 0x000 0x04 0x000
#define MX25_PAD_CSI_D2__GPIO_1_27 0x120 0x318 0x000 0x15 0x000
#define MX25_PAD_CSI_D2__CSPI3_MOSI 0x120 0x318 0x000 0x17 0x000
#define MX25_PAD_CSI_D3__CSI_D3 0x124 0x31c 0x000 0x10 0x000
#define MX25_PAD_CSI_D3__UART5_TXD_MUX 0x124 0x31c 0x000 0x11 0x000
#define MX25_PAD_CSI_D3__SIM1_RST0 0x124 0x31c 0x000 0x04 0x000
#define MX25_PAD_CSI_D3__GPIO_1_28 0x124 0x31c 0x000 0x15 0x000
#define MX25_PAD_CSI_D3__CSPI3_MISO 0x124 0x31c 0x4b4 0x17 0x001
#define MX25_PAD_CSI_D4__CSI_D4 0x128 0x320 0x000 0x10 0x000
#define MX25_PAD_CSI_D4__UART5_RTS 0x128 0x320 0x574 0x11 0x001
#define MX25_PAD_CSI_D4__SIM1_VEN0 0x128 0x320 0x000 0x04 0x000
#define MX25_PAD_CSI_D4__GPIO_1_29 0x128 0x320 0x000 0x15 0x000
#define MX25_PAD_CSI_D4__CSPI3_SCLK 0x128 0x320 0x000 0x17 0x000
#define MX25_PAD_CSI_D5__CSI_D5 0x12c 0x324 0x000 0x10 0x000
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x001
#define MX25_PAD_CSI_D5__UART5_CTS 0x12c 0x324 0x000 0x11 0x000
#define MX25_PAD_CSI_D5__SIM1_TX0 0x12c 0x324 0x000 0x04 0x000
#define MX25_PAD_CSI_D5__GPIO_1_30 0x12c 0x324 0x000 0x15 0x000
#define MX25_PAD_CSI_D5__CSPI3_RDY 0x12c 0x324 0x000 0x17 0x000
#define MX25_PAD_CSI_D6__CSI_D6 0x130 0x328 0x000 0x10 0x000
#define MX25_PAD_CSI_D6__SDHC2_CMD 0x130 0x328 0x4e0 0x12 0x001
#define MX25_PAD_CSI_D6__SIM1_PD0 0x130 0x328 0x000 0x04 0x000
#define MX25_PAD_CSI_D6__GPIO_1_31 0x130 0x328 0x000 0x15 0x000
#define MX25_PAD_CSI_D7__CSI_D7 0x134 0x32c 0x000 0x10 0x000
......@@ -284,32 +323,32 @@
#define MX25_PAD_CSI_D7__GPIO_1_6 0x134 0x32c 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSI_D8 0x138 0x330 0x000 0x10 0x000
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x001
#define MX25_PAD_CSI_D8__AUD6_RXC 0x138 0x330 0x000 0x12 0x000
#define MX25_PAD_CSI_D8__GPIO_1_7 0x138 0x330 0x000 0x15 0x000
#define MX25_PAD_CSI_D8__CSPI3_SS2 0x138 0x330 0x4c4 0x17 0x000
#define MX25_PAD_CSI_D9__CSI_D9 0x13c 0x334 0x000 0x10 0x000
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x001
#define MX25_PAD_CSI_D9__AUD6_RXFS 0x13c 0x334 0x000 0x12 0x000
#define MX25_PAD_CSI_D9__GPIO_4_21 0x13c 0x334 0x000 0x15 0x000
#define MX25_PAD_CSI_D9__CSPI3_SS3 0x13c 0x334 0x4c8 0x17 0x000
#define MX25_PAD_CSI_MCLK__CSI_MCLK 0x140 0x338 0x000 0x10 0x000
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x001
#define MX25_PAD_CSI_MCLK__AUD6_TXD 0x140 0x338 0x000 0x11 0x000
#define MX25_PAD_CSI_MCLK__SDHC2_DAT0 0x140 0x338 0x4e4 0x12 0x001
#define MX25_PAD_CSI_MCLK__GPIO_1_8 0x140 0x338 0x000 0x15 0x000
#define MX25_PAD_CSI_VSYNC__CSI_VSYNC 0x144 0x33c 0x000 0x10 0x000
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x001
#define MX25_PAD_CSI_VSYNC__AUD6_RXD 0x144 0x33c 0x000 0x11 0x000
#define MX25_PAD_CSI_VSYNC__SDHC2_DAT1 0x144 0x33c 0x4e8 0x12 0x001
#define MX25_PAD_CSI_VSYNC__GPIO_1_9 0x144 0x33c 0x000 0x15 0x000
#define MX25_PAD_CSI_HSYNC__CSI_HSYNC 0x148 0x340 0x000 0x10 0x000
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x001
#define MX25_PAD_CSI_HSYNC__AUD6_TXC 0x148 0x340 0x000 0x11 0x000
#define MX25_PAD_CSI_HSYNC__SDHC2_DAT2 0x148 0x340 0x4ec 0x12 0x001
#define MX25_PAD_CSI_HSYNC__GPIO_1_10 0x148 0x340 0x000 0x15 0x000
#define MX25_PAD_CSI_PIXCLK__CSI_PIXCLK 0x14c 0x344 0x000 0x10 0x000
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x001
#define MX25_PAD_CSI_PIXCLK__AUD6_TXFS 0x14c 0x344 0x000 0x11 0x000
#define MX25_PAD_CSI_PIXCLK__SDHC2_DAT3 0x14c 0x344 0x4f0 0x12 0x001
#define MX25_PAD_CSI_PIXCLK__GPIO_1_11 0x14c 0x344 0x000 0x15 0x000
......@@ -369,8 +408,8 @@
#define MX25_PAD_UART2_RTS__CC1 0x188 0x380 0x000 0x13 0x000
#define MX25_PAD_UART2_RTS__GPIO_4_28 0x188 0x380 0x000 0x15 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ER 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__UART2_CTS 0x18c 0x384 0x000 0x10 0x000
#define MX25_PAD_UART2_CTS__FEC_RX_ERR 0x18c 0x384 0x518 0x12 0x002
#define MX25_PAD_UART2_CTS__GPIO_4_29 0x18c 0x384 0x000 0x15 0x000
#define MX25_PAD_SD1_CMD__SD1_CMD 0x190 0x388 0x000 0x10 0x000
......@@ -392,11 +431,11 @@
#define MX25_PAD_SD1_DATA1__GPIO_2_26 0x19c 0x394 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA2__SD1_DATA2 0x1a0 0x398 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x15 0x002
#define MX25_PAD_SD1_DATA2__FEC_RX_CLK 0x1a0 0x398 0x514 0x12 0x002
#define MX25_PAD_SD1_DATA2__GPIO_2_27 0x1a0 0x398 0x000 0x15 0x000
#define MX25_PAD_SD1_DATA3__SD1_DATA3 0x1a4 0x39c 0x000 0x10 0x000
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x10 0x002
#define MX25_PAD_SD1_DATA3__FEC_CRS 0x1a4 0x39c 0x508 0x12 0x002
#define MX25_PAD_SD1_DATA3__GPIO_2_28 0x1a4 0x39c 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW0__KPP_ROW0 0x1a8 0x3a0 0x000 0x10 0x000
......@@ -410,7 +449,7 @@
#define MX25_PAD_KPP_ROW2__GPIO_2_31 0x1b0 0x3a8 0x000 0x15 0x000
#define MX25_PAD_KPP_ROW3__KPP_ROW3 0x1b4 0x3ac 0x000 0x10 0x000
#define MX25_PAD_KPP_ROW3__CSI_LD1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__CSI_D1 0x1b4 0x3ac 0x48c 0x13 0x002
#define MX25_PAD_KPP_ROW3__GPIO_3_0 0x1b4 0x3ac 0x000 0x15 0x000
#define MX25_PAD_KPP_COL0__KPP_COL0 0x1b8 0x3b0 0x000 0x10 0x000
......@@ -455,9 +494,18 @@
#define MX25_PAD_FEC_RDATA0__GPIO_3_10 0x1dc 0x3d4 0x000 0x15 0x000
#define MX25_PAD_FEC_RDATA1__FEC_RDATA1 0x1e0 0x3d8 0x000 0x10 0x000
/*
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
* 01/2011) this is CAN1_TX but that's wrong.
*/
#define MX25_PAD_FEC_RDATA1__CAN2_TX 0x1e0 0x3d8 0x000 0x14 0x000
#define MX25_PAD_FEC_RDATA1__GPIO_3_11 0x1e0 0x3d8 0x000 0x15 0x000
#define MX25_PAD_FEC_RX_DV__FEC_RX_DV 0x1e4 0x3dc 0x000 0x10 0x000
/*
* According to the i.MX25 Reference manual (IMX25RM, Rev. 2,
* 01/2011) this is CAN1_RX but that's wrong.
*/
#define MX25_PAD_FEC_RX_DV__CAN2_RX 0x1e4 0x3dc 0x484 0x14 0x000
#define MX25_PAD_FEC_RX_DV__GPIO_3_12 0x1e4 0x3dc 0x000 0x15 0x000
......@@ -471,30 +519,34 @@
#define MX25_PAD_DE_B__DE_B 0x1f0 0x3ec 0x000 0x10 0x000
#define MX25_PAD_DE_B__GPIO_2_20 0x1f0 0x3ec 0x000 0x15 0x000
#define MX25_PAD_TDO__TDO 0x000 0x3e8 0x000 0x00 0x000
#define MX25_PAD_GPIO_A__GPIO_A 0x1f4 0x3f0 0x000 0x10 0x000
#define MX25_PAD_GPIO_A__CAN1_TX 0x1f4 0x3f0 0x000 0x16 0x000
#define MX25_PAD_GPIO_A__USBOTG_PWR 0x1f4 0x3f0 0x000 0x12 0x000
#define MX25_PAD_GPIO_B__GPIO_B 0x1f8 0x3f4 0x000 0x10 0x000
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_B__USBOTG_OC 0x1f8 0x3f4 0x57c 0x12 0x001
#define MX25_PAD_GPIO_B__CAN1_RX 0x1f8 0x3f4 0x480 0x16 0x001
#define MX25_PAD_GPIO_C__GPIO_C 0x1fc 0x3f8 0x000 0x10 0x000
#define MX25_PAD_GPIO_C__PWM4_PWMO 0x1fc 0x3f8 0x000 0x11 0x000
#define MX25_PAD_GPIO_C__I2C2_SCL 0x1fc 0x3f8 0x51c 0x12 0x001
#define MX25_PAD_GPIO_C__KPP_COL4 0x1fc 0x3f8 0x52c 0x13 0x001
#define MX25_PAD_GPIO_C__CAN2_TX 0x1fc 0x3f8 0x000 0x16 0x000
#define MX25_PAD_GPIO_D__GPIO_D 0x200 0x3fc 0x000 0x10 0x000
#define MX25_PAD_GPIO_D__I2C2_SDA 0x200 0x3fc 0x520 0x12 0x001
#define MX25_PAD_GPIO_D__CAN2_RX 0x200 0x3fc 0x484 0x16 0x001
#define MX25_PAD_GPIO_E__GPIO_E 0x204 0x400 0x000 0x10 0x000
#define MX25_PAD_GPIO_E__I2C3_CLK 0x204 0x400 0x524 0x11 0x002
#define MX25_PAD_GPIO_E__LD16 0x204 0x400 0x000 0x12 0x000
#define MX25_PAD_GPIO_E__AUD7_TXD 0x204 0x400 0x000 0x14 0x000
#define MX25_PAD_GPIO_E__UART4_RXD 0x204 0x400 0x570 0x16 0x002
#define MX25_PAD_GPIO_F__GPIO_F 0x208 0x404 0x000 0x10 0x000
#define MX25_PAD_GPIO_F__LD17 0x208 0x404 0x000 0x12 0x000
#define MX25_PAD_GPIO_F__AUD7_TXC 0x208 0x404 0x000 0x14 0x000
#define MX25_PAD_GPIO_F__UART4_TXD 0x208 0x404 0x000 0x16 0x000
#define MX25_PAD_EXT_ARMCLK__EXT_ARMCLK 0x20c 0x000 0x000 0x10 0x000
#define MX25_PAD_EXT_ARMCLK__GPIO_3_15 0x20c 0x000 0x000 0x15 0x000
......@@ -505,6 +557,7 @@
#define MX25_PAD_VSTBY_REQ__VSTBY_REQ 0x214 0x408 0x000 0x10 0x000
#define MX25_PAD_VSTBY_REQ__AUD7_TXFS 0x214 0x408 0x000 0x14 0x000
#define MX25_PAD_VSTBY_REQ__GPIO_3_17 0x214 0x408 0x000 0x15 0x000
#define MX25_PAD_VSTBY_ACK__VSTBY_ACK 0x218 0x40c 0x000 0x10 0x000
#define MX25_PAD_VSTBY_ACK__GPIO_3_18 0x218 0x40c 0x000 0x15 0x000
......@@ -517,6 +570,7 @@
#define MX25_PAD_BOOT_MODE0__BOOT_MODE0 0x224 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE0__GPIO_4_30 0x224 0x000 0x000 0x05 0x000
#define MX25_PAD_BOOT_MODE1__BOOT_MODE1 0x228 0x000 0x000 0x00 0x000
#define MX25_PAD_BOOT_MODE1__GPIO_4_31 0x228 0x000 0x000 0x05 0x000
......
arch/arm/boot/dts/imx27.dtsi
浏览文件 @ 8b3c8ba3
......@@ -488,6 +488,7 @@ usbh1: usb@10024200 {
interrupts = <54>;
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
......@@ -497,6 +498,7 @@ usbh2: usb@10024400 {
interrupts = <55>;
clocks = <&clks IMX27_CLK_USB_IPG_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx28-apf28.dts
浏览文件 @ 8b3c8ba3
......@@ -78,7 +78,7 @@ mac0: ethernet@800f0000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac0_pins_a>;
phy-reset-gpios = <&gpio4 13 0>;
phy-reset-gpios = <&gpio4 13 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
......
arch/arm/boot/dts/imx28-apf28dev.dts
浏览文件 @ 8b3c8ba3
......@@ -110,6 +110,13 @@ timing0: timing0 {
};
};
};
can0: can@80032000 {
pinctrl-names = "default";
pinctrl-0 = <&can0_pins_a>;
xceiver-supply = <&reg_can0_vcc>;
status = "okay";
};
};
apbx@80040000 {
......@@ -130,6 +137,13 @@ pwm: pwm@80064000 {
status = "okay";
};
auart0: serial@8006a000 {
pinctrl-names = "default";
pinctrl-0 = <&auart0_pins_a>;
fsl,uart-has-rtscts;
status = "okay";
};
usbphy0: usbphy@8007c000 {
status = "okay";
};
......@@ -143,7 +157,8 @@ usbphy1: usbphy@8007e000 {
ahb@80080000 {
usb0: usb@80080000 {
pinctrl-names = "default";
pinctrl-0 = <&usb0_otg_apf28dev>;
pinctrl-0 = <&usb0_otg_apf28dev
&usb0_id_pins_b>;
vbus-supply = <&reg_usb0_vbus>;
status = "okay";
};
......@@ -156,7 +171,7 @@ mac1: ethernet@800f4000 {
phy-mode = "rmii";
pinctrl-names = "default";
pinctrl-0 = <&mac1_pins_a>;
phy-reset-gpios = <&gpio0 23 0>;
phy-reset-gpios = <&gpio1 29 GPIO_ACTIVE_LOW>;
status = "okay";
};
};
......@@ -175,6 +190,14 @@ reg_usb0_vbus: regulator@0 {
gpio = <&gpio1 23 1>;
enable-active-high;
};
reg_can0_vcc: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "can0_vcc";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
};
leds {
......@@ -200,8 +223,9 @@ gpio-keys {
user-button {
label = "User button";
gpios = <&gpio0 17 0>;
gpios = <&gpio0 17 GPIO_ACTIVE_LOW>;
linux,code = <0x100>;
gpio-key,wakeup;
};
};
};
arch/arm/boot/dts/imx28.dtsi
浏览文件 @ 8b3c8ba3
......@@ -829,6 +829,19 @@ MX28_PAD_SSP3_SS0__SSP3_D3
fsl,pull-up = <MXS_PULL_DISABLE>;
};
spi3_pins_b: spi3@1 {
reg = <1>;
fsl,pinmux-ids = <
MX28_PAD_SSP3_SCK__SSP3_SCK
MX28_PAD_SSP3_MOSI__SSP3_CMD
MX28_PAD_SSP3_MISO__SSP3_D0
MX28_PAD_SSP3_SS0__SSP3_D3
>;
fsl,drive-strength = <MXS_DRIVE_8mA>;
fsl,voltage = <MXS_VOLTAGE_HIGH>;
fsl,pull-up = <MXS_PULL_ENABLE>;
};
usb0_pins_a: usb0@0 {
reg = <0>;
fsl,pinmux-ids = <
......@@ -1197,6 +1210,7 @@ usb1: usb@80090000 {
interrupts = <92>;
clocks = <&clks 61>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx35.dtsi
浏览文件 @ 8b3c8ba3
......@@ -318,6 +318,7 @@ usbhost1: usb@53ff4400 {
clocks = <&clks 73>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx50.dtsi
浏览文件 @ 8b3c8ba3
......@@ -197,6 +197,7 @@ usbh1: usb@53f80200 {
reg = <0x53f80200 0x0200>;
interrupts = <14>;
clocks = <&clks IMX5_CLK_USB_PHY2_GATE>;
dr_mode = "host";
status = "disabled";
};
......@@ -205,6 +206,7 @@ usbh2: usb@53f80400 {
reg = <0x53f80400 0x0200>;
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
dr_mode = "host";
status = "disabled";
};
......@@ -213,6 +215,7 @@ usbh3: usb@53f80600 {
reg = <0x53f80600 0x0200>;
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx51.dtsi
浏览文件 @ 8b3c8ba3
......@@ -265,6 +265,7 @@ usbh1: usb@73f80200 {
interrupts = <14>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
......@@ -274,6 +275,7 @@ usbh2: usb@73f80400 {
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
......@@ -283,6 +285,7 @@ usbh3: usb@73f80600 {
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx53.dtsi
浏览文件 @ 8b3c8ba3
......@@ -309,6 +309,7 @@ usbh1: usb@53f80200 {
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 1>;
fsl,usbphy = <&usbphy1>;
dr_mode = "host";
status = "disabled";
};
......@@ -318,6 +319,7 @@ usbh2: usb@53f80400 {
interrupts = <16>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
......@@ -327,6 +329,7 @@ usbh3: usb@53f80600 {
interrupts = <17>;
clocks = <&clks IMX5_CLK_USBOH3_GATE>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx6dl-aristainetos_4.dts
浏览文件 @ 8b3c8ba3
......@@ -83,3 +83,7 @@ &i2c2 {
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&pwm1 {
status = "okay";
};
arch/arm/boot/dts/imx6dl-aristainetos_7.dts
浏览文件 @ 8b3c8ba3
......@@ -72,3 +72,7 @@ &i2c2 {
&ipu1_di0_disp0 {
remote-endpoint = <&display0_in>;
};
&pwm3 {
status = "okay";
};
arch/arm/boot/dts/imx6dl-cubox-i.dts
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
......
arch/arm/boot/dts/imx6dl-hummingboard.dts
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
......
arch/arm/boot/dts/imx6q-cubox-i.dts
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
......
arch/arm/boot/dts/imx6q-hummingboard.dts
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Rabeeh Khoury (rabeeh@solid-run.com)
* Based on dt work by Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
......
arch/arm/boot/dts/imx6q.dtsi
浏览文件 @ 8b3c8ba3
......@@ -294,19 +294,21 @@ lvds1_mux_3: endpoint {
};
&mipi_dsi {
port@2 {
reg = <2>;
ports {
port@2 {
reg = <2>;
mipi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_mipi>;
mipi_mux_2: endpoint {
remote-endpoint = <&ipu2_di0_mipi>;
};
};
};
port@3 {
reg = <3>;
port@3 {
reg = <3>;
mipi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_mipi>;
mipi_mux_3: endpoint {
remote-endpoint = <&ipu2_di1_mipi>;
};
};
};
};
......
arch/arm/boot/dts/imx6qdl-cubox-i.dtsi
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
#include <dt-bindings/input/input.h>
#include <dt-bindings/gpio/gpio.h>
/ {
ir_recv: ir-receiver {
......@@ -66,6 +106,18 @@ sound-spdif {
spdif-controller = <&spdif>;
spdif-out;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-0 = <&pinctrl_gpio_key>;
pinctrl-names = "default";
button_0 {
label = "Button 0";
gpios = <&gpio3 8 GPIO_ACTIVE_LOW>;
linux,code = <BTN_0>;
};
};
};
&hdmi {
......@@ -170,9 +222,19 @@ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
>;
};
pinctrl_gpio_key: gpio-key {
fsl,pins = <
MX6QDL_PAD_EIM_DA8__GPIO3_IO08 0x17059
>;
};
};
};
&pwm1 {
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_cubox_i_spdif>;
......
arch/arm/boot/dts/imx6qdl-hummingboard.dtsi
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2013,2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
#include "imx6qdl-microsom.dtsi"
#include "imx6qdl-microsom-ar8035.dtsi"
......@@ -50,6 +88,19 @@ reg_usbotg_vbus: usb-otg-vbus {
};
};
sound-sgtl5000 {
audio-codec = <&sgtl5000>;
audio-routing =
"MIC_IN", "Mic Jack",
"Mic Jack", "Mic Bias",
"Headphone Jack", "HP_OUT";
compatible = "fsl,imx-audio-sgtl5000";
model = "On-board Codec";
mux-ext-port = <5>;
mux-int-port = <1>;
ssi-controller = <&ssi1>;
};
sound-spdif {
compatible = "fsl,imx-audio-spdif";
model = "On-board SPDIF";
......@@ -59,6 +110,10 @@ sound-spdif {
};
};
&audmux {
status = "okay";
};
&can1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_flexcan1>;
......@@ -75,16 +130,24 @@ &hdmi {
&i2c1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_i2c1>;
/*
* Not fitted on Carrier-1 board... yet
status = "okay";
/* Pro baseboard model */
rtc: pcf8523@68 {
compatible = "nxp,pcf8523";
reg = <0x68>;
};
*/
/* Pro baseboard model */
sgtl5000: sgtl5000@0a {
clocks = <&clks IMX6QDL_CLK_CKO>;
compatible = "fsl,sgtl5000";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_sgtl5000>;
reg = <0x0a>;
VDDA-supply = <&reg_3p3v>;
VDDIO-supply = <&reg_3p3v>;
};
};
&i2c2 {
......@@ -129,6 +192,20 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_hummingboard_pwm1: pwm1grp {
fsl,pins = <MX6QDL_PAD_DISP0_DAT8__PWM1_OUT 0x1b0b1>;
};
pinctrl_hummingboard_sgtl5000: hummingboard-sgtl5000 {
fsl,pins = <
MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0
MX6QDL_PAD_KEY_COL0__AUD5_TXC 0x130b0
MX6QDL_PAD_KEY_ROW0__AUD5_TXD 0x110b0
MX6QDL_PAD_KEY_COL1__AUD5_TXFS 0x130b0
MX6QDL_PAD_GPIO_5__CCM_CLKO1 0x130b0
>;
};
pinctrl_hummingboard_spdif: hummingboard-spdif {
fsl,pins = <MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x13091>;
};
......@@ -168,12 +245,28 @@ MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x13059
};
};
&pwm1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_pwm1>;
status = "okay";
};
&pwm2 {
pinctrl-names = "default";
status = "okay";
};
&spdif {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hummingboard_spdif>;
status = "okay";
};
&ssi1 {
fsl,mode = "i2s-slave";
status = "okay";
};
&usbh1 {
disable-over-current;
vbus-supply = <&reg_usbh1_vbus>;
......
arch/arm/boot/dts/imx6qdl-microsom-ar8035.dtsi
浏览文件 @ 8b3c8ba3
......@@ -3,6 +3,44 @@
*
* This describes the hookup for an AR8035 to the iMX6 on the SolidRun
* MicroSOM.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&fec {
pinctrl-names = "default";
......
arch/arm/boot/dts/imx6qdl-microsom.dtsi
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2013,2014 Russell King
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of the
* License.
*
* This file is distributed in the hope that it will be useful
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* Or, alternatively
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
&iomuxc {
......
arch/arm/boot/dts/imx6qdl-sabreauto.dtsi
浏览文件 @ 8b3c8ba3
......@@ -182,6 +182,34 @@ vgen6_reg: vgen6 {
};
};
&i2c3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c3>;
pinctrl-assert-gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>;
status = "okay";
max7310_a: gpio@30 {
compatible = "maxim,max7310";
reg = <0x30>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_b: gpio@32 {
compatible = "maxim,max7310";
reg = <0x32>;
gpio-controller;
#gpio-cells = <2>;
};
max7310_c: gpio@34 {
compatible = "maxim,max7310";
reg = <0x34>;
gpio-controller;
#gpio-cells = <2>;
};
};
&iomuxc {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_hog>;
......@@ -265,6 +293,13 @@ MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
>;
};
pinctrl_i2c3: i2c3grp {
fsl,pins = <
MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
>;
};
pinctrl_pwm3: pwm1grp {
fsl,pins = <
MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
......
arch/arm/boot/dts/imx6qdl.dtsi
浏览文件 @ 8b3c8ba3
......@@ -53,6 +53,7 @@ intc: interrupt-controller@00a01000 {
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
......@@ -82,7 +83,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
dma_apbh: dma-apbh@00110000 {
......@@ -122,6 +123,7 @@ timer@00a00600 {
compatible = "arm,cortex-a9-twd-timer";
reg = <0x00a00600 0x20>;
interrupts = <1 13 0xf01>;
interrupt-parent = <&intc>;
clocks = <&clks IMX6QDL_CLK_TWD>;
};
......@@ -357,6 +359,7 @@ pwm1: pwm@02080000 {
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM1>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm2: pwm@02084000 {
......@@ -367,6 +370,7 @@ pwm2: pwm@02084000 {
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM2>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm3: pwm@02088000 {
......@@ -377,6 +381,7 @@ pwm3: pwm@02088000 {
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM3>;
clock-names = "ipg", "per";
status = "disabled";
};
pwm4: pwm@0208c000 {
......@@ -387,6 +392,7 @@ pwm4: pwm@0208c000 {
clocks = <&clks IMX6QDL_CLK_IPG>,
<&clks IMX6QDL_CLK_PWM4>;
clock-names = "ipg", "per";
status = "disabled";
};
can1: flexcan@02090000 {
......@@ -598,7 +604,7 @@ reg_pu: regulator-vddpu@140 {
regulator-name = "vddpu";
regulator-min-microvolt = <725000>;
regulator-max-microvolt = <1450000>;
regulator-always-on;
regulator-enable-ramp-delay = <150>;
anatop-reg-offset = <0x140>;
anatop-vol-bit-shift = <9>;
anatop-vol-bit-width = <5>;
......@@ -658,7 +664,7 @@ snvs@020cc000 {
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
......@@ -693,8 +699,19 @@ src: src@020d8000 {
gpc: gpc@020dc000 {
compatible = "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>,
<0 90 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6QDL_CLK_GPU3D_CORE>,
<&clks IMX6QDL_CLK_GPU3D_SHADER>,
<&clks IMX6QDL_CLK_GPU2D_CORE>,
<&clks IMX6QDL_CLK_GPU2D_AXI>,
<&clks IMX6QDL_CLK_OPENVG_AXI>,
<&clks IMX6QDL_CLK_VPU_AXI>;
#power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
......@@ -845,6 +862,7 @@ usbh1: usb@02184200 {
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbphy = <&usbphy2>;
fsl,usbmisc = <&usbmisc 1>;
dr_mode = "host";
status = "disabled";
};
......@@ -854,6 +872,7 @@ usbh2: usb@02184400 {
interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
......@@ -863,6 +882,7 @@ usbh3: usb@02184600 {
interrupts = <0 42 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6QDL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 3>;
dr_mode = "host";
status = "disabled";
};
......@@ -1022,19 +1042,24 @@ mipi_dsi: mipi@021e0000 {
reg = <0x021e0000 0x4000>;
status = "disabled";
port@0 {
reg = <0>;
ports {
#address-cells = <1>;
#size-cells = <0>;
port@0 {
reg = <0>;
mipi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_mipi>;
mipi_mux_0: endpoint {
remote-endpoint = <&ipu1_di0_mipi>;
};
};
};
port@1 {
reg = <1>;
port@1 {
reg = <1>;
mipi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_mipi>;
mipi_mux_1: endpoint {
remote-endpoint = <&ipu1_di1_mipi>;
};
};
};
};
......
arch/arm/boot/dts/imx6sl-warp.dts 0 → 100644
浏览文件 @ 8b3c8ba3
/*
* Copyright 2014, 2015 O.S. Systems Software LTDA.
*
* This file is dual-licensed: you can use it either under the terms
* of the GPL or the X11 license, at your option. Note that this dual
* licensing only applies to this file, and not this project as a
* whole.
*
* a) This file is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This file is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public
* License along with this file; if not, write to the Free
* Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
* MA 02110-1301 USA
*
* Or, alternatively,
*
* b) Permission is hereby granted, free of charge, to any person
* obtaining a copy of this software and associated documentation
* files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use,
* copy, modify, merge, publish, distribute, sublicense, and/or
* sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following
* conditions:
*
* The above copyright notice and this permission notice shall be
* included in all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
* OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
* HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
* WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include "imx6sl.dtsi"
/ {
model = "WaRP Board";
compatible = "warp,imx6sl-warp", "fsl,imx6sl";
memory {
reg = <0x80000000 0x20000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
reg_usb_otg1_vbus: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 0 0>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio4 2 0>;
enable-active-high;
};
reg_1p8v: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
regulator-name = "1P8V";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
};
usdhc3_pwrseq: usdhc3_pwrseq {
compatible = "mmc-pwrseq-simple";
reset-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>, /* WL_REG_ON */
<&gpio3 25 GPIO_ACTIVE_LOW>, /* BT_REG_ON */
<&gpio4 4 GPIO_ACTIVE_LOW>, /* BT_WAKE */
<&gpio4 6 GPIO_ACTIVE_LOW>; /* BT_RST_N */
};
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart2>;
fsl,uart-has-rtscts;
status = "okay";
};
&uart3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart3>;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
dr_mode = "host";
disable-over-current;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
disable-over-current;
status = "okay";
};
&usdhc2 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc2>;
pinctrl-1 = <&pinctrl_usdhc2_100mhz>;
pinctrl-2 = <&pinctrl_usdhc2_200mhz>;
bus-width = <8>;
non-removable;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <4>;
non-removable;
keep-power-in-suspend;
enable-sdio-wakeup;
mmc-pwrseq = <&usdhc3_pwrseq>;
status = "okay";
};
&iomuxc {
imx6sl-warp {
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SL_PAD_UART1_RXD__UART1_RX_DATA 0x41b0b1
MX6SL_PAD_UART1_TXD__UART1_TX_DATA 0x41b0b1
>;
};
pinctrl_uart2: uart2grp {
fsl,pins = <
MX6SL_PAD_EPDC_D12__UART2_RX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D13__UART2_TX_DATA 0x41b0b1
MX6SL_PAD_EPDC_D14__UART2_RTS_B 0x4130B1
MX6SL_PAD_EPDC_D15__UART2_CTS_B 0x4130B1
>;
};
pinctrl_uart3: uart3grp {
fsl,pins = <
MX6SL_PAD_AUD_RXC__UART3_RX_DATA 0x41b0b1
MX6SL_PAD_AUD_RXC__UART3_TX_DATA 0x41b0b1
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x417059
MX6SL_PAD_SD2_CLK__SD2_CLK 0x410059
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x417059
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x417059
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x417059
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x417059
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x417059
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x417059
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x417059
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x417059
>;
};
pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170b9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100b9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170b9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170b9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170b9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170b9
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170b9
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170b9
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170b9
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170b9
>;
};
pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
fsl,pins = <
MX6SL_PAD_SD2_CMD__SD2_CMD 0x4170f9
MX6SL_PAD_SD2_CLK__SD2_CLK 0x4100f9
MX6SL_PAD_SD2_DAT0__SD2_DATA0 0x4170f9
MX6SL_PAD_SD2_DAT1__SD2_DATA1 0x4170f9
MX6SL_PAD_SD2_DAT2__SD2_DATA2 0x4170f9
MX6SL_PAD_SD2_DAT3__SD2_DATA3 0x4170f9
MX6SL_PAD_SD2_DAT4__SD2_DATA4 0x4170f9
MX6SL_PAD_SD2_DAT5__SD2_DATA5 0x4170f9
MX6SL_PAD_SD2_DAT6__SD2_DATA6 0x4170f9
MX6SL_PAD_SD2_DAT7__SD2_DATA7 0x4170f9
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x417059
MX6SL_PAD_SD3_CLK__SD3_CLK 0x410059
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x417059
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x417059
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x417059
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x417059
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170b9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100b9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170b9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170b9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170b9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
fsl,pins = <
MX6SL_PAD_SD3_CMD__SD3_CMD 0x4170f9
MX6SL_PAD_SD3_CLK__SD3_CLK 0x4100f9
MX6SL_PAD_SD3_DAT0__SD3_DATA0 0x4170f9
MX6SL_PAD_SD3_DAT1__SD3_DATA1 0x4170f9
MX6SL_PAD_SD3_DAT2__SD3_DATA2 0x4170f9
MX6SL_PAD_SD3_DAT3__SD3_DATA3 0x4170f9
>;
};
};
};
arch/arm/boot/dts/imx6sl.dtsi
浏览文件 @ 8b3c8ba3
......@@ -72,6 +72,7 @@ intc: interrupt-controller@00a01000 {
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
......@@ -95,7 +96,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
ocram: sram@00900000 {
......@@ -568,7 +569,7 @@ snvs@020cc000 {
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>,
......@@ -603,7 +604,14 @@ src: src@020d8000 {
gpc: gpc@020dc000 {
compatible = "fsl,imx6sl-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <0 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
pu-supply = <&reg_pu>;
clocks = <&clks IMX6SL_CLK_GPU2D_OVG>,
<&clks IMX6SL_CLK_GPU2D_PODF>;
#power-domain-cells = <1>;
};
gpr: iomuxc-gpr@020e0000 {
......@@ -699,6 +707,7 @@ usbh: usb@02184400 {
interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&clks IMX6SL_CLK_USBOH3>;
fsl,usbmisc = <&usbmisc 2>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/imx6sx-sdb-reva.dts 0 → 100644
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "imx6sx-sdb.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB RevA Board";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
reg = <0x08>;
regulators {
sw1a_reg: sw1ab {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on;
};
sw3a_reg: sw3a {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw3b_reg: sw3b {
regulator-min-microvolt = <400000>;
regulator-max-microvolt = <1975000>;
regulator-boot-on;
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
};
snvs_reg: vsnvs {
regulator-min-microvolt = <1000000>;
regulator-max-microvolt = <3000000>;
regulator-boot-on;
regulator-always-on;
};
vref_reg: vrefddr {
regulator-boot-on;
regulator-always-on;
};
vgen1_reg: vgen1 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
regulator-always-on;
};
vgen2_reg: vgen2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1550000>;
};
vgen3_reg: vgen3 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen4_reg: vgen4 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen5_reg: vgen5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
vgen6_reg: vgen6 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-always-on;
};
};
};
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: s25fl128s@0 {
reg = <0>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
flash1: s25fl128s@1 {
reg = <1>;
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
};
arch/arm/boot/dts/imx6sx-sdb.dts
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
* Copyright (C) 2015 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
#include "imx6sx-sdb.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB Board";
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_psu_5v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PSU-5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
reg_peri_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3v3>;
regulator-name = "enet_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
model = "Freescale i.MX6 SoloX SDB RevB Board";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
};
&cpu0 {
operating-points = <
/* kHz uV */
996000 1250000
792000 1175000
396000 1175000
>;
fsl,soc-operating-points = <
/* ARM kHz SOC uV */
996000 1250000
792000 1175000
396000 1175000
>;
};
&fec2 {
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
};
&i2c1 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c1>;
status = "okay";
pmic: pfuze100@08 {
compatible = "fsl,pfuze100";
compatible = "fsl,pfuze200";
reg = <0x08>;
regulators {
......@@ -203,14 +46,6 @@ sw1a_reg: sw1ab {
regulator-ramp-delay = <6250>;
};
sw1c_reg: sw1c {
regulator-min-microvolt = <300000>;
regulator-max-microvolt = <1875000>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <6250>;
};
sw2_reg: sw2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
......@@ -232,11 +67,6 @@ sw3b_reg: sw3b {
regulator-always-on;
};
sw4_reg: sw4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
};
swbst_reg: swbst {
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5150000>;
......@@ -292,401 +122,24 @@ vgen6_reg: vgen6 {
};
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SX_CLK_AUDIO>;
DCVDD-supply = <&vgen4_reg>;
DBVDD-supply = <&vgen4_reg>;
AVDD-supply = <&vgen4_reg>;
CPVDD-supply = <&vgen4_reg>;
MICVDD-supply = <&vgen3_reg>;
PLLVDD-supply = <&vgen4_reg>;
SPKVDD1-supply = <&reg_psu_5v>;
SPKVDD2-supply = <&reg_psu_5v>;
};
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&qspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_qspi2>;
status = "okay";
flash0: s25fl128s@0 {
reg = <0>;
flash0: n25q256a@0 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <0>;
};
flash1: s25fl128s@1 {
reg = <1>;
flash1: n25q256a@1 {
#address-cells = <1>;
#size-cells = <1>;
compatible = "spansion,s25fl128s";
spi-max-frequency = <66000000>;
};
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&vcc_sd3>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx6x-sdb {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_qspi2: qspi2grp {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
compatible = "micron,n25q256a";
spi-max-frequency = <29000000>;
reg = <1>;
};
};
arch/arm/boot/dts/imx6sx-sdb.dtsi 0 → 100644
浏览文件 @ 8b3c8ba3
/*
* Copyright (C) 2014 Freescale Semiconductor, Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
/dts-v1/;
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/input/input.h>
#include "imx6sx.dtsi"
/ {
model = "Freescale i.MX6 SoloX SDB Board";
compatible = "fsl,imx6sx-sdb", "fsl,imx6sx";
chosen {
stdout-path = &uart1;
};
memory {
reg = <0x80000000 0x40000000>;
};
backlight {
compatible = "pwm-backlight";
pwms = <&pwm3 0 5000000>;
brightness-levels = <0 4 8 16 32 64 128 255>;
default-brightness-level = <6>;
};
gpio-keys {
compatible = "gpio-keys";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_gpio_keys>;
volume-up {
label = "Volume Up";
gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEUP>;
};
volume-down {
label = "Volume Down";
gpios = <&gpio1 19 GPIO_ACTIVE_LOW>;
linux,code = <KEY_VOLUMEDOWN>;
};
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
#size-cells = <0>;
vcc_sd3: regulator@0 {
compatible = "regulator-fixed";
reg = <0>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_vcc_sd3>;
regulator-name = "VCC_SD3";
regulator-min-microvolt = <3000000>;
regulator-max-microvolt = <3000000>;
gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg1_vbus: regulator@1 {
compatible = "regulator-fixed";
reg = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1>;
regulator-name = "usb_otg1_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 9 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_usb_otg2_vbus: regulator@2 {
compatible = "regulator-fixed";
reg = <2>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg2>;
regulator-name = "usb_otg2_vbus";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
reg_psu_5v: regulator@3 {
compatible = "regulator-fixed";
reg = <3>;
regulator-name = "PSU-5V0";
regulator-min-microvolt = <5000000>;
regulator-max-microvolt = <5000000>;
};
reg_lcd_3v3: regulator@4 {
compatible = "regulator-fixed";
reg = <4>;
regulator-name = "lcd-3v3";
gpio = <&gpio3 27 0>;
enable-active-high;
};
reg_peri_3v3: regulator@5 {
compatible = "regulator-fixed";
reg = <5>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_peri_3v3>;
regulator-name = "peri_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>;
enable-active-high;
regulator-always-on;
};
reg_enet_3v3: regulator@6 {
compatible = "regulator-fixed";
reg = <6>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet_3v3>;
regulator-name = "enet_3v3";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
};
};
sound {
compatible = "fsl,imx6sx-sdb-wm8962", "fsl,imx-audio-wm8962";
model = "wm8962-audio";
ssi-controller = <&ssi2>;
audio-codec = <&codec>;
audio-routing =
"Headphone Jack", "HPOUTL",
"Headphone Jack", "HPOUTR",
"Ext Spk", "SPKOUTL",
"Ext Spk", "SPKOUTR",
"AMIC", "MICBIAS",
"IN3R", "AMIC";
mux-int-port = <2>;
mux-ext-port = <6>;
};
};
&audmux {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_audmux>;
status = "okay";
};
&fec1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet1>;
phy-supply = <&reg_enet_3v3>;
phy-mode = "rgmii";
phy-handle = <&ethphy1>;
status = "okay";
mdio {
#address-cells = <1>;
#size-cells = <0>;
ethphy1: ethernet-phy@1 {
reg = <1>;
};
ethphy2: ethernet-phy@2 {
reg = <2>;
};
};
};
&fec2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet2>;
phy-mode = "rgmii";
phy-handle = <&ethphy2>;
status = "okay";
};
&i2c4 {
clock-frequency = <100000>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_i2c4>;
status = "okay";
codec: wm8962@1a {
compatible = "wlf,wm8962";
reg = <0x1a>;
clocks = <&clks IMX6SX_CLK_AUDIO>;
DCVDD-supply = <&vgen4_reg>;
DBVDD-supply = <&vgen4_reg>;
AVDD-supply = <&vgen4_reg>;
CPVDD-supply = <&vgen4_reg>;
MICVDD-supply = <&vgen3_reg>;
PLLVDD-supply = <&vgen4_reg>;
SPKVDD1-supply = <&reg_psu_5v>;
SPKVDD2-supply = <&reg_psu_5v>;
};
};
&lcdif1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_lcd>;
lcd-supply = <&reg_lcd_3v3>;
display = <&display0>;
status = "okay";
display0: display0 {
bits-per-pixel = <16>;
bus-width = <24>;
display-timings {
native-mode = <&timing0>;
timing0: timing0 {
clock-frequency = <33500000>;
hactive = <800>;
vactive = <480>;
hback-porch = <89>;
hfront-porch = <164>;
vback-porch = <23>;
vfront-porch = <10>;
hsync-len = <10>;
vsync-len = <10>;
hsync-active = <0>;
vsync-active = <0>;
de-active = <1>;
pixelclk-active = <0>;
};
};
};
};
&pwm3 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pwm3>;
status = "okay";
};
&snvs_poweroff {
status = "okay";
};
&ssi2 {
status = "okay";
};
&uart1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart1>;
status = "okay";
};
&uart5 { /* for bluetooth */
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_uart5>;
fsl,uart-has-rtscts;
status = "okay";
};
&usbotg1 {
vbus-supply = <&reg_usb_otg1_vbus>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usb_otg1_id>;
status = "okay";
};
&usbotg2 {
vbus-supply = <&reg_usb_otg2_vbus>;
dr_mode = "host";
status = "okay";
};
&usdhc2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>;
non-removable;
no-1-8-v;
keep-power-in-suspend;
enable-sdio-wakeup;
status = "okay";
};
&usdhc3 {
pinctrl-names = "default", "state_100mhz", "state_200mhz";
pinctrl-0 = <&pinctrl_usdhc3>;
pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
bus-width = <8>;
cd-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
keep-power-in-suspend;
enable-sdio-wakeup;
vmmc-supply = <&vcc_sd3>;
status = "okay";
};
&usdhc4 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc4>;
cd-gpios = <&gpio6 21 GPIO_ACTIVE_HIGH>;
wp-gpios = <&gpio6 20 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&iomuxc {
imx6x-sdb {
pinctrl_audmux: audmuxgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA00__AUDMUX_AUD6_TXC 0x130b0
MX6SX_PAD_CSI_DATA01__AUDMUX_AUD6_TXFS 0x130b0
MX6SX_PAD_CSI_HSYNC__AUDMUX_AUD6_TXD 0x120b0
MX6SX_PAD_CSI_VSYNC__AUDMUX_AUD6_RXD 0x130b0
MX6SX_PAD_CSI_PIXCLK__AUDMUX_MCLK 0x130b0
>;
};
pinctrl_enet1: enet1grp {
fsl,pins = <
MX6SX_PAD_ENET1_MDIO__ENET1_MDIO 0xa0b1
MX6SX_PAD_ENET1_MDC__ENET1_MDC 0xa0b1
MX6SX_PAD_RGMII1_TXC__ENET1_RGMII_TXC 0xa0b1
MX6SX_PAD_RGMII1_TD0__ENET1_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII1_TD1__ENET1_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII1_TD2__ENET1_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII1_TD3__ENET1_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII1_TX_CTL__ENET1_TX_EN 0xa0b1
MX6SX_PAD_RGMII1_RXC__ENET1_RX_CLK 0x3081
MX6SX_PAD_RGMII1_RD0__ENET1_RX_DATA_0 0x3081
MX6SX_PAD_RGMII1_RD1__ENET1_RX_DATA_1 0x3081
MX6SX_PAD_RGMII1_RD2__ENET1_RX_DATA_2 0x3081
MX6SX_PAD_RGMII1_RD3__ENET1_RX_DATA_3 0x3081
MX6SX_PAD_RGMII1_RX_CTL__ENET1_RX_EN 0x3081
MX6SX_PAD_ENET2_RX_CLK__ENET2_REF_CLK_25M 0x91
>;
};
pinctrl_enet_3v3: enet3v3grp {
fsl,pins = <
MX6SX_PAD_ENET2_COL__GPIO2_IO_6 0x80000000
>;
};
pinctrl_enet2: enet2grp {
fsl,pins = <
MX6SX_PAD_RGMII2_TXC__ENET2_RGMII_TXC 0xa0b9
MX6SX_PAD_RGMII2_TD0__ENET2_TX_DATA_0 0xa0b1
MX6SX_PAD_RGMII2_TD1__ENET2_TX_DATA_1 0xa0b1
MX6SX_PAD_RGMII2_TD2__ENET2_TX_DATA_2 0xa0b1
MX6SX_PAD_RGMII2_TD3__ENET2_TX_DATA_3 0xa0b1
MX6SX_PAD_RGMII2_TX_CTL__ENET2_TX_EN 0xa0b1
MX6SX_PAD_RGMII2_RXC__ENET2_RX_CLK 0x3081
MX6SX_PAD_RGMII2_RD0__ENET2_RX_DATA_0 0x3081
MX6SX_PAD_RGMII2_RD1__ENET2_RX_DATA_1 0x3081
MX6SX_PAD_RGMII2_RD2__ENET2_RX_DATA_2 0x3081
MX6SX_PAD_RGMII2_RD3__ENET2_RX_DATA_3 0x3081
MX6SX_PAD_RGMII2_RX_CTL__ENET2_RX_EN 0x3081
>;
};
pinctrl_gpio_keys: gpio_keysgrp {
fsl,pins = <
MX6SX_PAD_CSI_DATA04__GPIO1_IO_18 0x17059
MX6SX_PAD_CSI_DATA05__GPIO1_IO_19 0x17059
>;
};
pinctrl_i2c1: i2c1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO01__I2C1_SDA 0x4001b8b1
MX6SX_PAD_GPIO1_IO00__I2C1_SCL 0x4001b8b1
>;
};
pinctrl_i2c4: i2c4grp {
fsl,pins = <
MX6SX_PAD_CSI_DATA07__I2C4_SDA 0x4001b8b1
MX6SX_PAD_CSI_DATA06__I2C4_SCL 0x4001b8b1
>;
};
pinctrl_lcd: lcdgrp {
fsl,pins = <
MX6SX_PAD_LCD1_DATA00__LCDIF1_DATA_0 0x4001b0b0
MX6SX_PAD_LCD1_DATA01__LCDIF1_DATA_1 0x4001b0b0
MX6SX_PAD_LCD1_DATA02__LCDIF1_DATA_2 0x4001b0b0
MX6SX_PAD_LCD1_DATA03__LCDIF1_DATA_3 0x4001b0b0
MX6SX_PAD_LCD1_DATA04__LCDIF1_DATA_4 0x4001b0b0
MX6SX_PAD_LCD1_DATA05__LCDIF1_DATA_5 0x4001b0b0
MX6SX_PAD_LCD1_DATA06__LCDIF1_DATA_6 0x4001b0b0
MX6SX_PAD_LCD1_DATA07__LCDIF1_DATA_7 0x4001b0b0
MX6SX_PAD_LCD1_DATA08__LCDIF1_DATA_8 0x4001b0b0
MX6SX_PAD_LCD1_DATA09__LCDIF1_DATA_9 0x4001b0b0
MX6SX_PAD_LCD1_DATA10__LCDIF1_DATA_10 0x4001b0b0
MX6SX_PAD_LCD1_DATA11__LCDIF1_DATA_11 0x4001b0b0
MX6SX_PAD_LCD1_DATA12__LCDIF1_DATA_12 0x4001b0b0
MX6SX_PAD_LCD1_DATA13__LCDIF1_DATA_13 0x4001b0b0
MX6SX_PAD_LCD1_DATA14__LCDIF1_DATA_14 0x4001b0b0
MX6SX_PAD_LCD1_DATA15__LCDIF1_DATA_15 0x4001b0b0
MX6SX_PAD_LCD1_DATA16__LCDIF1_DATA_16 0x4001b0b0
MX6SX_PAD_LCD1_DATA17__LCDIF1_DATA_17 0x4001b0b0
MX6SX_PAD_LCD1_DATA18__LCDIF1_DATA_18 0x4001b0b0
MX6SX_PAD_LCD1_DATA19__LCDIF1_DATA_19 0x4001b0b0
MX6SX_PAD_LCD1_DATA20__LCDIF1_DATA_20 0x4001b0b0
MX6SX_PAD_LCD1_DATA21__LCDIF1_DATA_21 0x4001b0b0
MX6SX_PAD_LCD1_DATA22__LCDIF1_DATA_22 0x4001b0b0
MX6SX_PAD_LCD1_DATA23__LCDIF1_DATA_23 0x4001b0b0
MX6SX_PAD_LCD1_CLK__LCDIF1_CLK 0x4001b0b0
MX6SX_PAD_LCD1_ENABLE__LCDIF1_ENABLE 0x4001b0b0
MX6SX_PAD_LCD1_VSYNC__LCDIF1_VSYNC 0x4001b0b0
MX6SX_PAD_LCD1_HSYNC__LCDIF1_HSYNC 0x4001b0b0
MX6SX_PAD_LCD1_RESET__GPIO3_IO_27 0x4001b0b0
>;
};
pinctrl_peri_3v3: peri3v3grp {
fsl,pins = <
MX6SX_PAD_QSPI1A_DATA0__GPIO4_IO_16 0x80000000
>;
};
pinctrl_pwm3: pwm3grp-1 {
fsl,pins = <
MX6SX_PAD_SD1_DATA2__PWM3_OUT 0x110b0
>;
};
pinctrl_qspi2: qspi2grp {
fsl,pins = <
MX6SX_PAD_NAND_WP_B__QSPI2_A_DATA_0 0x70f1
MX6SX_PAD_NAND_READY_B__QSPI2_A_DATA_1 0x70f1
MX6SX_PAD_NAND_CE0_B__QSPI2_A_DATA_2 0x70f1
MX6SX_PAD_NAND_CE1_B__QSPI2_A_DATA_3 0x70f1
MX6SX_PAD_NAND_CLE__QSPI2_A_SCLK 0x70f1
MX6SX_PAD_NAND_ALE__QSPI2_A_SS0_B 0x70f1
MX6SX_PAD_NAND_DATA01__QSPI2_B_DATA_0 0x70f1
MX6SX_PAD_NAND_DATA00__QSPI2_B_DATA_1 0x70f1
MX6SX_PAD_NAND_WE_B__QSPI2_B_DATA_2 0x70f1
MX6SX_PAD_NAND_RE_B__QSPI2_B_DATA_3 0x70f1
MX6SX_PAD_NAND_DATA02__QSPI2_B_SCLK 0x70f1
MX6SX_PAD_NAND_DATA03__QSPI2_B_SS0_B 0x70f1
>;
};
pinctrl_vcc_sd3: vccsd3grp {
fsl,pins = <
MX6SX_PAD_KEY_COL1__GPIO2_IO_11 0x17059
>;
};
pinctrl_uart1: uart1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO04__UART1_TX 0x1b0b1
MX6SX_PAD_GPIO1_IO05__UART1_RX 0x1b0b1
>;
};
pinctrl_uart5: uart5grp {
fsl,pins = <
MX6SX_PAD_KEY_ROW3__UART5_RX 0x1b0b1
MX6SX_PAD_KEY_COL3__UART5_TX 0x1b0b1
MX6SX_PAD_KEY_ROW2__UART5_CTS_B 0x1b0b1
MX6SX_PAD_KEY_COL2__UART5_RTS_B 0x1b0b1
>;
};
pinctrl_usb_otg1: usbotg1grp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO09__GPIO1_IO_9 0x10b0
>;
};
pinctrl_usb_otg1_id: usbotg1idgrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO10__ANATOP_OTG1_ID 0x17059
>;
};
pinctrl_usb_otg2: usbot2ggrp {
fsl,pins = <
MX6SX_PAD_GPIO1_IO12__GPIO1_IO_12 0x10b0
>;
};
pinctrl_usdhc2: usdhc2grp {
fsl,pins = <
MX6SX_PAD_SD2_CMD__USDHC2_CMD 0x17059
MX6SX_PAD_SD2_CLK__USDHC2_CLK 0x10059
MX6SX_PAD_SD2_DATA0__USDHC2_DATA0 0x17059
MX6SX_PAD_SD2_DATA1__USDHC2_DATA1 0x17059
MX6SX_PAD_SD2_DATA2__USDHC2_DATA2 0x17059
MX6SX_PAD_SD2_DATA3__USDHC2_DATA3 0x17059
>;
};
pinctrl_usdhc3: usdhc3grp {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x17059
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x10059
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x17059
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x17059
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x17059
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x17059
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x17059
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x17059
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x17059
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x17059
MX6SX_PAD_KEY_COL0__GPIO2_IO_10 0x17059 /* CD */
MX6SX_PAD_KEY_ROW0__GPIO2_IO_15 0x17059 /* WP */
>;
};
pinctrl_usdhc3_100mhz: usdhc3grp-100mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170b9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100b9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170b9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170b9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170b9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170b9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170b9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170b9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170b9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170b9
>;
};
pinctrl_usdhc3_200mhz: usdhc3grp-200mhz {
fsl,pins = <
MX6SX_PAD_SD3_CMD__USDHC3_CMD 0x170f9
MX6SX_PAD_SD3_CLK__USDHC3_CLK 0x100f9
MX6SX_PAD_SD3_DATA0__USDHC3_DATA0 0x170f9
MX6SX_PAD_SD3_DATA1__USDHC3_DATA1 0x170f9
MX6SX_PAD_SD3_DATA2__USDHC3_DATA2 0x170f9
MX6SX_PAD_SD3_DATA3__USDHC3_DATA3 0x170f9
MX6SX_PAD_SD3_DATA4__USDHC3_DATA4 0x170f9
MX6SX_PAD_SD3_DATA5__USDHC3_DATA5 0x170f9
MX6SX_PAD_SD3_DATA6__USDHC3_DATA6 0x170f9
MX6SX_PAD_SD3_DATA7__USDHC3_DATA7 0x170f9
>;
};
pinctrl_usdhc4: usdhc4grp {
fsl,pins = <
MX6SX_PAD_SD4_CMD__USDHC4_CMD 0x17059
MX6SX_PAD_SD4_CLK__USDHC4_CLK 0x10059
MX6SX_PAD_SD4_DATA0__USDHC4_DATA0 0x17059
MX6SX_PAD_SD4_DATA1__USDHC4_DATA1 0x17059
MX6SX_PAD_SD4_DATA2__USDHC4_DATA2 0x17059
MX6SX_PAD_SD4_DATA3__USDHC4_DATA3 0x17059
MX6SX_PAD_SD4_DATA7__GPIO6_IO_21 0x17059 /* CD */
MX6SX_PAD_SD4_DATA6__GPIO6_IO_20 0x17059 /* WP */
>;
};
};
};
arch/arm/boot/dts/imx6sx.dtsi
浏览文件 @ 8b3c8ba3
......@@ -88,6 +88,7 @@ intc: interrupt-controller@00a01000 {
interrupt-controller;
reg = <0x00a01000 0x1000>,
<0x00a00100 0x100>;
interrupt-parent = <&intc>;
};
clocks {
......@@ -131,7 +132,7 @@ soc {
#address-cells = <1>;
#size-cells = <1>;
compatible = "simple-bus";
interrupt-parent = <&intc>;
interrupt-parent = <&gpc>;
ranges;
pmu {
......@@ -666,7 +667,7 @@ snvs: snvs@020cc000 {
#size-cells = <1>;
ranges = <0 0x020cc000 0x4000>;
snvs-rtc-lp@34 {
snvs_rtc: snvs-rtc-lp@34 {
compatible = "fsl,sec-v4.0-mon-rtc-lp";
reg = <0x34 0x58>;
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
......@@ -700,7 +701,10 @@ src: src@020d8000 {
gpc: gpc@020dc000 {
compatible = "fsl,imx6sx-gpc", "fsl,imx6q-gpc";
reg = <0x020dc000 0x4000>;
interrupt-controller;
#interrupt-cells = <3>;
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
};
iomuxc: iomuxc@020e0000 {
......@@ -763,6 +767,7 @@ usbh: usb@02184400 {
fsl,usbmisc = <&usbmisc 2>;
phy_type = "hsic";
fsl,anatop = <&anatop>;
dr_mode = "host";
status = "disabled";
};
......
arch/arm/boot/dts/omap2420.dtsi
浏览文件 @ 8b3c8ba3
......@@ -14,47 +14,65 @@ / {
compatible = "ti,omap2420", "ti,omap2";
ocp {
prcm: prcm@48008000 {
compatible = "ti,omap2-prcm";
reg = <0x48008000 0x1000>;
l4: l4@48000000 {
compatible = "ti,omap2-l4", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x100000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm: prcm@8000 {
compatible = "ti,omap2-prcm";
reg = <0x8000 0x1000>;
prcm_clockdomains: clockdomains {
};
};
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm: scrm@48000000 {
compatible = "ti,omap2-scrm";
reg = <0x48000000 0x1000>;
prcm_clockdomains: clockdomains {
};
};
scrm_clocks: clocks {
scm: scm@0 {
compatible = "ti,omap2-scm", "simple-bus";
reg = <0x0 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x0 0x1000>;
omap2420_pmx: pinmux@30 {
compatible = "ti,omap2420-padconf",
"pinctrl-single";
reg = <0x30 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x100>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
};
scrm_clockdomains: clockdomains {
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
};
};
counter32k: counter@48004000 {
compatible = "ti,omap-counter32k";
reg = <0x48004000 0x20>;
ti,hwmods = "counter_32k";
};
omap2420_pmx: pinmux@48000030 {
compatible = "ti,omap2420-padconf", "pinctrl-single";
reg = <0x48000030 0x0113>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
gpio1: gpio@48018000 {
compatible = "ti,omap2-gpio";
reg = <0x48018000 0x200>;
......
arch/arm/boot/dts/omap2430-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -8,12 +8,12 @@
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp3_fck: mcbsp3_fck {
......@@ -27,7 +27,7 @@ mcbsp4_mux_fck: mcbsp4_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp4_fck: mcbsp4_fck {
......@@ -41,7 +41,7 @@ mcbsp5_mux_fck: mcbsp5_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02e8>;
reg = <0x78>;
};
mcbsp5_fck: mcbsp5_fck {
......
arch/arm/boot/dts/omap2430.dtsi
浏览文件 @ 8b3c8ba3
......@@ -14,60 +14,73 @@ / {
compatible = "ti,omap2430", "ti,omap2";
ocp {
prcm: prcm@49006000 {
compatible = "ti,omap2-prcm";
reg = <0x49006000 0x1000>;
l4_wkup: l4_wkup@49000000 {
compatible = "ti,omap2-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x49000000 0x31000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prcm: prcm@6000 {
compatible = "ti,omap2-prcm";
reg = <0x6000 0x1000>;
prcm_clockdomains: clockdomains {
};
};
scrm: scrm@49002000 {
compatible = "ti,omap2-scrm";
reg = <0x49002000 0x1000>;
prcm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
prcm_clockdomains: clockdomains {
};
};
scrm_clockdomains: clockdomains {
scm: scm@2000 {
compatible = "ti,omap2-scm", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
omap2430_pmx: pinmux@30 {
compatible = "ti,omap2430-padconf",
"pinctrl-single";
reg = <0x30 0x0154>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x240>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
scm_clockdomains: clockdomains {
};
};
};
counter32k: counter@49020000 {
compatible = "ti,omap-counter32k";
reg = <0x49020000 0x20>;
ti,hwmods = "counter_32k";
};
omap2430_pmx: pinmux@49002030 {
compatible = "ti,omap2430-padconf", "pinctrl-single";
reg = <0x49002030 0x0154>;
#address-cells = <1>;
#size-cells = <0>;
pinctrl-single,register-width = <8>;
pinctrl-single,function-mask = <0x3f>;
};
omap2_scm_general: tisyscon@49002270 {
compatible = "syscon";
reg = <0x49002270 0x240>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x230 0x4>;
syscon = <&omap2_scm_general>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
counter32k: counter@20000 {
compatible = "ti,omap-counter32k";
reg = <0x20000 0x20>;
ti,hwmods = "counter_32k";
};
};
......
arch/arm/boot/dts/omap24xx-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -7,13 +7,13 @@
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
&scrm_clocks {
&scm_clocks {
mcbsp1_mux_fck: mcbsp1_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x0274>;
reg = <0x4>;
};
mcbsp1_fck: mcbsp1_fck {
......@@ -27,7 +27,7 @@ mcbsp2_mux_fck: mcbsp2_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&func_96m_ck>, <&mcbsp_clks>;
ti,bit-shift = <6>;
reg = <0x0274>;
reg = <0x4>;
};
mcbsp2_fck: mcbsp2_fck {
......
arch/arm/boot/dts/omap3.dtsi
浏览文件 @ 8b3c8ba3
......@@ -87,6 +87,60 @@ ocp {
ranges;
ti,hwmods = "l3_main";
l4_core: l4@48000000 {
compatible = "ti,omap3-l4-core", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x48000000 0x1000000>;
scm: scm@2000 {
compatible = "ti,omap3-scm", "simple-bus";
reg = <0x2000 0x2000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x2000>;
omap3_pmx_core: pinmux@30 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0x30 0x238>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
scm_conf: scm_conf@270 {
compatible = "syscon";
reg = <0x270 0x330>;
#address-cells = <1>;
#size-cells = <1>;
scm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
};
scm_clockdomains: clockdomains {
};
omap3_pmx_wkup: pinmux@a00 {
compatible = "ti,omap3-padconf",
"pinctrl-single";
reg = <0xa00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
};
};
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
......@@ -123,19 +177,6 @@ cm_clockdomains: clockdomains {
};
};
scrm: scrm@48002000 {
compatible = "ti,omap3-scrm";
reg = <0x48002000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@48320000 {
compatible = "ti,omap-counter32k";
reg = <0x48320000 0x20>;
......@@ -161,37 +202,10 @@ sdma: dma-controller@48056000 {
dma-requests = <96>;
};
omap3_pmx_core: pinmux@48002030 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002030 0x0238>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_pmx_wkup: pinmux@48002a00 {
compatible = "ti,omap3-padconf", "pinctrl-single";
reg = <0x48002a00 0x5c>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0xff1f>;
};
omap3_scm_general: tisyscon@48002270 {
compatible = "syscon";
reg = <0x48002270 0x2f0>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x2b0 0x4>;
syscon = <&omap3_scm_general>;
syscon = <&scm_conf>;
pbias_mmc_reg: pbias_mmc_omap2430 {
regulator-name = "pbias_mmc_omap2430";
regulator-min-microvolt = <1800000>;
......
arch/arm/boot/dts/omap34xx.dtsi
浏览文件 @ 8b3c8ba3
......@@ -46,7 +46,7 @@ isp: isp@480bc000 {
0x480bd800 0x017c>;
interrupts = <24>;
iommus = <&mmu_isp>;
syscon = <&omap3_scm_general 0xdc>;
syscon = <&scm_conf 0xdc>;
ti,phy-type = <OMAP3ISP_PHY_TYPE_COMPLEX_IO>;
#clock-cells = <1>;
ports {
......
arch/arm/boot/dts/omap36xx.dtsi
浏览文件 @ 8b3c8ba3
......@@ -78,7 +78,7 @@ isp: isp@480bc000 {
0x480bd800 0x0600>;
interrupts = <24>;
iommus = <&mmu_isp>;
syscon = <&omap3_scm_general 0x2f0>;
syscon = <&scm_conf 0x2f0>;
ti,phy-type = <OMAP3ISP_PHY_TYPE_CSIPHY>;
#clock-cells = <1>;
ports {
......
arch/arm/boot/dts/omap3xxx-clocks.dtsi
浏览文件 @ 8b3c8ba3
......@@ -79,13 +79,14 @@ wkup_l4_ick: wkup_l4_ick {
clock-div = <1>;
};
};
&scrm_clocks {
&scm_clocks {
mcbsp5_mux_fck: mcbsp5_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <4>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp5_fck: mcbsp5_fck {
......@@ -99,7 +100,7 @@ mcbsp1_mux_fck: mcbsp1_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&core_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x0274>;
reg = <0x04>;
};
mcbsp1_fck: mcbsp1_fck {
......@@ -113,7 +114,7 @@ mcbsp2_mux_fck: mcbsp2_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <6>;
reg = <0x0274>;
reg = <0x04>;
};
mcbsp2_fck: mcbsp2_fck {
......@@ -126,7 +127,7 @@ mcbsp3_mux_fck: mcbsp3_mux_fck {
#clock-cells = <0>;
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp3_fck: mcbsp3_fck {
......@@ -140,7 +141,7 @@ mcbsp4_mux_fck: mcbsp4_mux_fck {
compatible = "ti,composite-mux-clock";
clocks = <&per_96m_fck>, <&mcbsp_clks>;
ti,bit-shift = <2>;
reg = <0x02d8>;
reg = <0x68>;
};
mcbsp4_fck: mcbsp4_fck {
......
arch/arm/boot/dts/omap4.dtsi
浏览文件 @ 8b3c8ba3
......@@ -124,99 +124,141 @@ ocp {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
cm1: cm1@4a004000 {
compatible = "ti,omap4-cm1";
reg = <0x4a004000 0x2000>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
l4_cfg: l4@4a000000 {
compatible = "ti,omap4-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x1000000>;
cm1_clockdomains: clockdomains {
};
};
cm1: cm1@4000 {
compatible = "ti,omap4-cm1";
reg = <0x4000 0x2000>;
prm: prm@4a306000 {
compatible = "ti,omap4-prm";
reg = <0x4a306000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
cm1_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
cm1_clockdomains: clockdomains {
};
};
prm_clockdomains: clockdomains {
};
};
cm2: cm2@8000 {
compatible = "ti,omap4-cm2";
reg = <0x8000 0x3000>;
cm2: cm2@4a008000 {
compatible = "ti,omap4-cm2";
reg = <0x4a008000 0x3000>;
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm2_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
cm2_clockdomains: clockdomains {
};
};
cm2_clockdomains: clockdomains {
omap4_scm_core: scm@2000 {
compatible = "ti,omap4-scm-core", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2000 0x1000>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
};
scrm: scrm@4a30a000 {
compatible = "ti,omap4-scrm";
reg = <0x4a30a000 0x2000>;
scrm_clocks: clocks {
omap4_padconf_core: scm@100000 {
compatible = "ti,omap4-scm-padconf-core",
"simple-bus";
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x100000 0x1000>;
omap4_pmx_core: pinmux@40 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x40 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_padconf_global: omap4_padconf_global@5a0 {
compatible = "syscon";
reg = <0x5a0 0x170>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
regulator-name = "pbias_mmc_omap4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
};
scrm_clockdomains: clockdomains {
};
};
counter32k: counter@4a304000 {
compatible = "ti,omap-counter32k";
reg = <0x4a304000 0x20>;
ti,hwmods = "counter_32k";
};
omap4_pmx_core: pinmux@4a100040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a100040 0x0196>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_pmx_wkup: pinmux@4a31e040 {
compatible = "ti,omap4-padconf", "pinctrl-single";
reg = <0x4a31e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap4_padconf_global: tisyscon@4a1005a0 {
compatible = "syscon";
reg = <0x4a1005a0 0x170>;
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap4_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap4 {
regulator-name = "pbias_mmc_omap4";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
l4_wkup: l4@300000 {
compatible = "ti,omap4-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x300000 0x40000>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x20>;
ti,hwmods = "counter_32k";
};
prm: prm@6000 {
compatible = "ti,omap4-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
scrm: scrm@a000 {
compatible = "ti,omap4-scrm";
reg = <0xa000 0x2000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
};
};
omap4_pmx_wkup: pinmux@1e040 {
compatible = "ti,omap4-padconf",
"pinctrl-single";
reg = <0x1e040 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
};
};
......
arch/arm/boot/dts/omap5.dtsi
浏览文件 @ 8b3c8ba3
......@@ -139,99 +139,141 @@ ocp {
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
prm: prm@4ae06000 {
compatible = "ti,omap5-prm";
reg = <0x4ae06000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
l4_cfg: l4@4a000000 {
compatible = "ti,omap5-l4-cfg", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4a000000 0x22a000>;
prm_clocks: clocks {
scm_core: scm@2000 {
compatible = "ti,omap5-scm-core", "simple-bus";
reg = <0x2000 0x1000>;
#address-cells = <1>;
#size-cells = <0>;
#size-cells = <1>;
ranges = <0 0x2000 0x800>;
scm_conf: scm_conf@0 {
compatible = "syscon";
reg = <0x0 0x800>;
#address-cells = <1>;
#size-cells = <1>;
};
};
prm_clockdomains: clockdomains {
scm_padconf_core: scm@2800 {
compatible = "ti,omap5-scm-padconf-core",
"simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x2800 0x800>;
omap5_pmx_core: pinmux@40 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0x40 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_padconf_global: omap5_padconf_global@5a0 {
compatible = "syscon";
reg = <0x5a0 0xec>;
#address-cells = <1>;
#size-cells = <1>;
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
};
};
};
};
};
cm_core_aon: cm_core_aon@4a004000 {
compatible = "ti,omap5-cm-core-aon";
reg = <0x4a004000 0x2000>;
cm_core_aon: cm_core_aon@4000 {
compatible = "ti,omap5-cm-core-aon";
reg = <0x4000 0x2000>;
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_aon_clockdomains: clockdomains {
cm_core_aon_clockdomains: clockdomains {
};
};
};
scrm: scrm@4ae0a000 {
compatible = "ti,omap5-scrm";
reg = <0x4ae0a000 0x2000>;
cm_core: cm_core@8000 {
compatible = "ti,omap5-cm-core";
reg = <0x8000 0x3000>;
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
scrm_clockdomains: clockdomains {
cm_core_clockdomains: clockdomains {
};
};
};
cm_core: cm_core@4a008000 {
compatible = "ti,omap5-cm-core";
reg = <0x4a008000 0x3000>;
l4_wkup: l4@4ae00000 {
compatible = "ti,omap5-l4-wkup", "simple-bus";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x4ae00000 0x2b000>;
cm_core_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
counter32k: counter@4000 {
compatible = "ti,omap-counter32k";
reg = <0x4000 0x40>;
ti,hwmods = "counter_32k";
};
cm_core_clockdomains: clockdomains {
prm: prm@6000 {
compatible = "ti,omap5-prm";
reg = <0x6000 0x3000>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
prm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
prm_clockdomains: clockdomains {
};
};
};
counter32k: counter@4ae04000 {
compatible = "ti,omap-counter32k";
reg = <0x4ae04000 0x40>;
ti,hwmods = "counter_32k";
};
scrm: scrm@a000 {
compatible = "ti,omap5-scrm";
reg = <0xa000 0x2000>;
omap5_pmx_core: pinmux@4a002840 {
compatible = "ti,omap5-padconf", "pinctrl-single";
reg = <0x4a002840 0x01b6>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
omap5_pmx_wkup: pinmux@4ae0c840 {
compatible = "ti,omap5-padconf", "pinctrl-single";
reg = <0x4ae0c840 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
scrm_clocks: clocks {
#address-cells = <1>;
#size-cells = <0>;
};
omap5_padconf_global: tisyscon@4a002da0 {
compatible = "syscon";
reg = <0x4A002da0 0xec>;
};
scrm_clockdomains: clockdomains {
};
};
pbias_regulator: pbias_regulator {
compatible = "ti,pbias-omap";
reg = <0x60 0x4>;
syscon = <&omap5_padconf_global>;
pbias_mmc_reg: pbias_mmc_omap5 {
regulator-name = "pbias_mmc_omap5";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3000000>;
omap5_pmx_wkup: pinmux@c840 {
compatible = "ti,omap5-padconf",
"pinctrl-single";
reg = <0xc840 0x0038>;
#address-cells = <1>;
#size-cells = <0>;
#interrupt-cells = <1>;
interrupt-controller;
pinctrl-single,register-width = <16>;
pinctrl-single,function-mask = <0x7fff>;
};
};
......
arch/arm/boot/dts/vf-colibri-eval-v3.dtsi
浏览文件 @ 8b3c8ba3
......@@ -12,6 +12,12 @@ chosen {
bootargs = "console=ttyLP0,115200";
};
clk16m: clk16m {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <16000000>;
};
regulators {
compatible = "simple-bus";
#address-cells = <1>;
......@@ -47,6 +53,21 @@ &bl {
status = "okay";
};
&dspi1 {
status = "okay";
mcp2515can: can@0 {
compatible = "microchip,mcp2515";
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_can_int>;
reg = <0>;
clocks = <&clk16m>;
spi-max-frequency = <10000000>;
interrupt-parent = <&gpio1>;
interrupts = <11 GPIO_ACTIVE_LOW>;
};
};
&esdhc1 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_esdhc1>;
......@@ -94,3 +115,13 @@ &uart2 {
&usbh1 {
vbus-supply = <&usbh_vbus_reg>;
};
&iomuxc {
vf610-colibri {
pinctrl_can_int: can_int {
fsl,pins = <
VF610_PAD_PTB21__GPIO_43 0x22ed
>;
};
};
};
arch/arm/boot/dts/vf-colibri.dtsi
浏览文件 @ 8b3c8ba3
......@@ -23,6 +23,12 @@ &adc1 {
status = "okay";
};
&dspi1 {
bus-num = <1>;
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_dspi1>;
};
&edma0 {
status = "okay";
};
......@@ -107,6 +113,15 @@ VF610_PAD_PTD26__GPIO_68 0x22ed /* EXT_IO_2 */
>;
};
pinctrl_dspi1: dspi1grp {
fsl,pins = <
VF610_PAD_PTD5__DSPI1_CS0 0x33e2
VF610_PAD_PTD6__DSPI1_SIN 0x33e1
VF610_PAD_PTD7__DSPI1_SOUT 0x33e2
VF610_PAD_PTD8__DSPI1_SCK 0x33e2
>;
};
pinctrl_esdhc1: esdhc1grp {
fsl,pins = <
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
......
arch/arm/boot/dts/vf500.dtsi
浏览文件 @ 8b3c8ba3
......@@ -24,14 +24,13 @@ a5_cpu: cpu@0 {
};
soc {
interrupt-parent = <&intc>;
aips-bus@40000000 {
intc: interrupt-controller@40002000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
interrupt-controller;
interrupt-parent = <&intc>;
reg = <0x40003000 0x1000>,
<0x40002100 0x100>;
};
......@@ -40,145 +39,17 @@ global_timer: timer@40002200 {
compatible = "arm,cortex-a9-global-timer";
reg = <0x40002200 0x20>;
interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-parent = <&intc>;
clocks = <&clks VF610_CLK_PLATFORM_BUS>;
};
};
};
};
&adc0 {
interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
};
&adc1 {
interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
};
&can0 {
interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
};
&can1 {
interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
};
&dspi0 {
interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
};
&edma0 {
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
};
&edma1 {
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "edma-tx", "edma-err";
};
&esdhc1 {
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
};
&fec0 {
interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
};
&fec1 {
interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
};
&ftm {
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio0 {
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio1 {
interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio2 {
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio3 {
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
};
&gpio4 {
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
};
&i2c0 {
interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
};
&pit {
interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
};
&qspi0 {
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
};
&sai2 {
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
};
&snvsrtc {
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
};
&src {
interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
};
&uart0 {
interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
};
&uart1 {
interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
};
&uart2 {
interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
};
&uart3 {
interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
};
&uart4 {
interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
};
&uart5 {
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
};
&usbdev0 {
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
};
&usbh1 {
interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
};
&usbphy0 {
interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
};
&usbphy1 {
interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
&mscm_ir {
interrupt-parent = <&intc>;
};
&wdoga5 {
interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
status = "okay";
};
arch/arm/boot/dts/vfxxx.dtsi
浏览文件 @ 8b3c8ba3
此差异已折叠。
arch/arm/mach-imx/common.h
浏览文件 @ 8b3c8ba3
......@@ -66,6 +66,7 @@ unsigned int imx_get_soc_revision(void);
void imx_init_revision_from_anatop(void);
struct device *imx_soc_device_init(void);
void imx6_enable_rbc(bool enable);
void imx_gpc_check_dt(void);
void imx_gpc_set_arm_power_in_lpm(bool power_off);
void imx_gpc_set_arm_power_up_timing(u32 sw2iso, u32 sw);
void imx_gpc_set_arm_power_down_timing(u32 sw2iso, u32 sw);
......@@ -101,7 +102,6 @@ static inline void imx_scu_map_io(void) {}
static inline void imx_smp_prepare(void) {}
#endif
void imx_src_init(void);
void imx_gpc_init(void);
void imx_gpc_pre_suspend(bool arm_power_off);
void imx_gpc_post_resume(void);
void imx_gpc_mask_all(void);
......
arch/arm/mach-imx/gpc.c
浏览文件 @ 8b3c8ba3
此差异已折叠。
arch/arm/mach-imx/mach-imx6q.c
浏览文件 @ 8b3c8ba3
......@@ -388,10 +388,10 @@ static void __init imx6q_map_io(void)
static void __init imx6q_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}
......
arch/arm/mach-imx/mach-imx6sl.c
浏览文件 @ 8b3c8ba3
......@@ -61,10 +61,10 @@ static void __init imx6sl_init_machine(void)
static void __init imx6sl_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}
......
arch/arm/mach-imx/mach-imx6sx.c
浏览文件 @ 8b3c8ba3
......@@ -81,10 +81,10 @@ static void __init imx6sx_init_machine(void)
static void __init imx6sx_init_irq(void)
{
imx_gpc_check_dt();
imx_init_revision_from_anatop();
imx_init_l2cache();
imx_src_init();
imx_gpc_init();
irqchip_init();
}
......
arch/arm/mach-imx/pm-imx6.c
浏览文件 @ 8b3c8ba3
......@@ -310,10 +310,12 @@ int imx6q_set_lpm(enum mxc_cpu_pwr_mode mode)
* Low-Power mode.
* 3) Software should mask IRQ #32 right after CCM Low-Power mode
* is set (set bits 0-1 of CCM_CLPCR).
*
* Note that IRQ #32 is GIC SPI #0.
*/
imx_gpc_hwirq_unmask(32);
imx_gpc_hwirq_unmask(0);
writel_relaxed(val, ccm_base + CLPCR);
imx_gpc_hwirq_mask(32);
imx_gpc_hwirq_mask(0);
return 0;
}
......
arch/arm/mach-omap2/Kconfig
浏览文件 @ 8b3c8ba3
......@@ -81,6 +81,7 @@ config ARCH_OMAP2PLUS
select GENERIC_IRQ_CHIP
select MACH_OMAP_GENERIC
select MEMORY
select MFD_SYSCON
select OMAP_DM_TIMER
select OMAP_GPMC
select PINCTRL
......
arch/arm/mach-omap2/clock.c
浏览文件 @ 8b3c8ba3
此差异已折叠。
arch/arm/mach-omap2/clock.h
浏览文件 @ 8b3c8ba3
......@@ -271,10 +271,14 @@ extern const struct clksel_rate div_1_3_rates[];
extern const struct clksel_rate div_1_4_rates[];
extern const struct clksel_rate div31_1to31_rates[];
extern void __iomem *clk_memmaps[];
extern int omap2_clkops_enable_clkdm(struct clk_hw *hw);
extern void omap2_clkops_disable_clkdm(struct clk_hw *hw);
struct regmap;
int __init omap2_clk_provider_init(struct device_node *np, int index,
struct regmap *syscon, void __iomem *mem);
void __init omap2_clk_legacy_provider_init(int index, void __iomem *mem);
void __init ti_clk_init_features(void);
#endif
arch/arm/mach-omap2/cm.h
浏览文件 @ 8b3c8ba3
......@@ -70,6 +70,8 @@ int omap_cm_module_enable(u8 mode, u8 part, u16 inst, u16 clkctrl_offs);
int omap_cm_module_disable(u8 part, u16 inst, u16 clkctrl_offs);
extern int cm_register(struct cm_ll_data *cld);
extern int cm_unregister(struct cm_ll_data *cld);
int omap_cm_init(void);
int omap2_cm_base_init(void);
# endif
......
arch/arm/mach-omap2/cm2xxx.c
浏览文件 @ 8b3c8ba3
......@@ -393,7 +393,7 @@ static struct cm_ll_data omap2xxx_cm_ll_data = {
.wait_module_ready = &omap2xxx_cm_wait_module_ready,
};
int __init omap2xxx_cm_init(void)
int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data)
{
return cm_register(&omap2xxx_cm_ll_data);
}
......
arch/arm/mach-omap2/cm2xxx.h
浏览文件 @ 8b3c8ba3
......@@ -63,7 +63,7 @@ extern u32 omap2xxx_cm_get_core_pll_config(void);
extern void omap2xxx_cm_set_mod_dividers(u32 mpu, u32 dsp, u32 gfx, u32 core,
u32 mdm);
extern int __init omap2xxx_cm_init(void);
int __init omap2xxx_cm_init(const struct omap_prcm_init_data *data);
#endif
......
arch/arm/mach-omap2/cm33xx.c
浏览文件 @ 8b3c8ba3
......@@ -352,7 +352,7 @@ static struct cm_ll_data am33xx_cm_ll_data = {
.module_disable = &am33xx_cm_module_disable,
};
int __init am33xx_cm_init(void)
int __init am33xx_cm_init(const struct omap_prcm_init_data *data)
{
return cm_register(&am33xx_cm_ll_data);
}
......
arch/arm/mach-omap2/cm33xx.h
浏览文件 @ 8b3c8ba3
......@@ -19,6 +19,7 @@
#include "cm.h"
#include "cm-regbits-33xx.h"
#include "prcm-common.h"
/* CM base address */
#define AM33XX_CM_BASE 0x44e00000
......@@ -374,6 +375,6 @@
#ifndef __ASSEMBLER__
int am33xx_cm_init(void);
int am33xx_cm_init(const struct omap_prcm_init_data *data);
#endif /* ASSEMBLER */
#endif
arch/arm/mach-omap2/cm3xxx.c
浏览文件 @ 8b3c8ba3
......@@ -671,8 +671,9 @@ static struct cm_ll_data omap3xxx_cm_ll_data = {
.wait_module_ready = &omap3xxx_cm_wait_module_ready,
};
int __init omap3xxx_cm_init(void)
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data)
{
omap2_clk_legacy_provider_init(TI_CLKM_CM, cm_base + OMAP3430_IVA2_MOD);
return cm_register(&omap3xxx_cm_ll_data);
}
......
arch/arm/mach-omap2/cm3xxx.h
浏览文件 @ 8b3c8ba3
......@@ -72,7 +72,7 @@ extern void omap3_cm_save_context(void);
extern void omap3_cm_restore_context(void);
extern void omap3_cm_save_scratchpad_contents(u32 *ptr);
extern int __init omap3xxx_cm_init(void);
int __init omap3xxx_cm_init(const struct omap_prcm_init_data *data);
#endif
......
arch/arm/mach-omap2/cm44xx.h
浏览文件 @ 8b3c8ba3
......@@ -23,7 +23,6 @@
#define OMAP4_CM_CLKSTCTRL 0x0000
#define OMAP4_CM_STATICDEP 0x0004
void omap_cm_base_init(void);
int omap4_cm_init(void);
int omap4_cm_init(const struct omap_prcm_init_data *data);
#endif
arch/arm/mach-omap2/cm_common.c
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此差异已折叠。
arch/arm/mach-omap2/cminst44xx.c
浏览文件 @ 8b3c8ba3
......@@ -63,7 +63,7 @@ static void __iomem *_cm_bases[OMAP4_MAX_PRCM_PARTITIONS];
* Populates the base addresses of the _cm_bases
* array used for read/write of cm module registers.
*/
void omap_cm_base_init(void)
static void omap_cm_base_init(void)
{
_cm_bases[OMAP4430_PRM_PARTITION] = prm_base;
_cm_bases[OMAP4430_CM1_PARTITION] = cm_base;
......@@ -514,8 +514,10 @@ static struct cm_ll_data omap4xxx_cm_ll_data = {
.module_disable = &omap4_cminst_module_disable,
};
int __init omap4_cm_init(void)
int __init omap4_cm_init(const struct omap_prcm_init_data *data)
{
omap_cm_base_init();
return cm_register(&omap4xxx_cm_ll_data);
}
......
arch/arm/mach-omap2/control.c
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arch/arm/mach-omap2/control.h
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此差异已折叠。
arch/arm/mach-omap2/display.c
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此差异已折叠。
arch/arm/mach-omap2/id.c
浏览文件 @ 8b3c8ba3
......@@ -52,7 +52,10 @@ EXPORT_SYMBOL(omap_rev);
int omap_type(void)
{
u32 val = 0;
static u32 val = OMAP2_DEVICETYPE_MASK;
if (val < OMAP2_DEVICETYPE_MASK)
return val;
if (cpu_is_omap24xx()) {
val = omap_ctrl_readl(OMAP24XX_CONTROL_STATUS);
......
arch/arm/mach-omap2/io.c
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此差异已折叠。
arch/arm/mach-omap2/pm24xx.c
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此差异已折叠。
arch/arm/mach-omap2/pm34xx.c
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此差异已折叠。
arch/arm/mach-omap2/prcm-common.h
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此差异已折叠。
arch/arm/mach-omap2/prm.h
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此差异已折叠。
arch/arm/mach-omap2/prm2xxx.c
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此差异已折叠。
arch/arm/mach-omap2/prm2xxx.h
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此差异已折叠。
arch/arm/mach-omap2/prm33xx.c
浏览文件 @ 8b3c8ba3
......@@ -378,7 +378,7 @@ static struct prm_ll_data am33xx_prm_ll_data = {
.reset_system = am33xx_prm_global_warm_sw_reset,
};
int __init am33xx_prm_init(void)
int __init am33xx_prm_init(const struct omap_prcm_init_data *data)
{
return prm_register(&am33xx_prm_ll_data);
}
......
arch/arm/mach-omap2/prm33xx.h
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此差异已折叠。
arch/arm/mach-omap2/prm3xxx.c
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此差异已折叠。
arch/arm/mach-omap2/prm3xxx.h
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arch/arm/mach-omap2/prm44xx.c
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arch/arm/mach-omap2/prm44xx.h
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arch/arm/mach-omap2/prm44xx_54xx.h
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arch/arm/mach-omap2/prm54xx.h
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此差异已折叠。
arch/arm/mach-omap2/prm7xx.h
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此差异已折叠。
arch/arm/mach-omap2/prm_common.c
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arch/arm/mach-omap2/prminst44xx.c
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此差异已折叠。
arch/arm/mach-omap2/prminst44xx.h
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arch/arm/mach-omap2/vp.h
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此差异已折叠。
arch/arm/mach-omap2/vp3xxx_data.c
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此差异已折叠。
arch/arm/mach-omap2/vp44xx_data.c
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此差异已折叠。
include/linux/clk/ti.h
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此差异已折叠。
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