sh: Add support for SH7786 CPU subtype.

This adds preliminary support for the SH7786 CPU subtype.

While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.

More information on this particular CPU subtype is available at:

	http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/Signed-off-by: NKuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: NPaul Mundt <lethal@linux-sh.org>

arch/sh/Kconfig

@@ -356,6 +356,13 @@ config CPU_SUBTYPE_SH7785
 	select ARCH_SPARSEMEM_ENABLE
 	select SYS_SUPPORTS_NUMA
 
+config CPU_SUBTYPE_SH7786
+	bool "Support SH7786 processor"
+	select CPU_SH4A
+	select CPU_SHX2
+	select ARCH_SPARSEMEM_ENABLE
+	select SYS_SUPPORTS_NUMA
+
 config CPU_SUBTYPE_SHX3
 	bool "Support SH-X3 processor"
 	select CPU_SH4A

arch/sh/include/asm/processor.h

@@ -31,7 +31,7 @@ enum cpu_type {
 	CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
 
 	/* SH-4A types */
-	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+	CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
 	CPU_SH7723, CPU_SHX3,
 
 	/* SH4AL-DSP types */

arch/sh/include/cpu-sh4/cpu/freq.h

@@ -29,6 +29,10 @@
 #define FRQCR0			0xffc80000
 #define FRQCR1			0xffc80004
 #define FRQMR1			0xffc80014
+#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
+#define FRQCR0			0xffc40000
+#define FRQCR1			0xffc40004
+#define FRQMR1			0xffc40014
 #elif defined(CONFIG_CPU_SUBTYPE_SHX3)
 #define FRQCR			0xffc00014
 #else

arch/sh/include/cpu-sh4/cpu/sh7786.h

+/*
+ * SH7786 Pinmux
+ *
+ * Copyright (C) 2008, 2009  Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ *  Based on sh7785.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __CPU_SH7786_H__
+#define __CPU_SH7786_H__
+
+enum {
+	/* PA */
+	GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
+	GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
+
+	/* PB */
+	GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
+	GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
+
+	/* PC */
+	GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
+	GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
+
+	/* PD */
+	GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
+	GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
+
+	/* PE */
+	GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
+	GPIO_PE1, GPIO_PE0,
+
+	/* PF */
+	GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
+	GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
+
+	/* PG */
+	GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
+	GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
+
+	/* PH */
+	GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
+	GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+
+	/* PJ */
+	GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
+	GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
+
+	GPIO_FN_CDE,
+	GPIO_FN_ETH_MAGIC,
+	GPIO_FN_DISP,
+	GPIO_FN_ETH_LINK,
+	GPIO_FN_DR5,
+	GPIO_FN_ETH_TX_ER,
+	GPIO_FN_DR4,
+	GPIO_FN_ETH_TX_EN,
+	GPIO_FN_DR3,
+	GPIO_FN_ETH_TXD3,
+	GPIO_FN_DR2,
+	GPIO_FN_ETH_TXD2,
+	GPIO_FN_DR1,
+	GPIO_FN_ETH_TXD1,
+	GPIO_FN_DR0,
+	GPIO_FN_ETH_TXD0,
+	GPIO_FN_VSYNC,
+	GPIO_FN_HSPI_CLK,
+	GPIO_FN_ODDF,
+	GPIO_FN_HSPI_CS,
+	GPIO_FN_DG5,
+	GPIO_FN_ETH_MDIO,
+	GPIO_FN_DG4,
+	GPIO_FN_ETH_RX_CLK,
+	GPIO_FN_DG3,
+	GPIO_FN_ETH_MDC,
+	GPIO_FN_DG2,
+	GPIO_FN_ETH_COL,
+	GPIO_FN_DG1,
+	GPIO_FN_ETH_TX_CLK,
+	GPIO_FN_DG0,
+	GPIO_FN_ETH_CRS,
+	GPIO_FN_DCLKIN,
+	GPIO_FN_HSPI_RX,
+	GPIO_FN_HSYNC,
+	GPIO_FN_HSPI_TX,
+	GPIO_FN_DB5,
+	GPIO_FN_ETH_RXD3,
+	GPIO_FN_DB4,
+	GPIO_FN_ETH_RXD2,
+	GPIO_FN_DB3,
+	GPIO_FN_ETH_RXD1,
+	GPIO_FN_DB2,
+	GPIO_FN_ETH_RXD0,
+	GPIO_FN_DB1,
+	GPIO_FN_ETH_RX_DV,
+	GPIO_FN_DB0,
+	GPIO_FN_ETH_RX_ER,
+	GPIO_FN_DCLKOUT,
+	GPIO_FN_SCIF1_SLK,
+	GPIO_FN_SCIF1_RXD,
+	GPIO_FN_SCIF1_TXD,
+	GPIO_FN_DACK1,
+	GPIO_FN_BACK,
+	GPIO_FN_FALE,
+	GPIO_FN_DACK0,
+	GPIO_FN_FCLE,
+	GPIO_FN_DREQ1,
+	GPIO_FN_BREQ,
+	GPIO_FN_USB_OVC1,
+	GPIO_FN_DREQ0,
+	GPIO_FN_USB_OVC0,
+	GPIO_FN_USB_PENC1,
+	GPIO_FN_USB_PENC0,
+	GPIO_FN_HAC1_SDOUT,
+	GPIO_FN_SSI1_SDATA,
+	GPIO_FN_SDIF1CMD,
+	GPIO_FN_HAC1_SDIN,
+	GPIO_FN_SSI1_SCK,
+	GPIO_FN_SDIF1CD,
+	GPIO_FN_HAC1_SYNC,
+	GPIO_FN_SSI1_WS,
+	GPIO_FN_SDIF1WP,
+	GPIO_FN_HAC1_BITCLK,
+	GPIO_FN_SSI1_CLK,
+	GPIO_FN_SDIF1CLK,
+	GPIO_FN_HAC0_SDOUT,
+	GPIO_FN_SSI0_SDATA,
+	GPIO_FN_SDIF1D3,
+	GPIO_FN_HAC0_SDIN,
+	GPIO_FN_SSI0_SCK,
+	GPIO_FN_SDIF1D2,
+	GPIO_FN_HAC0_SYNC,
+	GPIO_FN_SSI0_WS,
+	GPIO_FN_SDIF1D1,
+	GPIO_FN_HAC0_BITCLK,
+	GPIO_FN_SSI0_CLK,
+	GPIO_FN_SDIF1D0,
+	GPIO_FN_SCIF3_SCK,
+	GPIO_FN_SSI2_SDATA,
+	GPIO_FN_SCIF3_RXD,
+	GPIO_FN_TCLK,
+	GPIO_FN_SSI2_SCK,
+	GPIO_FN_SCIF3_TXD,
+	GPIO_FN_HAC_RES,
+	GPIO_FN_SSI2_WS,
+	GPIO_FN_DACK3,
+	GPIO_FN_SDIF0CMD,
+	GPIO_FN_DACK2,
+	GPIO_FN_SDIF0CD,
+	GPIO_FN_DREQ3,
+	GPIO_FN_SDIF0WP,
+	GPIO_FN_SCIF0_CTS,
+	GPIO_FN_DREQ2,
+	GPIO_FN_SDIF0CLK,
+	GPIO_FN_SCIF0_RTS,
+	GPIO_FN_IRL7,
+	GPIO_FN_SDIF0D3,
+	GPIO_FN_SCIF0_SCK,
+	GPIO_FN_IRL6,
+	GPIO_FN_SDIF0D2,
+	GPIO_FN_SCIF0_RXD,
+	GPIO_FN_IRL5,
+	GPIO_FN_SDIF0D1,
+	GPIO_FN_SCIF0_TXD,
+	GPIO_FN_IRL4,
+	GPIO_FN_SDIF0D0,
+	GPIO_FN_SCIF5_SCK,
+	GPIO_FN_FRB,
+	GPIO_FN_SCIF5_RXD,
+	GPIO_FN_IOIS16,
+	GPIO_FN_SCIF5_TXD,
+	GPIO_FN_CE2B,
+	GPIO_FN_DRAK3,
+	GPIO_FN_CE2A,
+	GPIO_FN_SCIF4_SCK,
+	GPIO_FN_DRAK2,
+	GPIO_FN_SSI3_WS,
+	GPIO_FN_SCIF4_RXD,
+	GPIO_FN_DRAK1,
+	GPIO_FN_SSI3_SDATA,
+	GPIO_FN_FSTATUS,
+	GPIO_FN_SCIF4_TXD,
+	GPIO_FN_DRAK0,
+	GPIO_FN_SSI3_SCK,
+	GPIO_FN_FSE,
+};
+
+#endif /* __CPU_SH7786_H__ */

arch/sh/kernel/cpu/sh4/probe.c

@@ -129,6 +129,13 @@ int __init detect_cpu_and_cache_system(void)
 		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
 					  CPU_HAS_LLSC;
 		break;
+	case 0x4004:
+		boot_cpu_data.type = CPU_SH7786;
+		boot_cpu_data.icache.ways = 4;
+		boot_cpu_data.dcache.ways = 4;
+		boot_cpu_data.flags |= CPU_HAS_FPU | CPU_HAS_PERF_COUNTER |
+			CPU_HAS_LLSC;
+		break;
 	case 0x3008:
 		boot_cpu_data.icache.ways = 4;
 		boot_cpu_data.dcache.ways = 4;

arch/sh/kernel/cpu/sh4a/Makefile

@@ -7,6 +7,7 @@ obj-$(CONFIG_CPU_SUBTYPE_SH7763)	+= setup-sh7763.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7770)	+= setup-sh7770.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7780)	+= setup-sh7780.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7785)	+= setup-sh7785.o
+obj-$(CONFIG_CPU_SUBTYPE_SH7786)	+= setup-sh7786.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7343)	+= setup-sh7343.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7722)	+= setup-sh7722.o
 obj-$(CONFIG_CPU_SUBTYPE_SH7723)	+= setup-sh7723.o
@@ -21,6 +22,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SH7763)	:= clock-sh7763.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7770)	:= clock-sh7770.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7780)	:= clock-sh7780.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7785)	:= clock-sh7785.o
+clock-$(CONFIG_CPU_SUBTYPE_SH7786)	:= clock-sh7786.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7343)	:= clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7722)	:= clock-sh7722.o
 clock-$(CONFIG_CPU_SUBTYPE_SH7723)	:= clock-sh7722.o
@@ -31,6 +33,7 @@ clock-$(CONFIG_CPU_SUBTYPE_SHX3)	:= clock-shx3.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7722)	:= pinmux-sh7722.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7723)	:= pinmux-sh7723.o
 pinmux-$(CONFIG_CPU_SUBTYPE_SH7785)	:= pinmux-sh7785.o
+pinmux-$(CONFIG_CPU_SUBTYPE_SH7786)	:= pinmux-sh7786.o
 
 obj-y			+= $(clock-y)
 obj-$(CONFIG_SMP)	+= $(smp-y)

arch/sh/kernel/cpu/sh4a/clock-sh7786.c

+/*
+ * arch/sh/kernel/cpu/sh4a/clock-sh7786.c
+ *
+ * SH7786 support for the clock framework
+ *
+ * Copyright (C) 2008, 2009  Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7785
+ *  Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/init.h>
+#include <linux/kernel.h>
+#include <asm/clock.h>
+#include <asm/freq.h>
+#include <asm/io.h>
+
+static int ifc_divisors[] = { 1, 2, 4, 1 };
+static int sfc_divisors[] = { 1, 1, 4, 1 };
+static int bfc_divisors[] = { 1, 1, 1, 1, 1, 12, 16, 1,
+			     24, 32, 1, 1, 1, 1, 1, 1 };
+static int mfc_divisors[] = { 1, 1, 4, 1 };
+static int pfc_divisors[] = { 1, 1, 1, 1, 1, 1, 16, 1,
+			      24, 32, 1, 48, 1, 1, 1, 1 };
+
+static void master_clk_init(struct clk *clk)
+{
+	clk->rate *= pfc_divisors[ctrl_inl(FRQMR1) & 0x000f];
+}
+
+static struct clk_ops sh7786_master_clk_ops = {
+	.init		= master_clk_init,
+};
+
+static void module_clk_recalc(struct clk *clk)
+{
+	int idx = (ctrl_inl(FRQMR1) & 0x000f);
+	clk->rate = clk->parent->rate / pfc_divisors[idx];
+}
+
+static struct clk_ops sh7786_module_clk_ops = {
+	.recalc		= module_clk_recalc,
+};
+
+static void bus_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 16) & 0x000f);
+	clk->rate = clk->parent->rate / bfc_divisors[idx];
+}
+
+static struct clk_ops sh7786_bus_clk_ops = {
+	.recalc		= bus_clk_recalc,
+};
+
+static void cpu_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 28) & 0x0003);
+	clk->rate = clk->parent->rate / ifc_divisors[idx];
+}
+
+static struct clk_ops sh7786_cpu_clk_ops = {
+	.recalc		= cpu_clk_recalc,
+};
+
+static struct clk_ops *sh7786_clk_ops[] = {
+	&sh7786_master_clk_ops,
+	&sh7786_module_clk_ops,
+	&sh7786_bus_clk_ops,
+	&sh7786_cpu_clk_ops,
+};
+
+void __init arch_init_clk_ops(struct clk_ops **ops, int idx)
+{
+	if (idx < ARRAY_SIZE(sh7786_clk_ops))
+		*ops = sh7786_clk_ops[idx];
+}
+
+static void shyway_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 20) & 0x0003);
+	clk->rate = clk->parent->rate / sfc_divisors[idx];
+}
+
+static struct clk_ops sh7786_shyway_clk_ops = {
+	.recalc		= shyway_clk_recalc,
+};
+
+static struct clk sh7786_shyway_clk = {
+	.name		= "shyway_clk",
+	.flags		= CLK_ALWAYS_ENABLED,
+	.ops		= &sh7786_shyway_clk_ops,
+};
+
+static void ddr_clk_recalc(struct clk *clk)
+{
+	int idx = ((ctrl_inl(FRQMR1) >> 12) & 0x0003);
+	clk->rate = clk->parent->rate / mfc_divisors[idx];
+}
+
+static struct clk_ops sh7786_ddr_clk_ops = {
+	.recalc		= ddr_clk_recalc,
+};
+
+static struct clk sh7786_ddr_clk = {
+	.name		= "ddr_clk",
+	.flags		= CLK_ALWAYS_ENABLED,
+	.ops		= &sh7786_ddr_clk_ops,
+};
+
+/*
+ * Additional SH7786-specific on-chip clocks that aren't already part of the
+ * clock framework
+ */
+static struct clk *sh7786_onchip_clocks[] = {
+	&sh7786_shyway_clk,
+	&sh7786_ddr_clk,
+};
+
+static int __init sh7786_clk_init(void)
+{
+	struct clk *clk = clk_get(NULL, "master_clk");
+	int i;
+
+	for (i = 0; i < ARRAY_SIZE(sh7786_onchip_clocks); i++) {
+		struct clk *clkp = sh7786_onchip_clocks[i];
+
+		clkp->parent = clk;
+		clk_register(clkp);
+		clk_enable(clkp);
+	}
+
+	/*
+	 * Now that we have the rest of the clocks registered, we need to
+	 * force the parent clock to propagate so that these clocks will
+	 * automatically figure out their rate. We cheat by handing the
+	 * parent clock its current rate and forcing child propagation.
+	 */
+	clk_set_rate(clk, clk_get_rate(clk));
+
+	clk_put(clk);
+
+	return 0;
+}
+arch_initcall(sh7786_clk_init);

arch/sh/kernel/cpu/sh4a/setup-sh7786.c

+/*
+ * SH7786 Setup
+ *
+ * Copyright (C) 2009  Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on SH7785 Setup
+ *
+ *  Copyright (C) 2007  Paul Mundt
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <linux/platform_device.h>
+#include <linux/init.h>
+#include <linux/serial.h>
+#include <linux/serial_sci.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <asm/mmzone.h>
+
+static struct plat_sci_port sci_platform_data[] = {
+	{
+		.mapbase	= 0xffea0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 40, 41, 43, 42 },
+	},
+	/*
+	 * The rest of these all have multiplexed IRQs
+	 */
+	{
+		.mapbase	= 0xffeb0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 44, 44, 44, 44 },
+	}, {
+		.mapbase	= 0xffec0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 50, 50, 50, 50 },
+	}, {
+		.mapbase	= 0xffed0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 51, 51, 51, 51 },
+	}, {
+		.mapbase	= 0xffee0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 52, 52, 52, 52 },
+	}, {
+		.mapbase	= 0xffef0000,
+		.flags		= UPF_BOOT_AUTOCONF,
+		.type		= PORT_SCIF,
+		.irqs		= { 53, 53, 53, 53 },
+	}, {
+		.flags = 0,
+	}
+};
+
+static struct platform_device sci_device = {
+	.name		= "sh-sci",
+	.id		= -1,
+	.dev		= {
+		.platform_data	= sci_platform_data,
+	},
+};
+
+static struct platform_device *sh7786_devices[] __initdata = {
+	&sci_device,
+};
+
+static int __init sh7786_devices_setup(void)
+{
+	return platform_add_devices(sh7786_devices,
+				    ARRAY_SIZE(sh7786_devices));
+}
+device_initcall(sh7786_devices_setup);
+
+enum {
+	UNUSED = 0,
+
+	/* interrupt sources */
+
+	IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+	IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+	IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+	IRL0_HHLL, IRL0_HHLH, IRL0_HHHL,
+
+	IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+	IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+	IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+	IRL4_HHLL, IRL4_HHLH, IRL4_HHHL,
+
+	IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7,
+	WDT,
+	TMU0_0, TMU0_1, TMU0_2, TMU0_3,
+	TMU1_0, TMU1_1, TMU1_2,
+	DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
+	HUDI1, HUDI0,
+	DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
+	HPB_0, HPB_1, HPB_2,
+	SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
+	SCIF1,
+	TMU2, TMU3,
+	SCIF2, SCIF3, SCIF4, SCIF5,
+	Eth_0, Eth_1,
+	PCIeC0_0, PCIeC0_1, PCIeC0_2,
+	PCIeC1_0, PCIeC1_1, PCIeC1_2,
+	USB,
+	I2C0, I2C1,
+	DU,
+	SSI0, SSI1, SSI2, SSI3,
+	PCIeC2_0, PCIeC2_1, PCIeC2_2,
+	HAC0, HAC1,
+	FLCTL,
+	HSPI,
+	GPIO0, GPIO1,
+	Thermal,
+	INTC0, INTC1, INTC2, INTC3, INTC4, INTC5, INTC6, INTC7,
+
+	/* interrupt groups */
+};
+
+static struct intc_vect vectors[] __initdata = {
+	INTC_VECT(WDT, 0x3e0),
+	INTC_VECT(TMU0_0, 0x400), INTC_VECT(TMU0_1, 0x420),
+	INTC_VECT(TMU0_2, 0x440), INTC_VECT(TMU0_3, 0x460),
+	INTC_VECT(TMU1_0, 0x480), INTC_VECT(TMU1_1, 0x4a0),
+	INTC_VECT(TMU1_2, 0x4c0),
+	INTC_VECT(DMAC0_0, 0x500), INTC_VECT(DMAC0_1, 0x520),
+	INTC_VECT(DMAC0_2, 0x540), INTC_VECT(DMAC0_3, 0x560),
+	INTC_VECT(DMAC0_4, 0x580), INTC_VECT(DMAC0_5, 0x5a0),
+	INTC_VECT(DMAC0_6, 0x5c0),
+	INTC_VECT(HUDI1, 0x5e0), INTC_VECT(HUDI0, 0x600),
+	INTC_VECT(DMAC1_0, 0x620), INTC_VECT(DMAC1_1, 0x640),
+	INTC_VECT(DMAC1_2, 0x660), INTC_VECT(DMAC1_3, 0x680),
+	INTC_VECT(HPB_0, 0x6a0), INTC_VECT(HPB_1, 0x6c0),
+	INTC_VECT(HPB_2, 0x6e0),
+	INTC_VECT(SCIF0_0, 0x700), INTC_VECT(SCIF0_1, 0x720),
+	INTC_VECT(SCIF0_2, 0x740), INTC_VECT(SCIF0_3, 0x760),
+	INTC_VECT(SCIF1, 0x780),
+	INTC_VECT(TMU2, 0x7a0), INTC_VECT(TMU3, 0x7c0),
+	INTC_VECT(SCIF2, 0x840), INTC_VECT(SCIF3, 0x860),
+	INTC_VECT(SCIF4, 0x880), INTC_VECT(SCIF5, 0x8a0),
+	INTC_VECT(Eth_0, 0x8c0), INTC_VECT(Eth_1, 0x8e0),
+	INTC_VECT(PCIeC0_0, 0xae0), INTC_VECT(PCIeC0_1, 0xb00),
+	INTC_VECT(PCIeC0_2, 0xb20),
+	INTC_VECT(PCIeC1_0, 0xb40), INTC_VECT(PCIeC1_1, 0xb60),
+	INTC_VECT(PCIeC1_2, 0xb80),
+	INTC_VECT(USB, 0xba0),
+	INTC_VECT(I2C0, 0xcc0), INTC_VECT(I2C1, 0xce0),
+	INTC_VECT(DU, 0xd00),
+	INTC_VECT(SSI0, 0xd20), INTC_VECT(SSI1, 0xd40),
+	INTC_VECT(SSI2, 0xd60), INTC_VECT(SSI3, 0xd80),
+	INTC_VECT(PCIeC2_0, 0xda0), INTC_VECT(PCIeC2_1, 0xdc0),
+	INTC_VECT(PCIeC2_2, 0xde0),
+	INTC_VECT(HAC0, 0xe00), INTC_VECT(HAC1, 0xe20),
+	INTC_VECT(FLCTL, 0xe40),
+	INTC_VECT(HSPI, 0xe80),
+	INTC_VECT(GPIO0, 0xea0), INTC_VECT(GPIO1, 0xec0),
+	INTC_VECT(Thermal, 0xee0),
+};
+
+/* FIXME: Main CPU support only now */
+#if 1 /* Main CPU */
+#define CnINTMSK0	0xfe410030
+#define CnINTMSK1	0xfe410040
+#define CnINTMSKCLR0	0xfe410050
+#define CnINTMSKCLR1	0xfe410060
+#define CnINT2MSKR0	0xfe410a20
+#define CnINT2MSKR1	0xfe410a24
+#define CnINT2MSKR2	0xfe410a28
+#define CnINT2MSKR3	0xfe410a2c
+#define CnINT2MSKCR0	0xfe410a30
+#define CnINT2MSKCR1	0xfe410a34
+#define CnINT2MSKCR2	0xfe410a38
+#define CnINT2MSKCR3	0xfe410a3c
+#else /* Sub CPU */
+#define CnINTMSK0	0xfe410034
+#define CnINTMSK1	0xfe410044
+#define CnINTMSKCLR0	0xfe410054
+#define CnINTMSKCLR1	0xfe410064
+#define CnINT2MSKR0	0xfe410b20
+#define CnINT2MSKR1	0xfe410b24
+#define CnINT2MSKR2	0xfe410b28
+#define CnINT2MSKR3	0xfe410b2c
+#define CnINT2MSKCR0	0xfe410b30
+#define CnINT2MSKCR1	0xfe410b34
+#define CnINT2MSKCR2	0xfe410b38
+#define CnINT2MSKCR3	0xfe410b3c
+#endif
+
+#define INTMSK2		0xfe410068
+#define INTMSKCLR2	0xfe41006c
+
+static struct intc_mask_reg mask_registers[] __initdata = {
+	{ CnINTMSK0, CnINTMSKCLR0, 32,
+	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+	{ INTMSK2, INTMSKCLR2, 32,
+	  { IRL0_LLLL, IRL0_LLLH, IRL0_LLHL, IRL0_LLHH,
+	    IRL0_LHLL, IRL0_LHLH, IRL0_LHHL, IRL0_LHHH,
+	    IRL0_HLLL, IRL0_HLLH, IRL0_HLHL, IRL0_HLHH,
+	    IRL0_HHLL, IRL0_HHLH, IRL0_HHHL, 0,
+	    IRL4_LLLL, IRL4_LLLH, IRL4_LLHL, IRL4_LLHH,
+	    IRL4_LHLL, IRL4_LHLH, IRL4_LHHL, IRL4_LHHH,
+	    IRL4_HLLL, IRL4_HLLH, IRL4_HLHL, IRL4_HLHH,
+	    IRL4_HHLL, IRL4_HHLH, IRL4_HHHL, 0, } },
+	{ CnINT2MSKR0, CnINT2MSKCR0 , 32,
+	  { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, WDT } },
+	{ CnINT2MSKR1, CnINT2MSKCR1, 32,
+	  { TMU0_0, TMU0_1, TMU0_2, TMU0_3, TMU1_0, TMU1_1, TMU1_2, 0,
+	    DMAC0_0, DMAC0_1, DMAC0_2, DMAC0_3, DMAC0_4, DMAC0_5, DMAC0_6,
+	    HUDI1, HUDI0,
+	    DMAC1_0, DMAC1_1, DMAC1_2, DMAC1_3,
+	    HPB_0, HPB_1, HPB_2,
+	    SCIF0_0, SCIF0_1, SCIF0_2, SCIF0_3,
+	    SCIF1,
+	    TMU2, TMU3, 0, } },
+	{ CnINT2MSKR2, CnINT2MSKCR2, 32,
+	  { 0, 0, SCIF2, SCIF3, SCIF4, SCIF5,
+	    Eth_0, Eth_1,
+	    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+	    PCIeC0_0, PCIeC0_1, PCIeC0_2,
+	    PCIeC1_0, PCIeC1_1, PCIeC1_2,
+	    USB, 0, 0 } },
+	{ CnINT2MSKR3, CnINT2MSKCR3, 32,
+	  { 0, 0, 0, 0, 0, 0,
+	    I2C0, I2C1,
+	    DU, SSI0, SSI1, SSI2, SSI3,
+	    PCIeC2_0, PCIeC2_1, PCIeC2_2,
+	    HAC0, HAC1,
+	    FLCTL, 0,
+	    HSPI, GPIO0, GPIO1, Thermal,
+	    0, 0, 0, 0, 0, 0, 0, 0 } },
+};
+
+static struct intc_prio_reg prio_registers[] __initdata = {
+	{ 0xfe410010, 0, 32, 4, /* INTPRI */   { IRQ0, IRQ1, IRQ2, IRQ3,
+						 IRQ4, IRQ5, IRQ6, IRQ7 } },
+	{ 0xfe410800, 0, 32, 8, /* INT2PRI0 */ { 0, 0, 0, WDT } },
+	{ 0xfe410804, 0, 32, 8, /* INT2PRI1 */ { TMU0_0, TMU0_1,
+						 TMU0_2, TMU0_3 } },
+	{ 0xfe410808, 0, 32, 8, /* INT2PRI2 */ { TMU1_0, TMU1_1,
+						 TMU1_2, 0 } },
+	{ 0xfe41080c, 0, 32, 8, /* INT2PRI3 */ { DMAC0_0, DMAC0_1,
+						 DMAC0_2, DMAC0_3 } },
+	{ 0xfe410810, 0, 32, 8, /* INT2PRI4 */ { DMAC0_4, DMAC0_5,
+						 DMAC0_6, HUDI1 } },
+	{ 0xfe410814, 0, 32, 8, /* INT2PRI5 */ { HUDI0, DMAC1_0,
+						 DMAC1_1, DMAC1_2 } },
+	{ 0xfe410818, 0, 32, 8, /* INT2PRI6 */ { DMAC1_3, HPB_0,
+						 HPB_1, HPB_2 } },
+	{ 0xfe41081c, 0, 32, 8, /* INT2PRI7 */ { SCIF0_0, SCIF0_1,
+						 SCIF0_2, SCIF0_3 } },
+	{ 0xfe410820, 0, 32, 8, /* INT2PRI8 */ { SCIF1, TMU2, TMU3, 0 } },
+	{ 0xfe410824, 0, 32, 8, /* INT2PRI9 */ { 0, 0, SCIF2, SCIF3 } },
+	{ 0xfe410828, 0, 32, 8, /* INT2PRI10 */ { SCIF4, SCIF5,
+						  Eth_0, Eth_1 } },
+	{ 0xfe41082c, 0, 32, 8, /* INT2PRI11 */ { 0, 0, 0, 0 } },
+	{ 0xfe410830, 0, 32, 8, /* INT2PRI12 */ { 0, 0, 0, 0 } },
+	{ 0xfe410834, 0, 32, 8, /* INT2PRI13 */ { 0, 0, 0, 0 } },
+	{ 0xfe410838, 0, 32, 8, /* INT2PRI14 */ { 0, 0, 0, PCIeC0_0 } },
+	{ 0xfe41083c, 0, 32, 8, /* INT2PRI15 */ { PCIeC0_1, PCIeC0_2,
+						  PCIeC1_0, PCIeC1_1 } },
+	{ 0xfe410840, 0, 32, 8, /* INT2PRI16 */ { PCIeC1_2, USB, 0, 0 } },
+	{ 0xfe410844, 0, 32, 8, /* INT2PRI17 */ { 0, 0, 0, 0 } },
+	{ 0xfe410848, 0, 32, 8, /* INT2PRI18 */ { 0, 0, I2C0, I2C1 } },
+	{ 0xfe41084c, 0, 32, 8, /* INT2PRI19 */ { DU, SSI0, SSI1, SSI2 } },
+	{ 0xfe410850, 0, 32, 8, /* INT2PRI20 */ { SSI3, PCIeC2_0,
+						  PCIeC2_1, PCIeC2_2 } },
+	{ 0xfe410854, 0, 32, 8, /* INT2PRI21 */ { HAC0, HAC1, FLCTL, 0 } },
+	{ 0xfe410858, 0, 32, 8, /* INT2PRI22 */ { HSPI, GPIO0,
+						  GPIO1, Thermal } },
+	{ 0xfe41085c, 0, 32, 8, /* INT2PRI23 */ { 0, 0, 0, 0 } },
+	{ 0xfe410860, 0, 32, 8, /* INT2PRI24 */ { 0, 0, 0, 0 } },
+};
+
+static DECLARE_INTC_DESC(intc_desc, "sh7786", vectors, NULL,
+			 mask_registers, prio_registers, NULL);
+
+/* Support for external interrupt pins in IRQ mode */
+
+static struct intc_vect vectors_irq0123[] __initdata = {
+	INTC_VECT(IRQ0, 0x200), INTC_VECT(IRQ1, 0x240),
+	INTC_VECT(IRQ2, 0x280), INTC_VECT(IRQ3, 0x2c0),
+};
+
+static struct intc_vect vectors_irq4567[] __initdata = {
+	INTC_VECT(IRQ4, 0x300), INTC_VECT(IRQ5, 0x340),
+	INTC_VECT(IRQ6, 0x380), INTC_VECT(IRQ7, 0x3c0),
+};
+
+static struct intc_sense_reg sense_registers[] __initdata = {
+	{ 0xfe41001c, 32, 2, /* ICR1 */   { IRQ0, IRQ1, IRQ2, IRQ3,
+					    IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static struct intc_mask_reg ack_registers[] __initdata = {
+	{ 0xfe410024, 0, 32, /* INTREQ */
+	  { IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, IRQ5, IRQ6, IRQ7 } },
+};
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq0123, "sh7786-irq0123",
+			     vectors_irq0123, NULL, mask_registers,
+			     prio_registers, sense_registers, ack_registers);
+
+static DECLARE_INTC_DESC_ACK(intc_desc_irq4567, "sh7786-irq4567",
+			     vectors_irq4567, NULL, mask_registers,
+			     prio_registers, sense_registers, ack_registers);
+
+/* External interrupt pins in IRL mode */
+
+static struct intc_vect vectors_irl0123[] __initdata = {
+	INTC_VECT(IRL0_LLLL, 0x200), INTC_VECT(IRL0_LLLH, 0x220),
+	INTC_VECT(IRL0_LLHL, 0x240), INTC_VECT(IRL0_LLHH, 0x260),
+	INTC_VECT(IRL0_LHLL, 0x280), INTC_VECT(IRL0_LHLH, 0x2a0),
+	INTC_VECT(IRL0_LHHL, 0x2c0), INTC_VECT(IRL0_LHHH, 0x2e0),
+	INTC_VECT(IRL0_HLLL, 0x300), INTC_VECT(IRL0_HLLH, 0x320),
+	INTC_VECT(IRL0_HLHL, 0x340), INTC_VECT(IRL0_HLHH, 0x360),
+	INTC_VECT(IRL0_HHLL, 0x380), INTC_VECT(IRL0_HHLH, 0x3a0),
+	INTC_VECT(IRL0_HHHL, 0x3c0),
+};
+
+static struct intc_vect vectors_irl4567[] __initdata = {
+	INTC_VECT(IRL4_LLLL, 0x900), INTC_VECT(IRL4_LLLH, 0x920),
+	INTC_VECT(IRL4_LLHL, 0x940), INTC_VECT(IRL4_LLHH, 0x960),
+	INTC_VECT(IRL4_LHLL, 0x980), INTC_VECT(IRL4_LHLH, 0x9a0),
+	INTC_VECT(IRL4_LHHL, 0x9c0), INTC_VECT(IRL4_LHHH, 0x9e0),
+	INTC_VECT(IRL4_HLLL, 0xa00), INTC_VECT(IRL4_HLLH, 0xa20),
+	INTC_VECT(IRL4_HLHL, 0xa40), INTC_VECT(IRL4_HLHH, 0xa60),
+	INTC_VECT(IRL4_HHLL, 0xa80), INTC_VECT(IRL4_HHLH, 0xaa0),
+	INTC_VECT(IRL4_HHHL, 0xac0),
+};
+
+static DECLARE_INTC_DESC(intc_desc_irl0123, "sh7786-irl0123", vectors_irl0123,
+			 NULL, mask_registers, NULL, NULL);
+
+static DECLARE_INTC_DESC(intc_desc_irl4567, "sh7786-irl4567", vectors_irl4567,
+			 NULL, mask_registers, NULL, NULL);
+
+#define INTC_ICR0	0xfe410000
+#define INTC_INTMSK0	CnINTMSK0
+#define INTC_INTMSK1	CnINTMSK1
+#define INTC_INTMSK2	INTMSK2
+#define INTC_INTMSKCLR1	CnINTMSKCLR1
+#define INTC_INTMSKCLR2	INTMSKCLR2
+
+void __init plat_irq_setup(void)
+{
+	/* disable IRQ3-0 + IRQ7-4 */
+	ctrl_outl(0xff000000, INTC_INTMSK0);
+
+	/* disable IRL3-0 + IRL7-4 */
+	ctrl_outl(0xc0000000, INTC_INTMSK1);
+	ctrl_outl(0xfffefffe, INTC_INTMSK2);
+
+	/* select IRL mode for IRL3-0 + IRL7-4 */
+	ctrl_outl(ctrl_inl(INTC_ICR0) & ~0x00c00000, INTC_ICR0);
+
+	register_intc_controller(&intc_desc);
+}
+
+void __init plat_irq_setup_pins(int mode)
+{
+	switch (mode) {
+	case IRQ_MODE_IRQ7654:
+		/* select IRQ mode for IRL7-4 */
+		ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00400000, INTC_ICR0);
+		register_intc_controller(&intc_desc_irq4567);
+		break;
+	case IRQ_MODE_IRQ3210:
+		/* select IRQ mode for IRL3-0 */
+		ctrl_outl(ctrl_inl(INTC_ICR0) | 0x00800000, INTC_ICR0);
+		register_intc_controller(&intc_desc_irq0123);
+		break;
+	case IRQ_MODE_IRL7654:
+		/* enable IRL7-4 but don't provide any masking */
+		ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+		ctrl_outl(0x0000fffe, INTC_INTMSKCLR2);
+		break;
+	case IRQ_MODE_IRL3210:
+		/* enable IRL0-3 but don't provide any masking */
+		ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+		ctrl_outl(0xfffe0000, INTC_INTMSKCLR2);
+		break;
+	case IRQ_MODE_IRL7654_MASK:
+		/* enable IRL7-4 and mask using cpu intc controller */
+		ctrl_outl(0x40000000, INTC_INTMSKCLR1);
+		register_intc_controller(&intc_desc_irl4567);
+		break;
+	case IRQ_MODE_IRL3210_MASK:
+		/* enable IRL0-3 and mask using cpu intc controller */
+		ctrl_outl(0x80000000, INTC_INTMSKCLR1);
+		register_intc_controller(&intc_desc_irl0123);
+		break;
+	default:
+		BUG();
+	}
+}
+
+void __init plat_mem_setup(void)
+{
+}

arch/sh/kernel/setup.c

@@ -432,6 +432,7 @@ static const char *cpu_name[] = {
 	[CPU_SH7763]	= "SH7763",	[CPU_SH7770]	= "SH7770",
 	[CPU_SH7780]	= "SH7780",	[CPU_SH7781]	= "SH7781",
 	[CPU_SH7343]	= "SH7343",	[CPU_SH7785]	= "SH7785",
+	[CPU_SH7786]	= "SH7786",
 	[CPU_SH7722]	= "SH7722",	[CPU_SHX3]	= "SH-X3",
 	[CPU_SH5_101]	= "SH5-101",	[CPU_SH5_103]	= "SH5-103",
 	[CPU_MXG]	= "MX-G",	[CPU_SH7723]	= "SH7723",

arch/sh/kernel/timers/timer-tmu.c

@@ -244,6 +244,7 @@ static int tmu_timer_init(void)
     !defined(CONFIG_CPU_SUBTYPE_SH7721) && \
     !defined(CONFIG_CPU_SUBTYPE_SH7760) && \
     !defined(CONFIG_CPU_SUBTYPE_SH7785) && \
+    !defined(CONFIG_CPU_SUBTYPE_SH7786) && \
     !defined(CONFIG_CPU_SUBTYPE_SHX3)
 	ctrl_outb(TMU_TOCR_INIT, TMU_TOCR);
 #endif

arch/sh/oprofile/common.c

@@ -107,6 +107,7 @@ int __init oprofile_arch_init(struct oprofile_operations *ops)
 	case CPU_SH7780:
 	case CPU_SH7781:
 	case CPU_SH7785:
+	case CPU_SH7786:
 	case CPU_SH7723:
 	case CPU_SHX3:
 		lmodel = &op_model_sh4a_ops;

drivers/serial/sh-sci.c

@@ -263,6 +263,7 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7763) || \
       defined(CONFIG_CPU_SUBTYPE_SH7780) || \
       defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7786) || \
       defined(CONFIG_CPU_SUBTYPE_SHX3)
 static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
 {
@@ -284,7 +285,8 @@ static inline void sci_init_pins(struct uart_port *port, unsigned int cflag)
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7785)
+    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7786)
 static inline int scif_txroom(struct uart_port *port)
 {
 	return SCIF_TXROOM_MAX - (sci_in(port, SCTFDR) & 0xff);

drivers/serial/sh-sci.h

@@ -126,7 +126,8 @@
 # define SCSPTR1	0xffe10024	/* 16 bit SCIF */
 # define SCIF_ORER	0x0001		/* Overrun error bit */
 # define SCSCR_INIT(port)	0x3a	/* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */
-#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7786)
 # define SCSPTR0	0xffea0024	/* 16 bit SCIF */
 # define SCSPTR1	0xffeb0024	/* 16 bit SCIF */
 # define SCSPTR2	0xffec0024	/* 16 bit SCIF */
@@ -182,6 +183,7 @@
     defined(CONFIG_CPU_SUBTYPE_SH7763)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7780)  || \
     defined(CONFIG_CPU_SUBTYPE_SH7785)  || \
+    defined(CONFIG_CPU_SUBTYPE_SH7786)  || \
     defined(CONFIG_CPU_SUBTYPE_SHX3)
 #define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */
 #else
@@ -413,7 +415,8 @@ SCIx_FNS(SCxRDR, 0x0a,  8, 0x14,  8, 0x0A,  8, 0x14,  8, 0x05,  8)
 SCIF_FNS(SCFCR,                      0x0c,  8, 0x18, 16)
 #if defined(CONFIG_CPU_SUBTYPE_SH7760) || \
     defined(CONFIG_CPU_SUBTYPE_SH7780) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7785)
+    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7786)
 SCIF_FNS(SCFDR,			     0x0e, 16, 0x1C, 16)
 SCIF_FNS(SCTFDR,		     0x0e, 16, 0x1C, 16)
 SCIF_FNS(SCRFDR,		     0x0e, 16, 0x20, 16)
@@ -644,7 +647,8 @@ static inline int sci_rxd_in(struct uart_port *port)
 		return ctrl_inw(SCSPTR1) & 0x0001 ? 1 : 0; /* SCIF */
 	return 1;
 }
-#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+      defined(CONFIG_CPU_SUBTYPE_SH7786)
 static inline int sci_rxd_in(struct uart_port *port)
 {
 	if (port->mapbase == 0xffea0000)
@@ -746,7 +750,8 @@ static inline int sci_rxd_in(struct uart_port *port)
  */
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7780) || \
-    defined(CONFIG_CPU_SUBTYPE_SH7785)
+    defined(CONFIG_CPU_SUBTYPE_SH7785) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7786)
 #define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1)
 #elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \
       defined(CONFIG_CPU_SUBTYPE_SH7720) || \