提交 55b89540 编写于 作者: M Matthew Leach 提交者: Catalin Marinas

arm64: compat: correct register concatenation for syscall wrappers

The arm64 port contains wrappers for arm32 syscalls that pass 64-bit
values. These wrappers concatenate the two registers to hold a 64-bit
value in a single X register. On BE, however, the lower and higher
words are swapped.

Create a new assembler macro, regs_to_64, that when on BE systems
swaps the registers in the orr instruction.
Acked-by: NWill Deacon <will.deacon@arm.com>
Signed-off-by: NMatthew Leach <matthew.leach@arm.com>
Signed-off-by: NCatalin Marinas <catalin.marinas@arm.com>
上级 a795a38e
...@@ -115,3 +115,15 @@ lr .req x30 // link register ...@@ -115,3 +115,15 @@ lr .req x30 // link register
.align 7 .align 7
b \label b \label
.endm .endm
/*
* Define a macro that constructs a 64-bit value by concatenating two
* 32-bit registers. Note that on big endian systems the order of the
* registers is swapped.
*/
#ifndef CONFIG_CPU_BIG_ENDIAN
.macro regs_to_64, rd, lbits, hbits
#else
.macro regs_to_64, rd, hbits, lbits
#endif
orr \rd, \lbits, \hbits, lsl #32
.endm
...@@ -59,48 +59,48 @@ ENDPROC(compat_sys_fstatfs64_wrapper) ...@@ -59,48 +59,48 @@ ENDPROC(compat_sys_fstatfs64_wrapper)
* extension. * extension.
*/ */
compat_sys_pread64_wrapper: compat_sys_pread64_wrapper:
orr x3, x4, x5, lsl #32 regs_to_64 x3, x4, x5
b sys_pread64 b sys_pread64
ENDPROC(compat_sys_pread64_wrapper) ENDPROC(compat_sys_pread64_wrapper)
compat_sys_pwrite64_wrapper: compat_sys_pwrite64_wrapper:
orr x3, x4, x5, lsl #32 regs_to_64 x3, x4, x5
b sys_pwrite64 b sys_pwrite64
ENDPROC(compat_sys_pwrite64_wrapper) ENDPROC(compat_sys_pwrite64_wrapper)
compat_sys_truncate64_wrapper: compat_sys_truncate64_wrapper:
orr x1, x2, x3, lsl #32 regs_to_64 x1, x2, x3
b sys_truncate b sys_truncate
ENDPROC(compat_sys_truncate64_wrapper) ENDPROC(compat_sys_truncate64_wrapper)
compat_sys_ftruncate64_wrapper: compat_sys_ftruncate64_wrapper:
orr x1, x2, x3, lsl #32 regs_to_64 x1, x2, x3
b sys_ftruncate b sys_ftruncate
ENDPROC(compat_sys_ftruncate64_wrapper) ENDPROC(compat_sys_ftruncate64_wrapper)
compat_sys_readahead_wrapper: compat_sys_readahead_wrapper:
orr x1, x2, x3, lsl #32 regs_to_64 x1, x2, x3
mov w2, w4 mov w2, w4
b sys_readahead b sys_readahead
ENDPROC(compat_sys_readahead_wrapper) ENDPROC(compat_sys_readahead_wrapper)
compat_sys_fadvise64_64_wrapper: compat_sys_fadvise64_64_wrapper:
mov w6, w1 mov w6, w1
orr x1, x2, x3, lsl #32 regs_to_64 x1, x2, x3
orr x2, x4, x5, lsl #32 regs_to_64 x2, x4, x5
mov w3, w6 mov w3, w6
b sys_fadvise64_64 b sys_fadvise64_64
ENDPROC(compat_sys_fadvise64_64_wrapper) ENDPROC(compat_sys_fadvise64_64_wrapper)
compat_sys_sync_file_range2_wrapper: compat_sys_sync_file_range2_wrapper:
orr x2, x2, x3, lsl #32 regs_to_64 x2, x2, x3
orr x3, x4, x5, lsl #32 regs_to_64 x3, x4, x5
b sys_sync_file_range2 b sys_sync_file_range2
ENDPROC(compat_sys_sync_file_range2_wrapper) ENDPROC(compat_sys_sync_file_range2_wrapper)
compat_sys_fallocate_wrapper: compat_sys_fallocate_wrapper:
orr x2, x2, x3, lsl #32 regs_to_64 x2, x2, x3
orr x3, x4, x5, lsl #32 regs_to_64 x3, x4, x5
b sys_fallocate b sys_fallocate
ENDPROC(compat_sys_fallocate_wrapper) ENDPROC(compat_sys_fallocate_wrapper)
......
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