提交 17ed9e31 编写于 作者: A Aneesh Kumar K.V 提交者: Michael Ellerman

powerpc/booke: Move nohash headers

Move the booke related headers below booke/32 or booke/64
Acked-by: NScott Wood <scottwood@freescale.com>
Signed-off-by: NAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: NMichael Ellerman <mpe@ellerman.id.au>
上级 1ca72129
#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
#define _ASM_POWERPC_PGTABLE_PPC32_H
#ifndef _ASM_POWERPC_NOHASH_32_PGTABLE_H
#define _ASM_POWERPC_NOHASH_32_PGTABLE_H
#include <asm-generic/pgtable-nopmd.h>
......@@ -106,15 +106,15 @@ extern int icache_44x_need_flush;
*/
#if defined(CONFIG_40x)
#include <asm/pte-40x.h>
#include <asm/nohash/32/pte-40x.h>
#elif defined(CONFIG_44x)
#include <asm/pte-44x.h>
#include <asm/nohash/32/pte-44x.h>
#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
#include <asm/pte-book3e.h>
#include <asm/nohash/pte-book3e.h>
#elif defined(CONFIG_FSL_BOOKE)
#include <asm/pte-fsl-booke.h>
#include <asm/nohash/32/pte-fsl-booke.h>
#elif defined(CONFIG_8xx)
#include <asm/pte-8xx.h>
#include <asm/nohash/32/pte-8xx.h>
#endif
/* And here we include common definitions */
......@@ -340,4 +340,4 @@ extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
#endif /* !__ASSEMBLY__ */
#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
#endif /* __ASM_POWERPC_NOHASH_32_PGTABLE_H */
#ifndef _ASM_POWERPC_PTE_40x_H
#define _ASM_POWERPC_PTE_40x_H
#ifndef _ASM_POWERPC_NOHASH_32_PTE_40x_H
#define _ASM_POWERPC_NOHASH_32_PTE_40x_H
#ifdef __KERNEL__
/*
......@@ -61,4 +61,4 @@
#define PTE_ATOMIC_UPDATES 1
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PTE_40x_H */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_40x_H */
#ifndef _ASM_POWERPC_PTE_44x_H
#define _ASM_POWERPC_PTE_44x_H
#ifndef _ASM_POWERPC_NOHASH_32_PTE_44x_H
#define _ASM_POWERPC_NOHASH_32_PTE_44x_H
#ifdef __KERNEL__
/*
......@@ -94,4 +94,4 @@
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PTE_44x_H */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_44x_H */
#ifndef _ASM_POWERPC_PTE_8xx_H
#define _ASM_POWERPC_PTE_8xx_H
#ifndef _ASM_POWERPC_NOHASH_32_PTE_8xx_H
#define _ASM_POWERPC_NOHASH_32_PTE_8xx_H
#ifdef __KERNEL__
/*
......@@ -62,4 +62,4 @@
_PAGE_HWWRITE | _PAGE_EXEC)
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PTE_8xx_H */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_8xx_H */
#ifndef _ASM_POWERPC_PTE_FSL_BOOKE_H
#define _ASM_POWERPC_PTE_FSL_BOOKE_H
#ifndef _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
#define _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H
#ifdef __KERNEL__
/* PTE bit definitions for Freescale BookE SW loaded TLB MMU based
......@@ -37,4 +37,4 @@
#define PTE_WIMGE_SHIFT (6)
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
#endif /* _ASM_POWERPC_NOHASH_32_PTE_FSL_BOOKE_H */
#ifndef _ASM_POWERPC_PGTABLE_PPC64_4K_H
#define _ASM_POWERPC_PGTABLE_PPC64_4K_H
#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
#define _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H
/*
* Entries per page directory level. The PTE level must use a 64b record
* for each page table entry. The PMD and PGD level use a 32b record for
......@@ -89,4 +89,4 @@ extern struct page *pgd_page(pgd_t pgd);
#define remap_4k_pfn(vma, addr, pfn, prot) \
remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
#endif /* _ASM_POWERPC_PGTABLE_PPC64_4K_H */
#endif /* _ _ASM_POWERPC_NOHASH_64_PGTABLE_4K_H */
#ifndef _ASM_POWERPC_PGTABLE_PPC64_64K_H
#define _ASM_POWERPC_PGTABLE_PPC64_64K_H
#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
#define _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H
#include <asm-generic/pgtable-nopud.h>
......@@ -41,4 +41,4 @@
#define pgd_pte(pgd) (pud_pte(((pud_t){ pgd })))
#define pte_pgd(pte) ((pgd_t)pte_pud(pte))
#endif /* _ASM_POWERPC_PGTABLE_PPC64_64K_H */
#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_64K_H */
#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
#define _ASM_POWERPC_PGTABLE_PPC64_H_
#ifndef _ASM_POWERPC_NOHASH_64_PGTABLE_H
#define _ASM_POWERPC_NOHASH_64_PGTABLE_H
/*
* This file contains the functions and defines necessary to modify and use
* the ppc64 hashed page table.
*/
#ifdef CONFIG_PPC_64K_PAGES
#include <asm/pgtable-ppc64-64k.h>
#include <asm/nohash/64/pgtable-64k.h>
#else
#include <asm/pgtable-ppc64-4k.h>
#include <asm/nohash/64/pgtable-4k.h>
#endif
#include <asm/barrier.h>
......@@ -18,7 +18,7 @@
* Size of EA range mapped by our pagetables.
*/
#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
#define PGTABLE_RANGE (ASM_CONST(1) << PGTABLE_EADDR_SIZE)
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
......@@ -97,7 +97,7 @@
/*
* Include the PTE bits definitions
*/
#include <asm/pte-book3e.h>
#include <asm/nohash/pte-book3e.h>
#include <asm/pte-common.h>
#ifdef CONFIG_PPC_MM_SLICES
......@@ -637,4 +637,4 @@ static inline int pmd_move_must_withdraw(struct spinlock *new_pmd_ptl,
return true;
}
#endif /* __ASSEMBLY__ */
#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
#endif /* _ASM_POWERPC_NOHASH_64_PGTABLE_H */
#ifndef _ASM_POWERPC_PGTABLE_BOOK3E_H
#define _ASM_POWERPC_PGTABLE_BOOK3E_H
#ifndef _ASM_POWERPC_NOHASH_PGTABLE_H
#define _ASM_POWERPC_NOHASH_PGTABLE_H
#if defined(CONFIG_PPC64)
#include <asm/pgtable-ppc64.h>
#include <asm/nohash/64/pgtable.h>
#else
#include <asm/pgtable-ppc32.h>
#include <asm/nohash/32/pgtable.h>
#endif
#ifndef __ASSEMBLY__
......
#ifndef _ASM_POWERPC_PTE_BOOK3E_H
#define _ASM_POWERPC_PTE_BOOK3E_H
#ifndef _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
#define _ASM_POWERPC_NOHASH_PTE_BOOK3E_H
#ifdef __KERNEL__
/* PTE bit definitions for processors compliant to the Book3E
......@@ -84,4 +84,4 @@
#endif
#endif /* __KERNEL__ */
#endif /* _ASM_POWERPC_PTE_FSL_BOOKE_H */
#endif /* _ASM_POWERPC_NOHASH_PTE_BOOK3E_H */
......@@ -15,7 +15,7 @@ struct mm_struct;
#ifdef CONFIG_PPC_BOOK3S
#include <asm/book3s/pgtable.h>
#else
#include <asm/pgtable-book3e.h>
#include <asm/nohash/pgtable.h>
#endif /* !CONFIG_PPC_BOOK3S */
#ifndef __ASSEMBLY__
......
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