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    ARM: OMAP5+: dpll: support Duty Cycle Correction(DCC) · ce369a54
    Andrii Tseglytskyi 提交于
    Duty Cycle Correction(DCC) needs to be enabled if the MPU is to run at
    frequencies beyond 1.4GHz for OMAP5, DRA75x, DRA72x.
    
    MPU DPLL has a limitation on the maximum frequency it can be locked
    at. Duty Cycle Correction circuit is used to recover a correct duty
    cycle for achieving higher frequencies (hardware internally switches
    output to M3 output(CLKOUTHIF) from M2 output (CLKOUT)).
    
    For further information, See the note on OMAP5432 Technical Reference
    Manual(SWPU282U) chapter 3.6.3.3.1 "DPLLs Output Clocks Parameters",
    and also the "OMAP543x ES2.0 DM Operating Conditions Addendum v0.5"
    chapter 2.1 "Micro Processor Unit (MPU)". Equivalent information is
    present in relevant DRA75x, 72x documentation(SPRUHP2E, SPRUHI2P).
    Signed-off-by: NAndrii Tseglytskyi <andrii.tseglytskyi@ti.com>
    Signed-off-by: NTaras Kondratiuk <taras@ti.com>
    Signed-off-by: NJ Keerthy <j-keerthy@ti.com>
    Signed-off-by: NNishanth Menon <nm@ti.com>
    [t-kristo@ti.com: added TRM / DM references for DCC clock rate]
    Signed-off-by: NTero Kristo <t-kristo@ti.com>
    ce369a54
ti.h 12.5 KB