• N
    CLK: TI: dpll: support OMAP5 MPU DPLL that need special handling for higher frequencies · b4be0189
    Nishanth Menon 提交于
    MPU DPLL on OMAP5, DRA75x, DRA72x has a limitation on the maximum
    frequency it can be locked at. Duty Cycle Correction circuit is used
    to recover a correct duty cycle for achieving higher frequencies
    (hardware internally switches output to M3 output(CLKOUTHIF) from M2
    output (CLKOUT)).
    
    So provide support to setup required data to handle Duty cycle by
    the setting up the minimum frequency for DPLL. 1.4GHz is common
    for all these devices and is based on Technical Reference Manual
    information for OMAP5432((SWPU282U) chapter 3.6.3.3.1 "DPLLs Output
    Clocks Parameters", and equivalent information from DRA75x, DRA72x
    documentation(SPRUHP2E, SPRUHI2P).
    Signed-off-by: NNishanth Menon <nm@ti.com>
    [t-kristo@ti.com: updated for latest dpll init API call]
    Signed-off-by: NTero Kristo <t-kristo@ti.com>
    b4be0189
dpll.c 16.7 KB