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    MIPS: init upper 64b of vector registers when MSA is first used · c9017757
    Paul Burton 提交于
    When a task first makes use of MSA we need to ensure that the upper
    64b of the vector registers are set to some value such that no
    information can be leaked to it from the previous task to use MSA
    context on the CPU. The architecture formerly specified that these
    bits would be cleared to 0 when a scalar FP instructions wrote to the
    aliased FP registers, which would have implicitly handled this as the
    kernel restored scalar FP context. However more recent versions of the
    specification now state that the value of the bits in such cases is
    unpredictable. Initialise them explictly to be sure, and set all the
    bits to 1 rather than 0 for consistency with the least significant
    64b.
    Signed-off-by: NPaul Burton <paul.burton@imgtec.com>
    Cc: linux-mips@linux-mips.org
    Patchwork: https://patchwork.linux-mips.org/patch/7497/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    c9017757
asmmacro.h 10.0 KB