• V
    drm/i915: Clean up CHV lane soft reset programming · a8f327fb
    Ville Syrjälä 提交于
    Currently we release the lane soft reset before lane stagger settings
    have been programmed. I believe that means we don't actually do lane
    staggering. So move the soft reset deassert to happen after lane
    staggering has been programmed.
    
    The one confusing thing in this is that when we remove the power down
    override from the lanes, they power up with defaul register values,
    which do not have the soft reset overrides enabled. And according to
    some docs by default the data lane resets are tied to cmnreset. So that
    would mean that lanes would come out of reset without staggering as
    soon as the power down overrides are removed. But since we can't access
    either the lane stagger register nor the soft reset override registers
    until the lanes are powered on, we can't really do anything about it.
    So let's just set the soft reset overrides as soon as the lane is
    powered on and hope for the best.
    
    v2: Fix typos in commit message (Daniel)
    Signed-off-by: NVille Syrjälä <ville.syrjala@linux.intel.com>
    Reviewed-by: NDeepak S <deepak.s@linux.intel.com>
    Signed-off-by: NDaniel Vetter <daniel.vetter@ffwll.ch>
    a8f327fb
intel_dp.c 174.2 KB