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    MIPS: Malta: Make GIC FDC IRQ workaround Malta specific · 6249ecbb
    James Hogan 提交于
    Wider testing reveals that the Fast Debug Channel (FDC) interrupt is
    routed through the GIC just fine on Pistachio SoC, even though it
    contains interAptiv cores. Clearly the FDC interrupt routing problems
    previously observed on interAptiv and proAptiv cores are specific to the
    Malta FPGA bitstreams.
    
    Move the workaround for interAptiv and proAptiv out of
    gic_get_c0_fdc_int() in the GIC irqchip driver into Malta's
    get_c0_fdc_int() platform callback, to allow the Pistachio SoC to use
    the FDC interrupt.
    Signed-off-by: NJames Hogan <james.hogan@imgtec.com>
    Cc: Ralf Baechle <ralf@linux-mips.org>
    Cc: Andrew Bresticker <abrestic@chromium.org>
    Cc: Thomas Gleixner <tglx@linutronix.de>
    Cc: Jason Cooper <jason@lakedaemon.net>
    Cc: linux-mips@linux-mips.org
    Reviewed-by: NAndrew Bresticker <abrestic@chromium.org>
    Cc: James Hartley <james.hartley@imgtec.com>
    Patchwork: http://patchwork.linux-mips.org/patch/9748/Signed-off-by: NRalf Baechle <ralf@linux-mips.org>
    6249ecbb
irq-mips-gic.c 21.3 KB