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    PCI: add quirk for non-symmetric-mode irq routing to versions 0 and 4 of the MCP55 northbridge · 66db60ea
    Neil Horman 提交于
    A long time ago I worked on a RHEL5 bug in which kdump hung during boot
    on a set of systems.  The systems hung because they never received timer
    interrupts during calibrate_delay.  These systems also all had Opteron
    processors on a hypertransport bus, bridged to a pci bus via an Nvidia
    MCP55 northbridge chip.  After much wrangling I managed to learn from
    Nvidia that they have an undocumented register in some versions of that
    chip which control how legacy interrupts are send to the cpu complex
    when the ioapic isn't active.  Nvidia defaults this register to only
    send legacy interrupts to the BSP, so if kdump happens to boot on an AP,
    we never get timer interrupts and boom.  I had initially used this quirk
    as a workaround, with my intent being to move apic initalization to an
    earlier point in the boot process, so the setting of the register would
    be irrelevant.  Given the work involved in doing that however, the
    fragile nature of the apic initalization code, and the fact that, over
    the 2 years since we found this bug, the MCP55 is the only chip which
    seems to have this issue, I've figure at this point its likely safer to
    just carry the quirk around.  By setting the referenced bits in this
    hidden register, interrupts will be broadcast to all cpus when the
    ioapic isn't active on the above described systems.
    Acked-by: NSimon Horman <horms@verge.net.au>
    Acked-by: NVivek Goyal <vgoyal@redhat.com>
    Signed-off-by: NNeil Horman <nhorman@tuxdriver.com>
    Signed-off-by: NJesse Barnes <jbarnes@virtuousgeek.org>
    66db60ea
pci_ids.h 107.7 KB