Add Coresight CPU debug nodes for Juno r0, r1 & r2. The CPU
debug areas are mapped at the same address for all revisions,
like the ETM, even though the CPUs have changed from r1 to r2.

Cc: Leo Yan <leo.yan@linaro.org>
Cc: Mathieu Poirier <mathieu.porier@linaro.org>
Cc: Liviu Dudau <liviu.dudau@arm.com>
Signed-off-by: NSuzuki K Poulose <suzuki.poulose@arm.com>
[arranged nodes in ascending order with respect to register addresses]
Signed-off-by: NSudeep Holla <sudeep.holla@arm.com>