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由 Amit Kucheria 提交于
There are two banks of registers for v2 TSENS IPs: SROT and TM. On older SoCs these were contiguous, leading to DTs mapping them as one register address space of size 0x2000. In newer SoCs, these two banks are not contiguous anymore. Add logic to init_common() to differentiate between old and new DTs and adjust associated offsets for the TM register bank so that the old DTs will continue to function correctly. Signed-off-by: NAmit Kucheria <amit.kucheria@linaro.org> Reviewed-by: NBjorn Andersson <bjorn.andersson@linaro.org> Tested-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NMatthias Kaehlcke <mka@chromium.org> Reviewed-by: NDouglas Anderson <dianders@chromium.org> Signed-off-by: NEduardo Valentin <edubezval@gmail.com>
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