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    perf, x86, nmi: Move LVT un-masking into irq handlers · 2bce5dac
    Don Zickus 提交于
    It was noticed that P4 machines were generating double NMIs for
    each perf event.  These extra NMIs lead to 'Dazed and confused'
    messages on the screen.
    
    I tracked this down to a P4 quirk that said the overflow bit had
    to be cleared before re-enabling the apic LVT mask.  My first
    attempt was to move the un-masking inside the perf nmi handler
    from before the chipset NMI handler to after.
    
    This broke Nehalem boxes that seem to like the unmasking before
    the counters themselves are re-enabled.
    
    In order to keep this change simple for 2.6.39, I decided to
    just simply move the apic LVT un-masking to the beginning of all
    the chipset NMI handlers, with the exception of Pentium4's to
    fix the double NMI issue.
    
    Later on we can move the un-masking to later in the handlers to
    save a number of 'extra' NMIs on those particular chipsets.
    
    I tested this change on a P4 machine, an AMD machine, a Nehalem
    box, and a core2quad box.  'perf top' worked correctly along
    with various other small 'perf record' runs.  Anything high
    stress breaks all the machines but that is a different problem.
    
    Thanks to various people for testing different versions of this
    patch.
    Reported-and-tested-by: NShaun Ruffell <sruffell@digium.com>
    Signed-off-by: NDon Zickus <dzickus@redhat.com>
    Cc: Cyrill Gorcunov <gorcunov@gmail.com>
    Link: http://lkml.kernel.org/r/1303900353-10242-1-git-send-email-dzickus@redhat.comSigned-off-by: NIngo Molnar <mingo@elte.hu>
    CC: Cyrill Gorcunov <gorcunov@gmail.com>
    2bce5dac
perf_event_intel.c 39.3 KB